PD70F3416 PD703416 PD70F3417 PD703417 U18349EE2V2UM00 V850E/ V850E/DJ3 - Datasheet Archive

 

V850E/Dx3 - DG3 32-bit Single-Chip Microcontroller Hardware µPD70F3416, µPD703416 µPD70F3417, µPD703417

 

Preliminary User's Manual V850E/Dx3 - DG3 32-bit Single-Chip Microcontroller Hardware µPD70F3416 PD70F3416, µPD703416 PD703416 µPD70F3417 PD70F3417, µPD703417 PD703417 Document No. U18349EE2V2UM00 U18349EE2V2UM00 Date Published 9/12/08 NEC Electronics 2006 Printed in Germany 2 V850E/Dx3 - DG3 Preliminary User's Manual Notes for CMOS Devices (1) Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) Handling of unused input pins for CMOS No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) Status before initialization of MOS devices Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. User's Manual U18349EE2V2UM00 U18349EE2V2UM00 3 Legal Notes · The information in this document is current as of . The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, firecontainment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. 4 User's Manual U18349EE2V2UM00 U18349EE2V2UM00 The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application. Note 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. 2. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). User's Manual U18349EE2V2UM00 U18349EE2V2UM00 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: · · · · · Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) · Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044 4355111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554,| U.S.A. Tel: 408 5886000 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 0472 Düsseldorf, Germany Tel: 0211 65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: 010 82351155 http://www.cn.necel.com/ United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908 691133 Succursale Française 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cédex France Tel: 01 30675800 Sucursal en España Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091 5042787 Tyskland Filial Täby Centrum Entrance S (7th floor) 18322 Täby, Sweden Tel: 08 6387200 NEC Electronics Shanghai Ltd. Room 2511-2512, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai 200120, P.R. China Tel: 021 58885400 http://www.cn.necel.com/ NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886 9318 http://www.hk.necel.com/ NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R.O.C. Tel: 02 27192377 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02 667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven, The Netherlands Tel: 040 2654010 6 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253 8311 http://www.sg.necel.com/ NEC Electronics Korea Ltd. 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 http://www.kr.necel.com/ User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Preface Readers This manual is intended for users who want to understand the functions of the concerned microcontrollers. Purpose This manual presents the hardware manual for the concerned microcontrollers. Organization Module instances Legend Note Caution Numeric notation: Prefixes Register contents: Diagrams This system specification describes the following sections: · Pin function · CPU function · Internal peripheral function These microcontrollers may contain several instances of a dedicated module. In general the different instances of such modules are identified by the index "n", where "n" counts from 0 to the number of instances minus one. Symbols and notation are used as follows: · Weight in data notation: Left is high order column, right is low order column · Active low notation: xxx (pin or signal name is over-scored) or /xxx (slash before signal name) · Memory map address: High order at high stage and low order at low stage Additional remark or tip Item deserving extra attention · Binary: · Decimal: · Hexadecimal: xxxx or xxxB xxxx xxxxH or 0x xxxx representing powers of 2 (address space, memory capacity): · K (kilo): 210 = 1024 · M (mega): 220 = 10242 = 1,048,576 · G (giga): 230 = 10243 = 1,073,741,824 X, x = don't care Block diagrams do not necessarily show the exact wiring in hardware but the functional structure. Timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation. Further Information For further information see http://www.eu.necel.com. User's Manual U18349EE2V2UM00 U18349EE2V2UM00 7 8 User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 Product Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.3 Noise elimination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2 Port Group Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.2 Pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.3 Pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.4 Configuration of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.5 Alternative input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3 Port Types Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 Port Group Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.4.1 Port group configuration lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.2 Alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.3 Port group 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.4 Port group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.5 Port group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4.6 Port group 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4.7 Port group 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.8 Port group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.4.9 Port group 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.4.10 Port group 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.4.11 Port group 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.4.12 Port group 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.13 Port group 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.14 Port group 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.4.15 Port group 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.5 Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.5.1 Analog filtered inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.5.2 Digitally filtered inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.6 Pin Functions in Reset and Power Save Modes. . . . . . . . . . . . 71 2.7 Recommended Connection of unused Pins . . . . . . . . . . . . . . . 72 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 9 Table of Contents 2.8 Package Pins Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Chapter 3 CPU System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2.1 General purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3.2 Flash programming mode (flash memory devices only) . . . . . . . . . . . . . . . . 87 3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.1 CPU address space and physical address space . . . . . . . . . . . . . . . . . . . . . 87 3.4.2 Program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.5.1 Memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.5.2 Recommended use of data address space. . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.6 Write Protected Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.7 Instructions and Data Access Times . . . . . . . . . . . . . . . . . . . . . . 96 Chapter 4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.1.2 Clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.1.3 Power save modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.1.4 Start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.1.5 Start-up guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2 Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.1 General Clock Generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.2 SSCG control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.3 SCPS - SSCG post scaler control register . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.2.4 Control registers for peripheral clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2.5 Control registers for power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.2.6 Clock monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3.1 Power save modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3.2 Clock Generator state transistions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.3.3 Power save mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.3.4 CPU operation after power save mode release . . . . . . . . . . . . . . . . . . . . . 153 4.4 Clock Generator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.4.1 4.4.2 Watch Timer and Watch Calibration Timer clocks . . . . . . . . . . . . . . . . . . . 156 4.4.3 10 Ring and sub oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Clock output FOUTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents 4.4.4 Default Clock Generator setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4.4.5 Operation of the Clock Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Chapter 5 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.1.1 Flash memory address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.1.2 Flash memory erasure and rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.1.3 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.1.4 Boot block swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.2 Flash Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.2.1 Flash self-programming registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.2.2 Interrupt handling during flash self-programming . . . . . . . . . . . . . . . . . . . . 166 5.3 Flash Programming with Flash Programmer. . . . . . . . . . . . . . 167 5.3.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.3.2 Communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.3.3 Pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.4 Programming method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Chapter 6 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.3 Non-maskable interrupt status flag (NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.2.4 NMI0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.3.4 xxIC - Maskable interrupts control register . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.3.5 IMR0 to IMR5 - Interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.3.6 ISPR - In-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.8 External maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.9 Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.4 Edge and Level Detection Configuration . . . . . . . . . . . . . . . . . 201 6.5 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.5.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.5.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.5.3 Exception status flag (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.6 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.6.1 Illegal opcode definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.6.2 Debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 11 Table of Contents 6.7 Multiple Interrupt Processing Control . . . . . . . . . . . . . . . . . . . . 208 6.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.9 Periods in Which Interrupts Are Not Acknowledged . . . . . . 211 Chapter 7 Bus Control Unit (BCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.2 Peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 7.2.1 Fixed peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 7.2.2 Programmable peripheral I/O area (PPA) . . . . . . . . . . . . . . . . . . . . . . . . . . 215 7.2.3 NPB access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 7.3 Boundary operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.4 BCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Chapter 8 ROM Correction Function (ROMC) . . . . . . . . . . . . . . . . . . 221 8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 8.2 "Data Replacement" ROM Correction Unit. . . . . . . . . . . . . . . . 222 8.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8.2.2 "Data Replacement" ROM correction operation . . . . . . . . . . . . . . . . . . . . . 223 8.2.3 Setting of ROM correction addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.2.4 "Data Replacement" ROM correction registers . . . . . . . . . . . . . . . . . . . . . . 228 Chapter 9 Code Protection and Security . . . . . . . . . . . . . . . . . . . . . . . 239 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 9.2 Flash Writer and Self-Programming Protection . . . . . . . . . . . 240 9.3 Additional Firmware Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.3.1 ID-field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.3.2 Checksum calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.3.3 Variable reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Chapter 10 16-bit Timer/Event Counter P (TMP) . . . . . . . . . . . . . . . . 243 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 10.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 10.4 TMP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 10.5.1 10.5.2 External event count mode (TPnMD2 to TPnMD0 = 001). . . . . . . . . . . . . . 266 10.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010) . . . . . . . 275 10.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 = 011) . . . . . . . . . . . . 286 10.5.5 PWM output mode (TPnMD2 to TPnMD0 = 100) . . . . . . . . . . . . . . . . . . . . 293 10.5.6 12 Interval timer mode (TPnMD2 to TPnMD0 = 000). . . . . . . . . . . . . . . . . . . . 257 Free-running timer mode (TPnMD2 to TPnMD0 = 101) . . . . . . . . . . . . . . . 302 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents 10.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) . . . . . . . . . 319 10.5.8 Timer output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 10.6 Operating Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 10.6.1 Capture operation in pulse width measurement and free-running mode . . 326 10.6.2 Count jitter for PCLK4 to PCLK7 count clocks . . . . . . . . . . . . . . . . . . . . . . 326 Chapter 11 16-bit Interval Timer Z (TMZ) . . . . . . . . . . . . . . . . . . . . . . . . . 327 11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 11.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 11.1.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 11.2 TMZ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 11.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 11.3.1 Steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 11.3.2 Timer start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Chapter 12 16-bit Multi-Purpose Timer G (TMG) . . . . . . . . . . . . . . . . 337 12.1 Features of Timer G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.2 Function Overview of Each Timer Gn. . . . . . . . . . . . . . . . . . . . . 338 12.3 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 12.4 TMG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 12.5 Output Delay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.6 Explanation of Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.7 Operation in Free-Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 12.8 Match and Clear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.9 Edge Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 12.10 Precautions Timer Gn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Chapter 13 Watch Timer (WT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 13.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 13.2 Watch Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.3 Watch Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.3.1 Timing of steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.3.2 Watch Timer start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.4 Watch Calibration Timer Registers . . . . . . . . . . . . . . . . . . . . . . . 389 13.5 Watch Calibration Timer Operation . . . . . . . . . . . . . . . . . . . . . . . 394 Chapter 14 Watchdog Timer (WDT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 397 13 Table of Contents 14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.3 Watchdog Timer clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.1.4 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 14.2 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Chapter 15 Asynchronous Serial Interface (UARTA) . . . . . . . . . . . 407 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 15.3 UARTA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 15.4 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 15.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.5.1 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.5.2 SBF transmission/reception format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 15.5.3 SBF transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 15.5.4 SBF reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 15.5.5 UART transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 15.5.6 Continuous transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 15.5.7 UART reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 15.5.8 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 15.5.9 Parity types and operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 15.5.10 Receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 15.6 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.6.1 Baud Rate Generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.6.2 Baud Rate Generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 15.6.3 Baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.6.4 Baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.6.5 Baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.6.6 Allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . 435 15.6.7 Baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.7.1 UARTAn behaviour during and after power save mode . . . . . . . . . . . . . . . 438 15.7.2 UARTAn behaviour during debugger break . . . . . . . . . . . . . . . . . . . . . . . . 438 15.7.3 UARTAn operation stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Chapter 16 Clocked Serial Interface (CSIB) . . . . . . . . . . . . . . . . . . . . . 441 16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 16.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 16.3 CSIB Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 16.4.1 14 Single transfer mode (master mode, transmission/reception mode). . . . . . 452 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents 16.4.2 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . 454 16.4.3 Continuous mode (master mode, transmission/reception mode) . . . . . . . . 455 16.4.4 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 456 16.4.5 Continuous reception mode (error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.4.6 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . 458 16.4.7 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . 460 16.4.8 Clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.5 Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 16.6 Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 16.7 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 16.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 16.7.2 Baud Rate Generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 16.7.3 Baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 16.8 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 16.8.1 CSIBn behaviour during debugger break . . . . . . . . . . . . . . . . . . . . . . . . . . 473 16.8.2 CSIB operation stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Chapter 17 I2C Bus (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 17.2 I2C Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 17.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.4 IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.5 I2C Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 17.6 I2C Bus Definitions and Control Methods . . . . . . . . . . . . . . . . . 496 17.6.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.6.2 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 17.6.3 Transfer direction specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 17.6.4 Acknowledge signal (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 17.6.5 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 17.6.6 17.7 Wait signal (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 I2C Interrupt Request Signals (INTIICn) . . . . . . . . . . . . . . . . . . . 503 17.7.1 Master device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.7.2 Slave device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.7.3 Slave device operation (when receiving extension code) . . . . . . . . . . . . . . 510 17.7.4 Operation without communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) . . . . . . 514 17.7.6 Operation when arbitration loss occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 17.8 Interrupt Request Signal (INTIICn) . . . . . . . . . . . . . . . . . . . . . . . . 521 17.9 Address Match Detection Method . . . . . . . . . . . . . . . . . . . . . . . . 522 17.10 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 17.11 Extension Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 15 Table of Contents 17.12 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 17.13 Wakeup Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 17.14 Communication Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 17.14.1 Communication reservation function is enabled (IICFn.IICRSVn bit = 0) . . 526 17.14.2 Communication reservation function is disabled (IICFn.IICRSVn bit = 1). . 530 17.15 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 17.16 Communication Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 17.16.1 Master operation with communication reservation . . . . . . . . . . . . . . . . . . . 532 17.16.2 Master operation without communication reservation . . . . . . . . . . . . . . . . . 533 17.16.3 Slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 17.17 Timing of Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . 538 Chapter 18 CAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 18.1.1 Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 18.1.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 18.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 18.2.1 Frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 18.2.2 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 18.2.3 Data frame and remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 18.2.4 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 18.2.5 Overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 18.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 18.3.1 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 18.3.2 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 18.3.3 Multi masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 18.3.4 Multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 18.3.5 CAN sleep mode/CAN stop mode function . . . . . . . . . . . . . . . . . . . . . . . . . 560 18.3.6 Error control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 18.3.7 Baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 18.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . 570 18.5 Internal Registers of CAN Controller . . . . . . . . . . . . . . . . . . . . . 571 18.5.1 CAN module register and message buffer addresses . . . . . . . . . . . . . . . . 571 18.5.2 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.5.3 CAN registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 18.5.4 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 18.6 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 18.7 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 18.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 18.8.1 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 18.8.3 16 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 18.8.2 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents 18.8.4 Transition from initialization mode to operation mode. . . . . . . . . . . . . . . . . 618 18.8.5 Resetting error counter CnERC of CAN module. . . . . . . . . . . . . . . . . . . . . 619 18.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 18.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 18.9.2 Receive data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 18.9.3 Receive history list function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 18.9.4 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 18.9.5 Multi buffer receive block function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 18.9.6 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 18.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 18.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 18.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 18.10.3 Automatic block transmission (ABT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 18.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 18.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 18.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 18.11.1 CAN sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 18.11.2 CAN stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 18.11.3 Example of using power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 18.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 18.13 Diagnosis Functions and Special Operational Modes. . . . . 642 18.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 18.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 18.13.3 Self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 18.13.4 Receive/transmit operation in each operation mode. . . . . . . . . . . . . . . . . . 645 18.14 Time Stamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 18.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 18.15 Baud Rate Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 18.15.1 Baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 18.15.2 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . 651 18.16 Operation of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Chapter 19 A/D Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 19.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 19.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 19.3 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 19.4.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 19.4.2 Trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 19.4.3 Operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 19.4.4 Power-fail compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 19.5 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 17 Table of Contents 19.6 How to Read A/D Converter Characteristics Table . . . . . . . . 704 Chapter 20 Stepper Motor Controller/Driver (Stepper-C/D) . . . . 709 20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 20.1.1 Driver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 20.2 33Stepper Motor Controller/Driver Registers . . . . . . . . . . . . . 712 20.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 20.3.1 Stepper Motor Controller/Driver operation . . . . . . . . . . . . . . . . . . . . . . . . . 717 20.4 four3Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 20.4.1 Timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 20.4.2 Automatic PWM phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Chapter 21 LCD Controller/Driver (LCD-C/D) . . . . . . . . . . . . . . . . . . . . 723 21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 21.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 21.1.2 LCD panel addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 21.2 LCD-C/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 21.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 21.3.1 Common signals and segment signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 21.3.2 Activation of LCD segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 21.4 Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 Chapter 22 Sound Generator (SG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 22.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 22.1.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 22.2 Sound Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 22.3 Sound Generator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 22.3.1 Generating the tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 22.3.2 Generating the volume information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 22.4 Sound Generator Application Hints . . . . . . . . . . . . . . . . . . . . . . 753 22.4.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 22.4.2 Start and stop sound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 22.4.3 Change sound volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 22.4.4 INTSG0 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 22.4.5 Constant sound volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 22.4.6 Generate special sounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Chapter 23 Power Supply Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 23.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 18 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Table of Contents 23.3 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Chapter 24 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 24.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 24.1.1 General reset performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 24.1.2 Reset at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 24.1.3 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 24.1.4 Reset by Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 24.1.5 Reset by Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 24.1.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 24.2 Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 Appendix 25 Registers Access Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 Appendix 26 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 779 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 19 Table of Contents 20 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Chapter 1 Introduction V850E/Dx3 series The V850E/Dx3 is a product series in NEC Electronics' V850 family of singlechip microcontrollers designed for automotive applications. Beside the V850E/ V850E/ Dx3 - DG3 the poduct series comprises the V850E/DJ3 V850E/DJ3 and V850E/DL3 V850E/DL3 devices. For further information about V850E/DJ3 V850E/DJ3 and V850E/DL3 V850E/DL3 refer to the user's manual "V850E/Dx3 - DJ3/DL3" Document number U17566EE U17566EE 1.1 General The V850E/Dx3 - DG3 single-chip microcontroller devices make the performance gains attainable with 32-bit RISC-based controllers available for embedded control applications. The integrated V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs. The V850E/Dx3 - DG3 provide an excellent combination of general purpose peripheral functions, like serial communication interfaces (UARTs, Clocked Serial Interfaces), timers, and measurement inputs (A/D Converter), with dedicated CAN network support. The devices offer specific power-saving modes to manage the power consumption effectively under varying conditions. Thus equipped, the V850E/Dx3 - DG3 product line is ideally suited for automotive applications, like dashboard or body. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required. (1) V850E V850E CPU The V850E V850E CPU core is a RISC processor. Through the use of basic instructions that can be executed in one clock period combined with an optimized pipeline architecture, it achieves marked improvements in instruction execution speed. In addition, to make it ideal for use in digital control applications, a 32-bit hardware multiplier enables this CPU to support multiply instructions, saturated multiply instructions, bit operation instructions, etc. Through two-byte basic instructions and instructions compatible with high level languages, the object code efficiency in a C compiler is increased, and program size can be reduced. Further, because the on-chip interrupt controller provides high-speed interrupt response and processing, this device is well suited for high level real-time control applications. (2) On-chip flash memory The V850E/Dx3 - DG3 microcontrollers have on-chip flash memory. It is possible to program the controllers directly in the target environment where they are mounted. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 21 Chapter 1 Introduction With this feature, system development time can be reduced and system maintainability after shipping can be markedly improved. (3) A full range of software development tools A development system is available that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements. 1.2 Features Summary The following table provides a quick summary of the most outstanding features. Table 1-1 V850E/Dx3 - DG3 features summary (1/3) CPU Core V850E1 V850E1 Number of instructions 81 Minimum instruction execution time 41.667 ns (@ = 24 MHz) General registers 32 registers (32 bits each) Instruction set V850E V850E (compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed) Signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format Signed load instructions Internal flash memory Size · 256 KB (µPD70F3417 PD70F3417) · 128 KB (µPD70F3416 PD70F3416) Flash protection external programmer security function Secure self programming Internal mask ROM memory Size · 256 KB (µPD703417 PD703417) · 128 KB (µPD703416 PD703416) Internal data RAM Size 22 · 12 KB (µPD70(F)3417) · 6 KB (µPD70(F)3416) Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Introduction Table 1-1 Chapter 1 V850E/Dx3 - DG3 features summary (2/3) Clock Generator Internal spread-spectrum PLL 16 MHz ± 5 % Internal PLL (peripheral clock supply) 8-fold PLL CPU frequency range up to 24 MHz Peripheral frequency range up to 16 MHz Main crystal frequency range (main oscillator) 4 MHz Sub oscillator 32 KHz (typ.) Ring oscillator 240 KHz (typ.) Clock supervision 2 channels: · main oscillator monitor · sub oscillator monitor Auxiliary frequency output Built-in power saving modes HALT / IDLE / WATCH / Sub-WATCH / STOP I/O ports Input/output ports 72 Input ports 8 A/D Converter Number of channels 8 Resolution 10-bit Conversion modes · · · · Continuous select mode Continuous scan mode Timer trigger mode Software trigger mode Analog input channels shared with digital input port functionality Serial interfaces Synchroneous: CSI (CSIB) 2 channels Asynchroneous: UART (UARTA) 2 channels with LIN support I2C 1 channel (IIC) CAN (CAN) 1 channel with 32 message buffer Timers 16-bit multi purpose timer/event counter (TMP) 1 channel 16-bit multi purpose timer/counter (TMG) 2 channel 16-bit multi purpose timer/counter (TMZ) 6 channels Watch Timer (WT) 1 channel Watch Calibration Timer (WCT) 1 channel Watchdog Timer (WDT) 1 channel LCD Controller/Driver Segment signal output max. 40 Common signal output max. 4 Modes 1/4 duty, 1/3 bias Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 23 Chapter 1 Introduction Table 1-1 V850E/Dx3 - DG3 features summary (3/3) Stepper Motor Controller/Driver Number of channels 4 Resolution 8-bit and 8-bit + 1 Sound Generator Number of channels 1 Volume 9-bit volume level accuracy Sound frequency 100 Hz to 6 KHz with min. resolution of ± 20 Hz Sound duration 256 steps Interrupts and exceptions Non-maskable interrupts 2 sources Maskable interrupts 51 Software exceptions 32 sources Exception trap 2 sources ROM Correction Number of channels 8 channels by "Data Replacement" Power supply supervision Power-On-Clear Generates reset at power-up and in case of power loss Single supply operating voltage Range 3.5 V to 5.5 V (refer to Electrical Target Specification) Temperature range Ta = ­40 to +85°C (@ = 16 MHz) Range Package Package 100-pin LQFP Package size 14 mm × 14 mm Pin pitch 0.5 mm CMOS technology Note 24 The CAN controller of this device fulfils the requirements according ISO 11898. Additionally, the CAN controller was tested according to the test procedures required by ISO 16845. The CAN controller has successfully passed all test patterns. Beyond these test patterns, other tests like robustness tests and processor interface tests as recommended by C&S/FH Wolfenbuettel have been performed with success. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Introduction Chapter 1 1.3 Product Series Overview Table 1-2 shows the common and different features of the microcontrollers. An overview of the feature differences gives Table 1-3. Table 1-2 V850E/Dx3 - DG3 product series overview Part number µPD703417 PD703417 µPD70F3416 PD70F3416 µPD703416 PD703416 Flash 256 KB none 128 KB none ROM Internal memory µPD70F3417 PD70F3417 none 256 KB none 128 KB RAM Operating clock Main oscillator with 12 KB SSCGa 6 KB 16 MHz typ., 16.8 MHz max.b Ring oscillator Sub oscillator 32 KHz typ. Input/Output 72 Input I/O ports 240 KHz typ. 8 A/D converter Timers 8 channels 2 channels WDT 1 channel Watch provided Watch calibration provided CAN 1 channel UARTA 2 channels CSIB 2 channels I2C 1 channel External 4 channels Internal 51 channels NMI 2 channels ROM Correction 6 channels Power-On-Clear Other functions 1 channels TMG Interrupts 6 channels TMP Serial interfaces TMZ provided Clock supervision 2 channels Sound Generator 1 channel Stepper Motor Controller/Driver 4 channels LCD-Controller/Driver 40 x 4 Auxiliary frequency output provided 3.5 V to 5.5 Vb Operating voltage Package a) b) 100-pin LQFP, 0.5 mm pin pitch SSCG: spread spectrum Clock Generator Refer to the Electrical Target Specification Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 25 Chapter 1 Introduction 1.4 Description Figure 1-1 provides a functional block diagram of the V850E/DG3 V850E/DG3. Power and Reset Reset NMI POC Power supply Interrupt Controller INTP0 to INTP3 CPU CPU Core Memory Note 1 ROM Correction Flash Note 3 Note 2 RAM ROM Serial Interfaces RXDA0, RXDA1 2 x UARTA TXDA0, TXDA1 SIB0, SIB1 SOB0, SOB1 SCKB0, SCKB1 CRXD0 CTXD0 SDA0 SCL0 System Controller BRG 2 x CSIB Bus Control Unit Standby Controller BRG CAN I2C Bus Bridge NPB (NEC Peripheral Bus) Control Interfaces ANI0-ANI7 10-bit ADC 8 channels Ports P00 to P03 P16 to P17 P20 to P27 P30 to P37 P43 to P47 P50 to P51 P60 to P67 P70 to P77 P80 to P83 P85 to P87 P90 to P97 P104 to P107 P120 to P127 P130 to P137 AVREF SM31 to SM34 SM41 to SM44 SM51 to SM54 Stepper Motor C/D SM61 to SM64 SGO/SGOF SGOA SEG0 to SEG39 SEG39 COM0 to COM3 Clock Generator Ring oscillator SG0 Note LCD C/D 2 Sub oscillator 16-bit Timer TMZ0 - TMZ5 Timers Main oscillator TIG01 TIG01 to TIG04 TIG04 TIG11 TIG11 to TIG14 TIG14 16-bit Timer TMG0 - TMG1 16-bit Timer WCT TOG01 to TOG04 TOG11 to TOG14 16-bit Timer WT Watch and Watch Correction Timer XT1 XT2 X1 X2 Clock Generator Spread Spectrum Clock Generator RESET FOUT PLL TIP00 TIP00, TIP01 TIP01 16-bit Timer TMP0 TOP00, TOP01 Figure 1-1 Watchdog Timer Main and sub oscillator supervision V850E/DG3 V850E/DG3 block diagram Table 1-3 summarizes the different features of the of the V850E/DG3 V850E/DG3 µPD70(F)3417 and µPD70(F)3416 microcontrollers, marked as "Notes" in Figure 1-1. 26 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Introduction Table 1-3 Chapter 1 Feature set differences Note 1 µPD70F3417 PD70F3417 µPD703417 PD703417 µPD70F3416 PD70F3416 µPD703416 PD703416 Flash 256 KB ­ 128 KB ­ 2 ROM ­ 256 KB ­ 128 KB 3 Structure of the diagram Feature RAM 12 KB 12 KB 6 KB 6 KB In the diagram, the building blocks are grouped according to their function. At the top of the diagram, you find the functions for controlling power supply and reset. The upper right-hand section shows the building blocks of the CPU system and the memory interface components. The I/O ports are summarized below that section. The left-hand section of the block diagram identifies the interfaces to peripherals and also the built-in timers. All these components are connected to and can be controlled via the internal bus. The Clock Generator, depicted in the lower right-hand section, plays a central role. It generates and monitors not only the clocks for the CPU and the peripheral interfaces, but also governs the power save modes that can be entered when the device is not in use. Structure of the manual This manual explains how to use the V850E/Dx3 - DG3 microcontroller devices. It provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions. The manual provides individual chapters for the building blocks. These chapters are organized according to the grouping in the diagram. · Core functions "Pin Functions" on page 29 "CPU System Functions" on page 75 "Clock Generator" on page 99 "Interrupt Controller (INTC)" on page 177 · Memory access "Flash Memory" on page 161 "Bus Control Unit (BCU)" on page 213 "ROM Correction Function (ROMC)" on page 221 "Code Protection and Security" on page 239 · Timers "16-bit Timer/Event Counter P (TMP)" on page 243 "16-bit Interval Timer Z (TMZ)" on page 327 "16-bit Multi-Purpose Timer G (TMG)" on page 337 "Watch Timer (WT)" on page 377 "Watchdog Timer (WDT)" on page 397 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 27 Chapter 1 Introduction · Serial interfaces "Asynchronous Serial Interface (UARTA)" on page 407 "Clocked Serial Interface (CSIB)" on page 441 "I2C Bus (IIC)" on page 475 "CAN Controller (CAN)" on page 545 · Control interfaces "A/D Converter (ADC)" on page 683 "Stepper Motor Controller/Driver (Stepper-C/D)" on page 709 "LCD Controller/Driver (LCD-C/D)" on page 723 "Sound Generator (SG)" on page 737 · Power and reset "Power Supply Scheme" on page 755 "Reset" on page 759 1.5 Ordering Information Table 1-4 V850E/DG3 V850E/DG3 ordering information NEC order code Memory size Remarks UPD703416GC UPD703416GC(A)-UEU-QS-AX 100 pin LQFP 128 KB ROM ­ UPD70F3416GC UPD70F3416GC(A)-UEU-QS-AX 100 pin LQFP 128 KB flash ­ UPD703417GC UPD703417GC(A)-UEU-QS-AX 100 pin LQFP 256 KB ROM ­ UPD70F3417GC UPD70F3417GC(A)-UEU-QS-AX 28 Pin/package 100 pin LQFP 256 KB flash ­ Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Chapter 2 Pin Functions This chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter. 2.1 Overview The microcontroller offers various pins for input/output functions, so-called ports. The ports are organized in port groups. To allocate other than general purpose input/output functions to the pins, several control registers are provided. For a description of the terms pin, port or port group, see "Terms" on page 32. Features summary · Number of ports and port groups: ­ Port groups: 13 ­ I/O ports: 72 ­ Input ports: 8 · 5V I/O: Can be used as 3V I/O with degraded electrical parameters. Please refer to the Electrical Target Specification. · 24 high-drive ports for direct stepper motor drive. · Configuration possible for individual pins. · The following features can be selected for most of the pins: ­ One out of two input thresholds ­ One out of two input characteristics (Schmitt and non-Schmitt) ­ Output current limit ­ Open drain emulation · The following registers are offered for most of the ports: ­ Direct register for reading the pin values ­ Port register with selectable read source (for improved bit set / bit clear capabilities) Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 29 Chapter 2 Pin Functions 2.1.1 Description This microcontroller has the port groups shown below. P00 to P77 P16 P80 P17 Port group 1 to P03 Port group 0 P70 to P20 P83 Port group 8 to P85 P27 Port group 2 to P30 P87 to P90 P37 Port group 3 to P43 Port group 4 to P47 Port group 5 P50 P51 P104 to P67 P120 P130 P137 30 Port groups Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Port group 12 P127 to Figure 2-1 Port group 10 P107 to to Port group 9 P97 P60 Port group 6 Port group 7 Port group 13 Pin Functions Port group overview Table 2-1 Chapter 2 Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Functions of each port group Port group name Function Port mode Alternative mode 0 · External interrupt 0 to 3 · Non maskable interrupt 1 2-bit input/output · I2C0 data/clock line 2 8-bit input/output · Timer TMG0 to TMG1 channels · LCD controller segment signal output 3 8-bit input/output · · · · 4 5-bit input/output · Clocked Serial Interface CSIB1 data/clock line · LCD controller segment signal output · CAN0 transmit/receive data 5 2-bit input/output · Sound Generator outputs · Frequency output 6 8-bit input/output · Timer TMP0 channels · LCD controller segment signal output · I2C0 data/clock line 7 8-bit input · A/D Converter input 8 7-bit input/output · · · · 9 8-bit input/output · Clocked Serial Interface CSIB1 data/clock line · LCD controller segment signal output · LCD controller common signal output 10 4-bit input/output · LCD controller segment signal output · Clocked Serial Interface CSIB0 data/clock line 12 8-bit input/output · Stepper Motor Controller/Driver outputs 13 Pin configuration 4-bit input/output 8-bit input/output · Stepper Motor Controller/Driver outputs · Timer TMG0 to TMG1 channels Timer TMP0 channels UARTA0 transmit/receive data, UARTA1 transmit/receive data LCD controller segment signal output LCD controller segment signal output Frequency output Inverted frequency output UARTA0 transmit/receive data To define the function and the electrical characteristics of a pin, several control registers are provided. · For a general description of the registers, see "Port Group Configuration Registers" on page 33. · For every port, detailed information on the configuration registers is given in "Port Group Configuration" on page 45. There are three types of control circuits, defined as port types. For a description of the port types, see "Port Types Diagrams" on page 44. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 31 Chapter 2 Pin Functions 2.1.2 Terms In this section, the following terms are used: · Pin Denotes the physical pin. Every pin is uniquely denoted by its pin number. A pin can be used in several modes. Depending on the selected mode, a pin name is allocated to the pin. · Port group Denotes a group of pins. The pins of a port group have a common set of port mode control registers. · Port mode / Port A pin in port mode works as a general purpose input/output pin. It is then called "port". The corresponding name is Pnm. For example, P07 denotes port 7 of port group 0. It is referenced as "port P07". · Alternative mode In alternative mode, a pin can work in various non-general purpose input/ output functions, for example, as the input/output pin of on-chip peripherals. The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs. Note that for example P00 and INTP0 denote the same physical pin. The different names indicate the function in which the pin is being operated. · Port type A control circuit evaluates the settings of the configuration registers. There are different types of control circuits, called "port types". 2.1.3 Noise elimination The input signals at some pins are passing a filter to remove noise and glitches. The microcontroller supports both analog and digital filters. The analog filters are always applied to the input signals, whereas the digital filters can be enabled/disabled by control registers. See "Noise Elimination" on page 67 for a detailed description. 32 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin Functions Chapter 2 2.2 Port Group Configuration Registers This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are classified in the following groups: · "Pin function configuration" on page 34 · "Pin data input/output" on page 37 · "Configuration of electrical characteristics" on page 39 · "Alternative input selection" on page 42 2.2.1 Overview For the configuration of the individual pins of the port groups, the following registers are used: Table 2-2 Registers for port group configuration Register name Shortcut Function Port mode register PMn Pin function configuration Port mode control register PMCn Port function control register PFCn Port LCD control register PLCDCn Port register Pn Port read control register PRCn Port pin read register PPRn Port drive strength control register PDSCn Port input characteristic control register PICCn Port input level control register PILCn Port open drain control register PODCn Peripheral function select register PFSR0 to PFSR3 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin data input/output Configuration of electrical characteristics Alternative input selection 33 Chapter 2 Pin Functions 2.2.2 Pin function configuration The registers for pin function configuration define the general function of a pin: · input mode or output mode · port mode or alternative mode · selection of one of the alternative output functions ALT1-OUT/ALT2-OUT · pin usage for LCD Controller/Driver output LCD_OUT An overview of the register settings is given in the table below. Table 2-3 Pin function configuration (overview) Registers Function PLCDC PMC X Alternative output 1 mode Alternative output 2 mode Alternative input mode LCD signal output (segment or common signal) 1 X I 0 O 0 O 1 I X 1 1 1 0 O X Port mode (input) 0 X 0 PM 0 Port mode (output) (1) I/O PFC X O PMn - Port mode register The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. see "Port Group Configuration" on page 45 FFH or FFFFH. This register is initialized by any reset. 7 13 12 4 3 2 1 0 PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 R/W 14 5 PMn7 15 6 R/W R/W R/W R/W R/W R/W R/W 11 10 9 PMn15 PMn14 PMn13 PMn12 PMn11 PMn10 PMn9 R/W R/W R/W R/W Table 2-4 R/W R/W 7 6 5 4 3 2 1 0 PMn8 PMn7 PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 R/W R/W R/W R/W R/W R/W R/W R/W R/W PMn register contents Bit position 7 to 0 or 15 to 0 34 R/W 8 Bit name Function PMn[7:0] Specifies input/output mode of the corresponding pin or 0: Output mode (output enabled) PMn[15:0] 1: Input mode (output disabled) Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin Functions Chapter 2 (2) PMCn - Port mode control register The PMCn register specifies whether the individual pins of port group n are in port mode or in alternative mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. see "Port Group Configuration" on page 45 00H or 0000H 0000H. This register is initialized by any reset. 7 13 12 4 3 2 1 0 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0 R/W 14 5 PMCn7 15 6 R/W R/W R/W R/W R/W R/W R/W 11 10 9 8 7 6 5 4 3 2 1 0 PMCn15 PMCn14 PMCn13 PMCn12 PMCn11 PMCn10 PMCn9 PMCn8 PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0 R/W R/W R/W R/W Table 2-5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PMCn register contents Bit position 7 to 0 or 15 to 0 (3) R/W Bit name Function PMCn[7:0] Specifies the operation mode of the corresponding pin or 0: Port mode PMC[15:0] 1: Alternative mode PFCn - Port function control register If a pin is in alternative mode and serves as an output pin (PMn.PMnm = 0) some pins offer two output functions ALT1-OUT and ALT2-OUT. The 8-bit PFCn register specifies which output function of a pin is to be used. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 PFC0: 20H other PFCn: 00H This register is initialized by any reset. 7 5 4 3 2 1 0 PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 R/W Table 2-6 6 R/W R/W R/W R/W R/W R/W R/W PFCn register contents Bit position 7 to 0 Bit name Function PFCn[7:0] Specifies the output function of the pin 0: Alternative output mode 1 (ALT1-OUT) 1: Alternative output mode 2 (ALT2-OUT) See "Port Group Configuration" on page 45 for a list of the possible output modes. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 35 Chapter 2 Pin Functions (4) PLCDCn - Port LCD control register Some port groups comprise pins for signal output of the LCD Controller Driver. For those port groups, the 8-bit PLCDCn register specifies whether an individual pin of port group n serves as an output pin of the LCD Controller/ Driver or not. Access This register can be read/written in 8-bit and 1-bit units. Address see "Port Group Configuration" on page 45 Initial Value 00H. This register is initialized by any reset. 7 5 4 3 2 1 0 PLCDCn7 PLCDCn6 PLCDCn5 PLCDCn4 PLCDCn3 PLCDCn2 PLCDCn1 PLCDCn0 R/W Table 2-7 6 R/W R/W R/W R/W R/W R/W R/W PLCDCn register contents Bit position 7 to 0 Note 36 Bit name Function Enables LCD function of the pin: 0: Pin is not allocated to the LCD Controller/Driver. Pin function is specified in PMn, PMCn and PFCn PLCDCn[7:0] 1: Pin serves as an output pin of the LCD Controller/ Driver. Data is output directly from buffers of the LCD Controller/Driver. Bit Pn.Pnm is neglected. If PLCDCn.PLCDCnm = 1, the settings of the bits m in registers PMn, PMCn, and PFCn are neglected. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin Functions Chapter 2 2.2.3 Pin data input/output If a pin is in port mode, the registers for pin data input/output specify the input and output data. (1) Pn - Port register In port mode (PMCn.PMCnm=0), data is input from or output to an external device by writing or reading the Pn register. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register. Access Address Initial Value Note This register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. see "Port Group Configuration" on page 45 00H or 0000H 0000H. This register is cleared by any reset. After reset, the ports are in input mode (PMn.PMnm = 1). The read input value is determined by the port pins. 7 6 5 4 3 2 1 0 Pn7 15 14 12 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 2 1 0 Pn15 Pn14 Pn13 Pn12 Pn11 Pn10 Pn9 Pn8 Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 13 Pn6 R/W R/W R/W Table 2-8 11 R/W 10 R/W Pn register contents Bit position 7 to 0 or 15 to 0 Note Bit name Pn[7:0] or Pn[15:0] Function Data, see Table 2-9 for details. The value written to register Pn is retained until a new value is written to register Pn. Data is written to or read from the Pn register as follows: Table 2-9 Writing/reading register Pn Function PRC PM I/O Write to Pn and output contents of Pn to pins X 0 O Write to Pn without affecting the pin status X 1 I Read from Pn and thus read the pin status 0 1 I X 0 O 1 1 I Read from Pn and disregard the pin status Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 37 Chapter 2 Pin Functions (2) PRCn - Port read control register In input mode (PMn.PMnm = 1), the 8-bit PRCn register specifies whether the pin status or the contents of register Pn are read (see also Table 2-9). Each PRCn register contains only one control bit which defines the read source of all ports of the entire port group n. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 00H. This register is cleared by any reset. 7 5 4 3 2 1 0 X X X X X X X PRCn0 R/W Table 2-10 6 R/W R/W R/W R/W R/W R/W R/W PRCn register contents Bit position Bit name 0 Note (3) Function PRCn0 Specifies which data are to be read in port group n: 0: Pin status is read 1: Contents of Pn are read If PMn.PMnm = 0, the contents of Pn are read in any case-independent of PRCn.PRCnm. PPRn - Port pin read register The PPRn register reflects the actual pin value, independent of the control registers set-up. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register. Access Address Initial Value This register is read-only, in 8-bit and 1-bit units. 16-bit registers can also be read in 16-bit units. see "Port Group Configuration" on page 45 00H or 0000H 0000H. This register is cleared by any reset. 7 13 12 4 3 2 1 0 PPRn6 PPRn5 PPRn4 PPRn3 PPRn2 PPRn1 PPRn0 R 14 5 PPRn7 15 6 R R R R R R R 11 10 9 8 7 6 5 4 3 2 1 0 PPRn15 PPRn14 PPRn13 PPRn12 PPRn11 PPRn10 PPRn9 PPRn8 PPRn7 PPRn6 PPRn5 PPRn4 PPRn3 PPRn2 PPRn1 PPRn0 R R R R Table 2-11 R R R R R R PPRn register contents Bit position 7 to 0 or 15 to 0 38 R Bit name PPRn[7:0] or PPRn[15:0] Function Actual pin value Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 R R R R R Pin Functions Chapter 2 2.2.4 Configuration of electrical characteristics The registers for the configuration of electrical characteristics are briefly described in the following. For details refer to the Electrical Target Specification. (1) PDSCn - Port drive strength control register The 8-bit PDSCn register selects the output current limiting function for high- or low-drive strength. Access Address Initial Value This register can be read/written, in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 00H. This register is cleared by any reset. 7 6 5 4 3 2 1 0 PDSCn7 PDSCn6 PDSCn5 PDSCn4 PDSCn3 PDSCn2 PDSCn1 PDSCn0 R/W Table 2-12 R/W R/W R/W R/W R/W R/W R/W PDSCn register contents Bit position Bit name 7 to 0 Function PDSCn[7:0] Specifies output current limiting function: 0: Limit 1. 1: Limit 2. For the detailed specification of "Limit 1" and "Limit 2" refer to the Electrical Target Specification. (2) PICCn - Port input characteristic control register The 8-bit PICCn register selects between Schmitt Trigger or non-Schmitt Trigger input characteristics. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 FFH. This register is cleared by any reset. 7 5 4 3 2 1 0 PICCn7 PICCn6 PICCn5 PICCn4 PICCn3 PICCn2 PICCn1 PICCn0 R/W Table 2-13 6 R/W R/W R/W R/W R/W R/W R/W PICCn register contents Bit position 7 to 0 Bit name PICCn[7:0] Function Specifies Trigger input characteristics: 0: non-Schmitt Trigger 1: Schmitt Trigger Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 39 Chapter 2 Pin Functions (3) PILCn - Port input level control register The 8-bit PILCn register selects between different input characteristics for Schmitt Trigger (PICCn.PICCnm = 1) and non-Schmitt Trigger (PICCn.PICCnm = 0). Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 00H This register is initialized by any reset. 7 5 4 3 2 1 0 PILCn7 PILCn6 PILCn5 PILCn4 PILCn3 PILCn2 PILCn1 PILCn0 R/W Table 2-14 6 R/W R/W R/W R/W R/W R/W R/W PILCn register contents Bit position 7 to 0 40 Bit name PILCn[7:0] Function Selects the input level: for Schmitt Trigger (PICCn.PICCnm = 1): 0: Schmitt 1 1: Schmitt 2 for non-Schmitt Trigger (PICCn.PICCnm = 0): 0: CMOS1 1: CMOS2 Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin Functions Chapter 2 (4) PODCn - Port open drain control register The PODCn register selects the output buffer function as push-pull or opendrain emulation. Access Address Initial Value This register can be read/written in 8-bit and 1-bit units. see "Port Group Configuration" on page 45 00H. This register is cleared by any reset. 7 6 5 4 3 2 1 0 PODCn7 PODCn6 PODCn5 PODCn4 PODCn3 PODCn2 PODCn1 PODCn0 R/W Table 2-15 R/W R/W R/W R/W R/W R/W R/W PODCn register contents Bit position 7 to 0 Bit name PODCn[7:0] Function Specifies the output buffer function: 0: push-pull 1: open drain emulation output mode If open drain emulation is enabled the output function of the concerned pin is automatically enabled as well, independently of the PMn.PMnm setting. Caution Depending on the capacitive load applied to an output pin Pnm (PMnm = 0) in open-drain emulation (PODCnm = 1) a change from low to high level may take a remarkable rise time. Hence a read of the port pin status · via the PPRn register or · Pn register with PRCn = 0 (pin status read) immediately after setting Pnm to high level may still return low level at Pnm. Particular attention is needed when a read-modify-write instruction (SET1, CLR1, NOT1) is executed after setting Pnm = 1 (with PRCn0 = 0) to manipulate another port pin of the same port group n during the rise time of the Pnm output. In this case the read of Pnm may show 0 (though it should be 1) and the 0 is written back to Pnm at the end of the read-modify-write instruction. Consequently Pnm may never reach high level at the output pin. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 41 Chapter 2 Pin Functions 2.2.5 Alternative input selection Alternative input functions of CSIB1, UARTA0, I2C0, and TMG0 are provided on two pins each. Thus you can select on which pin the alternative function should appear. For this purpose, four peripheral function select registers PFSRk (k = 0, 2, 3) are provided. Note (1) The selection of the alternative input function is done by a different circuit than the selection of the alternative output function. Therefore, the registers for selecting the alternative input functions (PFSR) are not reflected in the block diagrams of the port types in chapter "Port Types Diagrams" on page 44. PFSR0 - Peripheral function select register The 8-bit PFSR0 register selects the alternative input paths for the peripheral functions CSIB1 and I2C0. Access Address Initial Value This register can be read/written in 8-bit units. FFFF F720H F720H 01H. This register is initialized by any reset. 7 6 5 4 3 2 1 0 0 0 0 PFSR04 PFSR04 0 0 PFSR01 PFSR01 0 R/W Ra R/W R/W Ra a a R R a) Table 2-16 zzThis bit may be written, but write is ignored. PFSR0 register contents Bit position 4 1 42 Ra Bit name Function PFSR04 PFSR04 Specifies the alternative input path for I2C0: 0: SCL0 is input from P17 (SCL0_0) SDA0 is input from P16 (SDA0_0) 1: SCL0 is input from P64 (SCL0_1) SDA0 is input from P65 (SDA0_1) PFSR01 PFSR01 Specifies the alternative input path for CSIB1: 0: SCKB1 is input from P45 (SCKB1_0) SIB1 is input from P43 (SIB1_0) 1: SCKB1 is input from P92 (SCKB1_1) SIB1 is input from P90 (SIB1_1) Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Pin Functions Chapter 2 (2) PFSR2 - Peripheral function select register The 8-bit PFSR2 register selects the alternative input paths for the peripheral functions TMG0. Access Address Initial Value This register can be read/written in 8-bit units. FFFF F724H F724H 01H. This register is initialized by any reset. 7 6 5 4 3 2 1 0 0 a) Table 2-17 0 0 0 PFSR23 PFSR23 PFSR22 PFSR22 PFSR21 PFSR21 PFSR20 PFSR20 Ra Ra Ra Ra R/W R/W R/W R/W This bit may be written, but write is ignored. PFSR2 register contents Bit position Bit name PFSR23 PFSR23 0 Specifies the alternative input path for timer channel 2 of TMG0: 0: TIG02 TIG02 is input from P21 (TIG02 TIG02_0) 1: TIG02 TIG02 is input from P131 (TIG02 TIG02_1) PFSR20 PFSR20 1 Specifies the alternative input path for timer channel 3 of TMG0: 0: TIG03 TIG03 is input from P22 (TIG03 TIG03_0) 1: TIG03 TIG03 is input from P132 (TIG03 TIG03_1) PFSR21 PFSR21 2 Specifies the alternative input path for timer channel 4 of TMG0: 0: TIG04 TIG04 is input from P23 (TIG04 TIG04_0) 1: TIG04 TIG04 is input from P133 (TIG04 TIG04_1) PFSR22 PFSR22 3 (3) Function Specifies the alternative input path for timer channel 1 of TMG0: 0: TIG01 TIG01 is input from P20 (TIG01 TIG01_0) 1: TIG01 TIG01 is input from P130 (TIG01 TIG01_1) PFSR3 - Peripheral function select register The 8-bit PFSR3 register selects the alternative input paths for the peripheral functions TMG2, UARTA0 and UARTA1. Access Address Initial Value This register can be read/written in 8-bit units. FFFF F726H F726H 01H. This register is initialized by any reset. 7 6 0 0 a a R R a) Table 2-18 5 4 3 2 1 0 R/W Ra Ra Ra PFSR34 PFSR34 R/W R/W These bits may be written, but write is ignored. PFSR3 register contents Bit position 4 Bit name PFSR34 PFSR34 Function Specifies the alternative input path for UARTA0: 0: RXDA0 is input from P31 (RXDA0_0) 1: RXDA0 is input from P87 (RXDA0_1) Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 43 Chapter 2 Pin Functions 2.3 Port Types Diagrams The control circuits that evaluate the settings of the configuration registers are of different types. This chapter presents the block diagrams of all port types. (1) Port type M Note 1 PDSCnm PICCnm PILCnm Note 2 PMCnm PMnm PODCnm Note 3 ALT1-OUT 0 ALT2-OUT ENABLE PFCnm 1 1 Pnm 0 Pnm 1 0 ENABLE 0 1 PRD PRCn0 internal RESET PPRRD Note 5 ALT-IN Analog Filter Note 4 PLCDCnm Figure 2-2 44 Block diagram: port type M Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 LCDBUFEN Pin Functions Chapter 2 Note 1. The PDSC register is not provided for port groups 12 and 13. 2. The PMC register is not provided for port group 0. 3. The PFC register is not provided for port groups 0, 1, 3, 4, 6, 10 and 12. 4. The PLCDC register is not provided for port groups 0, 1, 4, 5, 12 and 13. 5. The analog filter is provided only for the external interrupt port group 0. (2) Port type B This port type holds for pins that only work in input mode. Pins of port type B are used for the corresponding alternative input function A/D converter input. At the same time, the pin status can also be read via the port register Pn, so that the pin also works in port function. PILCnm PMCnm AIN select Pnm ADC input PRD Figure 2-3 Block diagram: port type B A/D conversion of the level at Pnm is independent of any register settings. For reading the pin status via the Pn register PMCnm has to be set to 0. Since the accuracy of an A/D conversion may degrade when Pn is read during the sampling time of the A/D converter, it is recommended to disable the port pin read by PCMnm = 1 during A/D conversion. 2.4 Port Group Configuration This section provides an overview of the port groups (Table 2-19) and of the pin functions (Table 2-20 on page 49). In Table 2-53 on page 71 it is listed how the pin functions change if the microcontroller is reset or if it is in one of the standby modes. In the subsections, for every port group the settings of the configuration registers is listed. Further, the addresses and initial values of the configuration registers are given. Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 45 Chapter 2 Pin Functions 2.4.1 Port group configuration lists Table 2-19 provides an overview of the functions available at each port pin. Table 2-19 Port group list (1/3) M P02 ­ INTP2 M ­ INTP3 M P16 SDA0 SDA0 M P17 SCL0 SCL0 M TOG01/SEG0 TIG01 TIG01 M TOG02/SEG1 TIG02 TIG02 M TOG03/SEG2 TIG03 TIG03 M P23 TOG04/SEG3 TIG04 TIG04 M P24 TOG11/SEG4 TIG11 TIG11 M TOG12/SEG5 TIG12 TIG12 M TOG13/SEG6 TIG13 TIG13 M TOG14/SEG7 TIG14 TIG14 M P30 TXDA0 ­ M P31 ­ RXDA0 M P32 TXDA1/SEG31 TXDA1/SEG31 ­ M P33 SEG29 SEG29 RXDA1 M P34 TOP01/SEG8 ­ M P35 SEG9 ­ M P36 SEG10 SEG10 ­ M P37 SEG11 SEG11 ­ M P43 SEG22 SEG22 SIB1 M P44 SOB1/SEG21 SOB1/SEG21 ­ M P45 SCKB1/SEG20 SCKB1/SEG20 SCKB1 M P46 ­ CRXD0 M P47 CTXD0 ­ M P50 FOUT/SGOA ­ M P51 SGO ­ M P60 TOP00/SEG12 TIP00 TIP00 M P61 TOP01/SEG13 TIP01 TIP01 M P62 SEG14 SEG14 ­ M P63 SEG15 SEG15 ­ M P64 SCL0/SEG16 SCL0/SEG16 SCL0 M P65 SDA0/SEG17 SDA0/SEG17 SDA0 M P66 SEG18 SEG18 ­ M P67 46 INTP1 P27 6 ­ P26 5 P01 P25 4 M P22 3 INTP0/NMI P21 2 ­ P20 1 Alternative outputs Alternative ALT1_OUT/ALT2_OUT/ inputs LCD_OUT P03 0 Port name P00 Port group name SEG19 SEG19 ­ M Preliminary User's Manual U18349EE2V2UM00 U18349EE2V2UM00 Port type Pin Functions Table 2-19 Chapter 2 Port group list (2/3) ­ ANI1 B ­ ANI2 B P73 ­ ANI3 B P74 ­ ANI4 B ­ ANI5 B ­ ANI6 B P77 ­ ANI7 B P80 SEG26 SEG26 ­ M P81 SEG25 SEG25 ­ M P82 SEG24 SEG24 ­ M P83 FOUT/SEG23 FOUT/SEG23 ­ M P85 FOUT/SEG27 FOUT/SEG27 ­ M P86 TXDA0/SEG30 TXDA0/SEG30 ­ M P87 SEG28 SEG28 RXDA0 M P90 ­ SIB1/SEG36 SIB1/SEG36 M P91 SOB1/SEG37 SOB1/SEG37 ­ M P92 SCKB1/SEG38 SCKB1/SEG38