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PD703128 PD703129 V850E/CA2TM 32-/16-BIT V850E/CA2 PD703129GJ V850E/ PD703128GJ - Datasheet Archive
MOS INTEGRATED CIRCUIT µPD703128, µPD703129 V850E/CA2TM JUPITER 32-/16-BIT ROMLESS MICROCONTROLLER DESCRIPTION The
PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD703128 PD703128, µPD703129 PD703129 V850E/CA2TM V850E/CA2TM JUPITER 32-/16-BIT 32-/16-BIT ROMLESS MICROCONTROLLER DESCRIPTION The V850E/CA2 V850E/CA2 Jupiter ROM-less microcontroller is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs. The V850E/CA2 V850E/CA2 Jupiter offers an excellent combination of general purpose peripheral functions, like serial communication interfaces (UART, clocked SI) and measurement inputs (A/D converter), with dedicated CAN network support. The device offers power-saving modes to manage the power consumption effectively under varying conditions. Thus equipped, the V850E/CA2 V850E/CA2 Jupiter is ideally suited for automotive applications, like dashboard, gateway or body. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required. FEATURES · · · · · · · · 32-bit RISC CPU with Harvard Architecture 4 K iCache (2-way associative) Full-CAN Interface: 2 or 4 channels Serial Interfaces: 5 channels - 3-wire mode: 3 channels - UART mode: 2 channels Timers: 7 channels - 16-bit multi purpose timer/event counter: channels: 2 channels - 16-bit multi purpose timer: 1 channel - 16-bit OS timer: 2 channels - Watch timer: 1 channel - Watchdog timer: 1 channel 10-bit resolution A/D Converter: 12 channels External Bus Interface (16-bit data / 24-bit address) I/O lines: 78 · · · · · · · Power supply voltage range: - +4.5 V VDD5 +5.5 V - +3.0 V VDD3 +3.6 V Frequency range: up to 32 MHz Built-in low power saving mode Built-in clock oscillator circuit with internal PLL Built-in clock oscillator circuit with internal Spread Spectrum PLL for CPU/ BCU clock operation Temperature range: - -40 °C to +85 °C (µPD703128 PD703128(A), µPD703129 PD703129(A) - -40 °C to +110 °C (µPD703129 PD703129(A1) Package: - 144 LQFP, 0.5 mm pin-pitch (20 x 20 mm) ORDERING INFORMATION Device Part Number µPD703129GJ PD703129GJ(A)-xxx-UEN V850E/ V850E/ CA2 µPD703129GJ PD703129GJ(A1)-xxx-UEN µPD703128GJ PD703128GJ(A)-xxx-UEN Package ROM ROM-less LQFP144 LQFP144 ROM-less 20 x 20 mm ROM-less Operating Temperature (TA) RAM FCAN Option 16 K 4 Channels -40°C ~ +85°C 16 K 4 Channels -40°C ~ +110°C 12 K 2 Channels -40°C ~ +85°C The information contained in this document is released in advance of the production cycle for the device. The parameters for the device may change before final production, or NEC Corporation may, at its own discretion, withdraw the device prior to production. NEC Corporation 2003 Document No. U16307EE1V0DS00 U16307EE1V0DS00 Data Published: January 2003 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) INTERNAL BLOCK DIAGRAM INTP00 INTP00, INTP05 INTP05 INTP10 INTP10, INTP15 INTP15 INTP20 INTP20, INTP21 INTP21 TIG00 TIG00 to TIG05 TIG05 TOG01 to TOG04 TIG10 TIG10 to TIC15 TIC15 TOG11 to TOG14 TIC00 TIC00, TIC01 TIC01 TOC00 power supply Interrupt Controller CPU Core PC 16-bit Timer TMG0 16-bit Timer TMG1 16-bit Timer TMC Barrel Shifter 4 KB iCache System Registers General Registers 16 KB or 12 KB Hardware Multiplier Bus Control Unit A L U A0 to A15 A16 to A23 D0 to D15 WAIT CS0, CS3, CS4 RD UWR, LWR RAM Internal Peripheral Bus b 16-bit Timer TMD0 FCAN1 FCTXD1 AVREF AVSS AVDD FCRXD1 10-bit ADC 12 channels ANI0-ANI11 ANI0-ANI11 16-bit Timer TMD1 Ports P10 to P17 P20 to P27 P30 to P35 P40 to P45 P50 to P56 P60 to P67 P70 to P77 P80 to P83 P90 to P97 NMI INTP0 to INTP5 FCRXD2 FCTXD2 FCAN2 FCRXD3 FCAN3 Bootstrap Loader Note FCTXD3 Sub-Oscillator FCRXD4 FCTXD4 Note Oscillator and Clock Generator with Spread Spectrum PLL, PLL UART50 UART50 BRG RXD51 RXD51 TXD51 TXD51 XT2 FCAN4 RXD50 RXD50 TXD50 TXD50 XT1 UART51 UART51 Watch Timer X1 X2 RESET RESOUT BRG SI00 SO00 SCK00 SCK00 CSI00 CSI00 SI01 SO01 SCK01 SCK01 CSI01 CSI01 Watchdog Timer BRG0 BRG1 SI02 SO02 SCK02 SCK02 CSI02 CSI02 Note: FCRXD3, FCTXD3, FCRXD4 and FCTXD4 are available only in the derivatives µPD703129 PD703129(A) and µPD703129 PD703129(A1). 2 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) PIN IDENTIFICATION A0 to A23 Address Bus P80 to P83 Port 8 D0 to D15 Data Bus P90 to P97 Port 9 ANI0 to ANI11 ANI11 Analog Input PAH0 to PAH7 Port AH AVDD Analog Power Supply PCM0 Port CM0 AVREF Analog Reference Voltage PCS0, PCS3, PCS4 Port CS AVSS Analog Ground PCT0, PCT1, PCT4 Port CT FCRXD1 to FCRXD4Note CAN Receive Line Input RESET Reset FCTXD1 to FCTXD4Note CAN Transmit Line Output RESOUT Reset Out CVDD Clock Generator Power Supply RXD50 RXD50 to RXD51 RXD51 Receive Data Input CVSS Clock Generator Ground SCK00 SCK00 to SCK02 SCK02 Serial Clock GND30 GND30 to GND36 GND36 Ground for 3 V Power Supply SI00 to SI02 Serial Input GND50 GND50 to GND52 GND52 Ground for 5 V Power Supply SO00 to SO02 Serial Output INTP0 to INTP5 External Interrupt Request TIG00 TIG00 to TIG05 TIG05, TIG10 TIG10 to TIG15 TIG15, TIC00 TIC00, TIC01 TIC01 Timer Input INTPn0, INTPn5, INTP2n External Interrupt Request TOG01 to TOG04, TOG11 to TOG14, TOC00 Timer Output MODE0 to MODE2 Mode Inputs TXD50 TXD50 to TXD51 TXD51 Transmit Data Output NMI Non-Maskable Interrupt Request VDD30 VDD30 to VDD36 VDD36 3 V Power Supply P10 to P17 Port 1 VDD50 VDD50 to VDD52 VDD52 5 V Power Supply P20 to P27 Port 2 WAIT Wait P30 to P35 Port 3 LWR, UWR Write Enable P40 to P45 Port 4 RD Read P50 to P56 Port 5 CS0, CS3, CS4 Chip Select P60 to P67 Port 6 X1, X2 Crystal (Main-OSC) P70 to P77 Port 7 XT1, XT2 Crystal (Sub-OSC) Note: FCRxD3, FCTxD3, FCRxD4 and FCTxD4 are available only in the derivative µPD703129 PD703129 (A) and µPD703129 PD703129 (A1). Remark: n = 0, 1 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 3 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) PIN CONFIGURATION (Top View) 144-Pin Plastic LQFP (fine pitch) (20 mm × 20 mm) · µPD703128 PD703128(A) · µPD703129 PD703129(A) P17/TXD51 P17/TXD51 P16/RXD51 P16/RXD51 P55/TIC01/INTP21 P55/TIC01/INTP21 P53/INTP5 P53/INTP5 P45/TIG15/INTP15 P45/TIG15/INTP15 P44/TIG14/TOG14 P44/TIG14/TOG14 114 113 112 111 110 109 121 120 119 118 117 116 115 P40/TIG10/INTP10 P40/TIG10/INTP10 P92 P91 P90 VDD52 VDD52 VSS52 VSS52 P27/TXD50 P27/TXD50 P26/RXD50 P26/RXD50 P54/TIC00/INTP20 P54/TIC00/INTP20 P94 P93 124 123 122 VDD36 VDD36 P95 P96 MODE1 VSS36 VSS36 138 137 136 135 134 133 132 131 130 129 128 127 126 125 V850E/CA2 V850E/CA2 "Jupiter" 21 22 23 24 88 87 86 85 25 84 26 27 28 29 30 83 82 81 80 79 78 77 76 75 74 73 31 32 33 34 XT1 P43/TIG13/TOG13 P43/TIG13/TOG13 P42/TIG12/TOG12 P42/TIG12/TOG12 P41/TIG11/TOG11 P41/TIG11/TOG11 P56/TOC00 P56/TOC00 P65/SI02 P65/SI02 P66/SO02 P66/SO02 P67/SCK02 P67/SCK02 VDD51 VDD51 VSS51 VSS51 P11/FCTXD1 P11/FCTXD1 P10/FCRXD1 P10/FCRXD1 P13/FCTXD2 P13/FCTXD2 P12/FCRXD2 P12/FCRXD2 P15/FCTXD3 P15/FCTXD3 Note P14/FCRXD3 P14/FCRXD3 Note P51/FCTXD4 P51/FCTXD4 Note Note P50/FCRXD4 P50/FCRXD4 VDD35 VDD35 VSS35 VSS35 P34/TIG04/TOG04 P34/TIG04/TOG04 P33/TIG03/TOG03 P33/TIG03/TOG03 P23/SI01 P23/SI01 P24/SO01 P24/SO01 P25/SCK01 P25/SCK01 P20/SI00 P20/SI00 P21/SO00 P21/SO00 P22/SCK00 P22/SCK00 VDD50 VDD50 VSS50 VSS50 P32/TIG02/TOG02 P32/TIG02/TOG02 P31/TIG01/TOG01 P31/TIG01/TOG01 P35/TIG05/INTP05 P35/TIG05/INTP05 P30/TIG00/INTP00 P30/TIG00/INTP00 71 72 P52/INTP4 P52/INTP4 P64/INTP3 P64/INTP3 P63/INTP2 P63/INTP2 P60/NMI P60/NMI P61/INTP0 P61/INTP0 P62/INTP1 P62/INTP1 67 68 69 70 58 59 60 61 62 63 64 65 66 CVDD X2 X1 RESET XT2 D6 D13 D5 D2 D9 D1 D10 D3 D11 PAH1/A7 D15 D7 D14 57 35 36 37 38 39 40 41 42 43 44 45 46 47 D8 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PAH5/A21 PAH5/A21 PAH6/A22 PAH6/A22 PAH7/A23 PAH7/A23 VDD34 VDD34 VSS34 VSS34 A0 PCT1/UWR PCS3/CS3 PCS4/CS4 CVSS PCS0/CS0 PCT4/RD D0 VDD32 VDD32 VSS32 VSS32 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD33 VDD33 VSS33 VSS33 A3 A2 A1 108 107 106 105 D12 D4 PAH0/A16 PAH0/A16 A15 A14 A13 A12 A11 A10 A9 PAH4/A20 PAH4/A20 VDD30 VDD30 VSS30 VSS30 PCT0/LWR RESOUT PCM0/WAIT VDD31 VDD31 VSS31 VSS31 PAH3/A19 PAH3/A19 PAH2/A18 PAH2/A18 A8 A7 A6 A5 A4 1 2 3 4 48 49 50 51 52 53 54 55 56 AVREF AVDD AVSS MODE2 143 142 141 140 139 144 P70/ANI0 P70/ANI0 P71/ANI1 P71/ANI1 P72/ANI2 P72/ANI2 P73/ANI3 P73/ANI3 P74/ANI4 P74/ANI4 P75/ANI5 P75/ANI5 P76/ANI6 P76/ANI6 P77/ANI7 P77/ANI7 P80/ANI8 P80/ANI8 P81/ANI9 P81/ANI9 P82/ANI10 P82/ANI10 P83/ANI11 P83/ANI11 MODE0 P97 · µPD703129 PD703129(A1) Note: FCRXD3, FCTXD3, FCRXD4 and FCTXD4 are available only in the derivatives µPD703129 PD703129(A) and µPD703129 PD703129(A1). 4 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table of Contents INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PIN IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONFIGURATION (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 1.3 Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Non-port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 Main Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2 Sub Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 Peripheral PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 Spread Spectrum PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 I/O Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.1 Peripheral Clock Operating Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 CPU Clock Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.3 Watch Timer Clock Operating Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.4 Watchdog Timer Clock Operating Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.2 AC Test Load Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.3 Recommended Main Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.4 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.5 External Memory Access Read Timing in R1/S1 (Direct) Mode . . . . . . . . . . . . . 35 2.5.6 External Memory Access Write Timing in R1/S1 (Direct) Mode . . . . . . . . . . . . . 37 2.5.7 External Memory Access Read Timing in R0/S0 (low EMI) Mode . . . . . . . . . . . 39 2.5.8 External Memory Access Write Timing in R0/S0 (low EMI) Mode . . . . . . . . . . . 41 2.5.9 RESET (power up/down Sequence). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.10 RESET Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.11 Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Peripheral Function Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.1 Timer G/Timer C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.2 CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6.3 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.4 FCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.5 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.6 Serial "External Flash Memory" Programming Operation Characteristics . . . . . 49 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 2.4 2.5 2.6 3. Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4. Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 5 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) List of Figures Figure 1-1: Figure 2-1: Figure 2-2: Figure 2-3: Figure 2-4: Figure 2-5: Figure 2-6: Figure 2-7: Figure 2-8: Figure 2-9: Figure 2-10: Figure 2-11: Figure 2-12: Figure 2-13: Figure 2-14: Figure 2-15: Figure 2-16: Figure 3-1: 6 Input / Output Circuits. 15 AC Test Input Waveform, AC Test Load Condition . 31 AC Test Load Condition . 31 Main Oscillator Recommendations. 32 Sub Oscillator Recommendations . 33 Clock Timing (1/2) . 34 External Memory Access Read Timing in R1/S1 (Direct) Mode. 36 External Memory Access Write Timing in R1/S1 (Direct) Mode . 38 External Memory Access Read Timing in R0/S0 (low EMI) Mode . 40 External Memory Access Write Timing in R0/S0 (low EMI) Mode. 42 RESET Timing. 43 Reset Output Timing. 44 Interrupt Timing . 45 Timer G Characteristics. 46 Timer C Characteristics . 46 CSI Slave Mode Characteristics. 47 Serial "External Flash Memory" Programming Characteristics Timing. 49 Package Drawing . 50 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) List of Tables Table 1-1: Table 1-2: Table 2-1: Table 2-2: Table 2-3: Table 2-4: Table 2-5: Table 2-6: Table 2-7: Table 2-8: Table 2-9: Table 2-10: Table 2-11: Table 2-12: Table 2-13: Table 2-14: Table 2-15: Table 2-16: Table 2-17: Table 2-18: Table 2-19: Table 2-20: Table 2-21: Table 2-22: Table 2-23: Table 2-24: Table 2-25: Table 2-26: Table 2-27: Table 2-28: Table 4-1: Port Function . 9 Non-Port Functions. 12 Absolute Maximum Ratings. 16 Main Oscillator Characteristics . 17 Sub Oscillator Characteristics . 17 Peripheral PLL Characteristics . 17 Spread Spectrum PLL Characteristics . 18 I/O Capacitances . 18 Peripheral Clock Operating Frequency . 19 CPU Clock Operating Frequency . 20 Peripheral Clock Operating Frequency . 21 Peripheral Clock Operating Frequency . 21 DC Characteristics. 22 Main system clock crystal recommendation . 32 Sub-system clock crystal recommendation . 33 Clock Timing. 34 External Memory Access Read Timing in R1/S1 (Direct) Mode. 35 External Memory Access Write Timing in R1/S1 (Direct) Mode . 37 External Memory Access Read Timing in R0/S0 (low EMI) Mode . 39 External Memory Access Write Timing in R0/S0 (low EMI) Mode. 41 Reset Timing . 43 Reset Output Timing. 44 Interrupt Timing . 45 Timer G/Timer C Characteristics . 46 CSI Master Mode Characteristics. 47 CSI Slave Mode Characteristics. 47 UART Characteristics . 48 FCAN Characteristics . 48 A/D Converter Characteristics . 48 Serial "External Flash Memory" Programming Characteristics. 49 Soldering Conditions . 51 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 7 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 8 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 1. Pin Functions 1.1 Port Pins Table 1-1: Port P10 Port Function (1/3) I/O Function I/O Driver Type Port 1: 8-bit input/output port 5-K Alternate FCRXD1 P11 FCTXD1 P12 FCRXD2 P13 FCTXD2 P14 FCRXD3Note P15 FCTXD3Note P16 RXD51 RXD51 P17 TXD51 TXD51 P20 I/O Port 2: 8-bit input/output port 5-K SI00 P21 SO00 P22 SCK00 SCK00 P23 SI01 P24 SO01 P25 SCK01 SCK01 P26 RXD50 RXD50 P27 TXD50 TXD50 P30 I/O Port 3: 6-bit input/output port 5-K TIG00 TIG00, INTP00 INTP00 P31 TIG01 TIG01, TOG01 P32 TIG02 TIG02, TOG02 P33 TIG03 TIG03, TOG03 P34 TIG04 TIG04, TOG04 P35 TIG05 TIG05, INTP05 INTP05 P40 I/O Port 4: 6-bit input/output port 5-K TIG10 TIG10, INTP10 INTP10 P41 TIG11 TIG11, TOG11 P42 TIG12 TIG12, TOG12 P43 TIG13 TIG13, TOG13 P44 TIG14 TIG14, TOG14 P45 TIG15 TIG15, INTP15 INTP15 P50 I/O Port 5: 7-bit input/output port 5-K FCRXD4Note P51 FCTXD4Note P52 INTP4 P53 INTP5 P54 TIC00 TIC00, INTP20 INTP20 P55 TIC01 TIC01, INTP21 INTP21 P56 TOC0 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 9 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 1-1: Port P60 Port Function (2/3) I/O Function I/O Port 6: 8-bit input/output port Driver Type 5-K Alternate NMI P61 INTP0 P62 INTP1 P63 INTP2 P64 INTP4 P65 SI02 P66 SO02 P67 SCK02 SCK02 P70 I Port 78: 12-bit input port 9-C ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 P80 ANI8 P81 ANI9 P82 ANI10 ANI10 P83 ANI11 ANI11 P90 I/O Port 9: 8-bit input/output port 5-K - P91 - P92 - P93 - P94 - P95 - P96 - P97 - PAH0 I/O Port AH: 8-bit input/output port 5 A16 PAH1 A17 PAH2 A18 PAH3 A19 PAH4 A20 PAH5 A21 PAH6 A22 PAH7 A23 PCS0 I/O Port CS: 3-bit input/output port 5 CS0 PCS3 CS3 PCS4 CS4 10 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 1-1: Port PCT0 I/O I/O Port Function (3/3) Function Driver Type Port CT: 2-bit input/ 3-bit output port 5 PCT1 Alternate WR0 WR1 PCT4 O PCM0 I/O RD Port CM: 1-bit input/output port 5 WAIT Note: FCRXD3, FCTXD3, FCRXD4 and FCTXD4 are available only in the derivatives µPD703129 PD703129(A) and µPD703129 PD703129(A1). Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 11 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 1.2 Non-port Pins Table 1-2: Pin Name Non-Port Functions (1/3) Termination if unused Function VDD50 VDD50 -VDD52 -VDD52 Power supply 5.0 V VSS50 VSS50 - VSS52 VSS52 Driver Type I/O Ground for power supply 5.0 V VDD30 VDD30 -VDD36Note 1 VSS30 VSS30 - VSS36 VSS36 Power supply 3.3 V Ground for power supply 3.3 V CVDDNote 2 Power supply 3.3 V clock oscillator and PLL CVSS Ground for clock oscillator and PLL circuit X1 Input X2 Output XT1 Input XT2 Output Clock oscillator connection pins Caution: pins are 3.3 V Sub-Clock oscillator connection pins Caution: pins are 3.3 V Refer to oscillator recommendations 16 MODE0 - MODE2 Input Selects operating mode 2 RESET Input System reset input 2 System reset output (incl. Watch dog timer reset) 3 RESOUT AVDD AVSS Output Power supply for A/D converter VDD5x Ground for A/D converter VSS5x AVREF Input Reference voltage input for A/D converter VDD5x ANI0 - ANI11 ANI11 Input Analog input to A/D converter VSS5x NMI Input Non-maskable interrupt SI00 Input Serial receive data input to CSI00 CSI00 SO00 Output SCK00 SCK00 I/O SI01 Input SO01 Output SCK01 SCK01 I/O SI02 Input SO02 Output SCK02 SCK02 I/O RXD50 RXD50 Input TXD50 TXD50 Output RXD51 RXD51 Input TXD51 TXD51 Output Serial transmit data output from CSI00 CSI00 Serial clock I/O from/to CSI00 CSI00 Serial receive data input to CSI01 CSI01 Serial transmit data output from CSI01 CSI01 Serial clock I/O from/to CSI01 CSI01 Serial receive data input to CSI02 CSI02 Serial transmit data output from CSI02 CSI02 Serial clock I/O from/to CSI02 CSI02 Serial receive data input to UART50 UART50 Serial transmit data output from UART50 UART50 Serial receive data input to UART51 UART51 Serial transmit data output from UART51 UART51 FCRXD1 Input FCTXD1 Output FCRXD2 Input Serial receive data input to FCAN2 FCTXD2 Output Serial transmit data output FCAN2 12 Serial receive data input to FCAN1 Serial transmit data output to FCAN1 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 100 K to VDD5x 5-K µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 1-2: Pin Name I/O Non-Port Functions (2/3) Function FCRXD3Note 3 Input FCTXD3Note 3 Output FCRXD4Note 3 Input FCTXD4Note 3 Output INTP0 - INTP5 Input Input Input Input External maskable interrupt 10 INTP15 INTP15 Input External maskable interrupt 15 INTP20 INTP20 Input External maskable interrupt 20 INTP21 INTP21 Input External maskable interrupt 21 TIG00 TIG00 Input Timer G0 capture input 0 TIG01 TIG01 Input Timer G0 capture input 1 TIG02 TIG02 Input Timer G0 capture input 2 TIG03 TIG03 Input Timer G0 capture input 3 TIG04 TIG04 Input Timer G0 capture input 4 TIG05 TIG05 Input Timer G0 capture input 5 TOG01 Output Timer G0 compare output 1 TOG02 Output Timer G0 compare output 2 TOG03 Output Timer G0 compare output 3 TOG04 Output Timer G0 compare output 4 TIG10 TIG10 Input Timer G1 capture input 0 TIG11 TIG11 Input Timer G1 capture input 1 TIG12 TIG12 Input Timer G1 capture input 2 TIG13 TIG13 Input Timer G1 capture input 3 TIG14 TIG14 Input Timer G1 capture input 4 TIG15 TIG15 Input Timer G1 capture input 5 TOG11 Output Timer G1 compare output 1 TOG12 Output Timer G1 compare output 2 TOG13 Output Timer G1 compare output 3 TOG14 Output Timer G1 compare output 4 TIC00 TIC00 Input Timer C1 capture input 0 TIC01 TIC01 Input Timer C1 capture input 1 TOC0 Output 5-K External maskable interrupt 05 INTP10 INTP10 100 K to VDD5x External maskable interrupt 00 INTP05 INTP05 Driver Type External maskable interrupts 0-5 INTP00 INTP00 Termination if unused Timer C1 compare output Serial receive data input to FCAN3 Serial transmit data output to FCAN3 Serial receive data input to FCAN4 Serial transmit data output to FCAN4 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 13 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 1-2: Pin Name D0 - D15 I/O I/O A0 - A7 Output A8 - A15 Function Data bus of external bus Termination if unused Driver Type 100 K to VDD5x 5 Output A16 - A23 Non-Port Functions (3/3) Address bus of external bus I/O 4 5 WR0 Output Write strobe lower byte (bit 0 - 7) WR1 Output Write strobe upper byte (bit 8 - 15) RD Output Read strobe for external bus WAIT Input CS0, CS3, CS4 Wait control signal for external bus Output Chip select output for external bus Notes: 1. All VDD3x power supply pins must be tied together externally. Resistance between VDD3x pins must not exceed 0.1 DC /2.5 at 20 MHz. 2. CVDD and VDD3x must be tied together externally. 3. FCRXD3, FCTXD3, FCRXD4 and FCTXD4 are available only in the derivatives µPD703129 PD703129(A) and µPD703129 PD703129(A1). 14 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 1.3 I/O Circuits Figure 1-1: Input / Output Circuits Type 2 Type 3 V DD P-ch Data OUT IN N-ch V SS Type 5 Type 4 VDD V DD data Data P-ch P-ch IN/OUT IN/OUT Output disable output disable N-ch N-ch input enable Type 5-K Type 9-C V DD P-ch Data Comparator + - P-ch IN/OUT Output disable N-ch V SS IN N-ch AVSS VREF (threshold voltage) Input enable Input enable Type 16 feedback cut-off P-ch XT1 XT2 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 15 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2. Electrical Specifications 2.1 Absolute Maximum Ratings (TA = 25°C, VSS3x = 0V) Table 2-1: Parameter Absolute Maximum Ratings Symbol Ratings Unit -0.5 ~ +6.0 V -0.5 ~ +6.0 V VDD3x -0.5 ~ +4.6 V CVDD -0.5 ~ +4.6 V VSS5x -0.5 ~ +0.5 V AVSS -0.5 ~ +0.5 V CVSS Supply voltage -0.5 ~ +0.5 V AVDD Input voltage Test Conditions VDD5x 5 V pins AVDD VDD5x + 0.5 V VI1Note 1 VI1 < VDD5x + 0.5 V -0.5 ~ +6.0 V AVREF AVREF AVDD + 0.5 V -0.5 ~ +6.0 V VI2Note 2 VI2 < VDD3x + 0.5 V -0.5 ~ +4.6 V P7, P8 VIA VIA < AVDD + 0.5 V -0.5 ~ +6.0 V 1 pin IOL0 4.0 mA All pins IOL1 50 mA 1 pin IOH0 -4.0 mA All pins IOH1 -50 mA Output voltage 5 V pinsNote 3 VO1 VO1 < VDD5x + 0.5 V -0.5 ~ +6.0 V Output voltage 3.3 V pinsNote 4 VO2 VO2 < VDD3x + 0.5 V -0.5 ~ +4.6 V TOPR µPD703128 PD703128(A), µPD703129 PD703129(A) -40 ~ +85 °C µPD703129 PD703129(A1) -40 ~ +110 °C -55 ~ +150 °C 3.3 V pins Output current low Output current high Operating temperature Storage temperature TSTGB Notes: 1. Referenced 5 V pins are P1, P2, P3, P4, P5, P6, P9, RESET, MODE0, MODE1 2. Referenced 3.3 V pins are PAH, PD, PCS, PCM, PCT, MODE2 3. Referenced 5 V pins are P1, P2, P3, P4, P5, P6, P9 4. Referenced 3.3 V pins are PA, PD, PCS, PCM, PCT, RESOUT 16 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.2 General Characteristics 2.2.1 Main Oscillator Characteristics µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-2: Parameter Main Oscillator Characteristics Symbol Test Conditions Oscillation stabilization time TOST OSC MODE Main oscillator frequency fOSC OSC MODE MIN. TYP. Unit 10 ms 5 4 MAX. MHz 2.2.2 Sub Oscillator Characteristics µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-3: Parameter Sub Oscillator Characteristics Symbol Test Conditions Oscillation stabilization time TSOST OSC MODE Sub oscillator frequency fSOSC MIN. OSC MODE TYP. MAX. Unit tbd. ms 32.768 KHz 2.2.3 Peripheral PLL Characteristics µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-4: Peripheral PLL Characteristics Parameter Symbol Test Conditions PLL lock time TPLL MIN. MAX. Unit OSC MODE: TA = -40 ~ +85°C 1 ms OSC MODE: TA = -40 ~ +110°C 1 ms Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 TYP. 17 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.2.4 Spread Spectrum PLL Characteristics µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-5: Parameter Spread Spectrum PLL Characteristics Frequency multiplication Test Conditions TSSCG MSSCG MAX. Unit TA = -40 ~ +85°C 3 ms TA = -40 ~ +110°C SSCG lock time Symbol MIN. TYP. 3 ms 32.0 - fOSC = 5 MHz 25.5 - Dithering enabled Frequency modulation fOSC = 4 MHz 0.65 % 2.2.5 I/O Capacitances (TA = 25°C, VDD5x = VSS5x = VDD3x = VSS3x = CVDD = CVSS = AVDD = AVSS = 0 V) Table 2-6: Parameter Input capacitance Symbol CI Input/output capacitance CIO Output capacitance CO 18 I/O Capacitances Test Conditions MIN. TYP. fC = 1 MHz Unmeasured pins returned to 0 V Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 MAX. Unit 15 pF 15 pF 15 pF µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.3 Operating Conditions 2.3.1 Peripheral Clock Operating Frequency (VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-7: Operation Mode Main OSC Mode, PLL onNote 1 Peripheral Clock Operating Frequency Operating Temperature (TA) -40°C ~ +85°C µPD703129 PD703129(A1) µPD703128 PD703128(A), µPD703129 PD703129(A) -40°C ~ +85°C Inside Operation Clock Frequency 3.0 V VDD3x 3.6 V 16 to 20 MHz 3.0 V VDD3x 3.6 V 4 to 5 MHz -40°C ~ +110°C µPD703129 PD703129(A1) Main OSC Mode, PLL offNote 2 µPD703128 PD703128(A), µPD703129 PD703129(A) Supply Voltage (VDD3x) -40°C ~ +110°C Notes: 1. The inside peripheral operation clock frequency is the crystal frequency multiplied with the multiplication factor x4. 2. The inside peripheral operation clock frequency is the crystal frequency. Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 19 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.3.2 CPU Clock Operating Frequency (VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-8: Operation Mode CPU Clock Operating Frequency Operating Temperature (TA) Sub-OSC Mode -40°C ~ +110°C µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) -40°C ~ +85°C -40°C ~ +110°C µPD703128 PD703128(A), µPD703129 PD703129(A) -40°C ~ +85°C µPD703129 PD703129(A1) µPD703128 PD703128(A), µPD703129 PD703129(A) -40°C ~ +85°C Inside Operation Clock Frequency -40°C ~ +110°C µPD703129 PD703129(A1) Main OSC Mode, SSCG off, PLL offNote 3 -40°C ~ +85°C µPD703129 PD703129(A1) Main OSC Mode, PLL onNote 2 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) µPD703129 PD703129(A1) Main OSC Mode, SSCG onNote 1 Supply Voltage (VDD3x) -40°C ~ +110°C 3.0 V VDD3x 3.6 V 16 to 32 MHz 16 to 20 MHz 3.0 V VDD3x 3.6 V 16 to 32 MHz 16 to 20 MHz 3.0 V VDD3x 3.6 V 4 to 5 MHz 3.0 V VDD3x 3.6 V 32 KHz Notes: 1. The max. inside operation clock frequency is the crystal frequency multiplied with a multiplication factor configured in the SSCG Frequency Control Register 1 (SCFC1) and divided by a factor configured in the SSCG Frequency Modulation Control Register (SCFMC). 2. The inside operation clock frequency is the crystal frequency multiplied with the multiplication factor x4 or x8 according to the setting of the Processor Clock Control Register (PCC). 3. The inside operation clock frequency is the crystal frequency. 20 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.3.3 Watch Timer Clock Operating Frequency (VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-9: Operation Mode Peripheral Clock Operating Frequency Operating Temperature (TA) -40°C ~ +85°C µPD703128 PD703128(A), µPD703129 PD703129(A) -40°C ~ +85°C Inside Operation Clock Frequency 3.0 V VDD3x 3.6 V fMain-OSC/128, fMain-OSC/512, fMain-OSC/4096 3.0 V VDD3x 3.6 V fSub-OSC/4, fSub-OSC/32 -40°C ~ +110°C µPD703129 PD703129(A1) Sub-OSC Mode µPD703128 PD703128(A), µPD703129 PD703129(A) µPD703129 PD703129(A1) Main OSC Mode Supply Voltage (VDD3x) -40°C ~ +110°C 2.3.4 Watchdog Timer Clock Operating Frequency (VDD5x = AVDD = 4.0 V ~ 5.5 V, CVDD = VDD3x, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-10: Operation Mode Peripheral Clock Operating Frequency Operating Temperature (TA) Sub-OSC Mode µPD703128 PD703128(A), µPD703129 PD703129(A) -40°C ~ +85°C µPD703129 PD703129(A1) Main OSC Mode -40°C ~ +85°C µPD703129 PD703129(A1) Inside Operation Clock Frequency 3.0 V VDD3x 3.6 V fMain-OSC, fMain-OSC/128 3.0 V VDD3x 3.6 V fSub-OSC -40°C ~ +110°C µPD703128 PD703128(A), µPD703129 PD703129(A) Supply Voltage (VDD3x) -40°C ~ +110°C Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 21 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.4 DC Characteristics (TA= -40 ~ +85°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-11: Parameter DC Characteristics Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage high Port pins group 1Not 1 VIH1 4.0 V VDD5x = AVDD 5.5 V 0.8 VDD5x VDD5x V Input voltage low Port pins group 1Note1 VIL1 4.0 V VDD5x = AVDD 5.5 V 0 0.2 VDD5x V Input voltage high P9 VIH2 0.8 VDD5x VDD5x V Input voltage low P9 VIL2 0 0.4 VDD5x V Input voltage high Port pins group 2Note2 VIH3 0.7 VDD3x VDD3x V Input voltage low Port pins group 2Not 2 VIL3 0 0.3 VDD3x V Input voltage high MODE2 VIH4 0.8 VDD3x VDD3x V Input voltage low MODE2 VIL4 0 0.2 VDD3x V Input voltage high P7, P8 VIHA VDD5x - 0.3 V AVDD VDD5x 0.7 VDD5x VDD5x V Input voltage low P7, P8 VILA VDD5x - 0.3 V AVDD VDD5x 0 0.3 VDD5x V VOH1 IOH5 = -3.0 mA VDD5x - 1.0 V V VOH1A IOH5 = -0.5 mA, VDD5x = AVDD = 4.0 V VDD5x - 1.0 V V VOL1 IOL5 = 3.0 mA 0.4 V VOL1A IOL5 = 0.5 mA, VDD5x = AVDD = 4.0 V 0.4 V Output voltage high Port pins group 4Note4 VOH2 IOH3 = -2.5 mA Output voltage low Port pins group 4Note4 VOL2 IOL3 = 2.5 mA 0.4 V Input leakage current, high Port pins group 1Note1, P9 ILIH1 VI = VDD5 5 µA Input leakage current, low Port pins group 1Note1, P9 ILIL1 VI = 0 V -5 µA Output voltage high Port pins group 3Note3 Output voltage low Port pins group 3Note3 22 VDD3x - 1.0 V Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 V µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 2-11: Parameter DC Characteristics Symbol Test Conditions MIN. TYP. MAX. Input leakage current, high P7, P8 ILIHA AVIN = AVDD 2 Input leakage current, low P7, P8 ILILA AVIN = 0 V -2 VI = VDD3 Unit 5 Input leakage current, high Port pins group 2Note2, MODE2 ILIH2 Input leakage current, low Port pins group 2Note2, MODE2 ILIL2 µA µA µA VI = 0 V -5 µA Notes: 1. Port pins group 1: P1, P2, P3, P4, P5, P6, MODE0, MODE1, RESET 2. Port pins group 2: PAH, PD, PCS, PCM, PCT, MODE2 3. Port pins group 3: P1, P2, P3, P4, P5, P6, P9 4. Port pins group 4: PA, PAH, PD, PCS, PCM, PCT, RESOUT Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 23 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (TA= -40 ~ +85°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = AVSS = CVSS = 0 V, fOSC = 4 MHz) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1SC1 DC Characteristics (1/2) Test Conditions TYP. MAX. Unit Operating (SSCG1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 86 129 mA IDD1SC2 Operating (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 48 72 mA IDD1P1 Operating (PLL1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 78 117 mA IDD1P2 Operating (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 55 83 mA IDD1O Operating (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 18 27 mA IDD2SC1 HALT (SSCG1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 65 98 mA IDD2SC2 HALT (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 40 60 mA IDD2P1 HALT (PLL1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 55 83 mA IDD2P2 HALT (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 38 57 mA IDD2O 24 MIN. HALT (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 10 15 mA Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD3SC1 DC Characteristics (2/2) Test Conditions MIN. TYP. MAX. Unit IDLE (SSCG1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 11 22 mA IDD3SC2 IDLE (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 11 22 mA IDD3P1 IDLE (PLL1): fCPU = 32 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 1.8 3.6 mA IDD3P2 IDLE (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 1.8 3.6 mA IDD3O IDLE (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 1.1 2.3 mA IDD4 WATCHNote 2 700 1300 µA IDD5P STOP 50 300 µA Notes: 1. All supply currents specified above are representing the total current consumption of the power supply pins VDD31 VDD31, VDD34 VDD34, VDD35 VDD35 and VDD36 VDD36. ADC and I/O buffer are not included. 2. The Watch timer and the Watchdog timer are supplied with a clock of 32 KHz. Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 25 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V, fOSC = 4 MHz) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1SC2 DC Characteristics Test Conditions MIN. TYP. MAX. Unit Operating (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 48 72 mA IDD1P2 Operating (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 55 83 mA IDD1O Operating (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 18 27 mA IDD2SC2 HALT (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on 40 60 mA IDD2P2 HALT (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on 38 57 mA IDD2O HALT (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 10 15 mA IDD3SC2 IDLE (SSCG2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: on, PLL: on tbd. tbd. mA IDD3P2 IDLE (PLL2): fCPU = 16 MHz, fPeripherals = 16 MHz SSCG: off, PLL: on tbd. tbd. mA IDD3O IDLE (OSC): fCPU = 4 MHz, fPeripherals = 4 MHz SSCG: off, PLL: off 1.2 2.4 mA IDD4 WATCHNote 2 800 1600 µA IDD5P STOP 50 500 µA Notes: 1. All supply currents specified above are representing the total current consumption of the power supply pins VDD31 VDD31, VDD34 VDD34, VDD35 VDD35 and VDD36 VDD36. ADC and I/O buffer are not included. 2. The Watch timer and the Watchdog timer are supplied with a clock of 32 KHz. 26 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (TA= -40 ~ +85°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = AVSS = CVSS = 0 V, fOSC = 5 MHz) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1SC1 DC Characteristics (1/2) Test Conditions MIN. TYP. MAX. Unit Operating (SSCG1): fCPU = 32 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 108 162 mA IDD1SC2 Operating (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 54 81 mA IDD1P2 Operating (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 68 102 mA IDD1O Operating (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 21 32 mA IDD2SC1 HALT (SSCG1): fCPU = 32 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 80 120 mA IDD2SC2 HALT (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 44 66 mA IDD2P2 HALT (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 42 63 mA IDD2O HALT (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 13 20 mA Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 27 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD3SC1 DC Characteristics (2/2) Test Conditions MIN. TYP. MAX. Unit IDLE (SSCG1): fCPU = 32 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 13 26 mA IDD3SC2 IDLE (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 13 26 mA IDD3P2 IDLE (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 2.5 5 mA IDD3O IDLE (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 1.4 2.8 mA IDD4 WATCHNote 2 900 1800 µA IDD5P STOP 50 300 µA Notes: 1. All supply currents specified above are representing the total current consumption of the power supply pins VDD31 VDD31, VDD34 VDD34, VDD35 VDD35 and VDD36 VDD36. ADC and I/O buffer are not included. 2. The Watch timer and the Watchdog timer are supplied with a clock of 32 KHz. 28 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V, fOSC = 5 MHz) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1SC2 DC Characteristics Test Conditions MIN. TYP. MAX. Unit Operating (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 54 81 mA IDD1P2 Operating (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 68 102 mA IDD1O Operating (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 21 32 mA IDD2SC2 HALT (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 40 60 mA IDD2P2 HALT (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 45 68 mA IDD2O HALT (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 13 26 mA IDD3SC2 IDLE (SSCG2): fCPU = 16 MHz, fPeripherals = 20 MHz SSCG: on, PLL: on 13 26 mA IDD3P2 IDLE (PLL2): fCPU = 20 MHz, fPeripherals = 20 MHz SSCG: off, PLL: on 2.5 5 mA IDD3O IDLE (OSC): fCPU = 5 MHz, fPeripherals = 5 MHz SSCG: off, PLL: off 1.4 3.0 mA IDD4 WATCHNote 2 900 2000 µA IDD5P STOP 50 500 µA Notes: 1. All supply currents specified above are representing the total current consumption of the power supply pins VDD31 VDD31, VDD34 VDD34, VDD35 VDD35 and VDD36 VDD36. ADC and I/O buffer are not included. 2. The Watch timer and the Watchdog timer are supplied with a clock of 32 KHz. Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 29 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (TA= -40 ~ +85°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V, fOSC = 4 MHz ~ 5 MHz, Main-Osc: Off) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1S IDD4S DC Characteristics Test Conditions MIN. TYP. MAX. Unit OperatingNote 2 (Sub-Osc.): fCPU = 32 KHz, fPeripherals = 0 Hz SSCG: off, PLL: off 50 350 µA Sub-WATCHNote 3 (Sub-Osc.): SSCG: off, PLL: off 50 325 µA (TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = AVSS = 0 V, fOSC = 4 MHz ~ 5 MHz, Main-Osc: Off) Table 2-11: Parameter Symbol Supply CurrentNote 1 IDD1S IDD4S DC Characteristics Test Conditions MIN. TYP. MAX. Unit OperatingNote 2 (Sub-Osc.): fCPU = 32 KHz, fPeripherals = 0 Hz SSCG: off, PLL: off 60 550 µA Sub-WATCHNote 3 (Sub-Osc.): SSCG: off, PLL: off 60 550 µA Notes: 1. All supply currents specified above are representing the total current consumption of the power supply pins VDD31 VDD31, VDD34 VDD34, VDD35 VDD35 and VDD36 VDD36. ADC and I/O buffer are not included. 2. During the Sub-Oscillation mode the following operation limitations become valid : · No iCache operation during the Sub-Osc. operating mode. Be sure to disable iCache operation before entering the Sub-Osc. operating mode · No instruction fetcj from iRAM during operation in Sub-Osc. operating mode 3. The Watch timer and the Watchdog timer are supplied with a clock of 32 KHz. 30 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5 AC Characteristics 2.5.1 General µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = AVSS = CVSS = 0 V, Output pin load capacitance: CL= 50 pF) Figure 2-1: AC Test Input Waveform, AC Test Load Condition Test Points VDD5x 0.8 VDD5x 0.2 VDD5x 0V Test Points VDD3x 0.8 VDD3x 0.2 VDD3x 0V 2.5.2 AC Test Load Condition Figure 2-2: AC Test Load Condition DUT Load on test CL = 50 pF Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 31 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.3 Recommended Main Oscillator Circuit (1) Main system clock oscillator (a) Ceramic resonator or crystal resonator connection (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), µPD703129 PD703129 (A1) Figure 2-3: Main Oscillator Recommendations X1 X2 QU C1' Remark: R1' C2' Values of capacitors C1', C2' and R1' depend on used resonator and must be specified in cooperation with the manufacturer. Cautions: 1. External clock input is prohibited. 2. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VSS. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. Table 2-12: Main system clock crystal recommendation QU [MHz] R1' [] CX-49F CX-49F 4.000 1200 12 12 AT-51 AT-51 4.000 0 12 12 ABRACON HC49U HC49U P/N AB 4.000 0 15-22 15-22 ABRACON HC49US HC49US P/N ABL 4.000 0 15-22 15-22 Manufacturer KINSEKI NDK 32 Type/Series Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 C1' [pF] C2' [pF] µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) (2) Recommended Sub-system clock oscillator circuit (a) Ceramic resonator or crystal resonator connection (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), µPD703129 PD703129 (A1) Figure 2-4: Sub Oscillator Recommendations XT1 XT2 QU C1' Remark: C2' Values of capacitors C1', C2' depend on used resonator and must be specified in cooperation with the manufacturer. Cautions: 1. External clock input is prohibited. 2. When using the sub system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VSS. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. Table 2-13: Manufacturer Sub-system clock crystal recommendation QU [KHz] C1' [pF] C2' [pF] 32.768 Type/Series tbd. tbd. Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 33 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.4 Clock timing µPD703128 PD703128 (A), µPD703129 PD703129 (A), (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703129 PD703129 (A1), VDD5x = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, VSS5x = VSS3x = CVSS = 0 V) Table 2-14: Parameter Clock Timing Symbol Test Conditions MIN. X1 input cycle tCYX OSC Mode 200 X1 input high-level width tWXH OSC Mode 95 ns X1 input low-level width tWXL OSC Mode 95 ns XT1 input cycle tCYXT OSC Mode 30.5 XT1 input high-level width tWXTH OSC Mode 15 µs XT1 input low-level width tWXTL OSC Mode 15 µs Figure 2-5: TYP. MAX. Unit 250 ns 30.6 Clock Timing (1/2) t CYX t WXH t WXL X1 Caution: The voltage power on the main oscillator input pin X1 must not exceed 3.6 V Figure 2-5: Clock Timing (2/2) t CYXT t WXTH t WXTL XT1 Caution: 34 The voltage power on the sub-oscillator input pin XT1 must not exceed 3.6 V. Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µs µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.5 External Memory Access Read Timing in R1/S1 (Direct) Mode Table 2-15: External Memory Access Read Timing in R1/S1 (Direct) Mode Parameter Symbol MAX. Unit TSAIDD (2 + wAS + wD + w)T - 23 ns TSRDIDD (1.5 + wD + w)T - 20 ns RD Low level width TWRDLD (1.5 + wD + w)T - 10 ns RD High level width TWRDHD (0.5 + wAS + i)T - 10 ns Address, CSn RD delay time TDARDD (0.5 + wAS)T - 15 ns RD address delay time TDRDAD iT - 8 ns Data input hold time (vs. RD) THRDIDD -8 ns RD data output delay time TDRDODD (0.5 + i)T - 6 ns WAIT set up time (vs. address) < 31 > TSAWD WAIT high level width TWWHD Data input set up time (vs. address) Data input set up time (vs. RD) Remarks: 1. T: MIN. (1 + wAS) T- 30 T + 10 ns ns 1/fCPU 2. i: Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to WAIT Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 35 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Figure 2-6: External Memory Access Read Timing in R1/S1 (Direct) Mode A0-A25 A0-A25 (output) CSn WR0, WR1 (output) RD (output) D0-D15 D0-D15 (in/out) WAIT (input) 36 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.6 External Memory Access Write Timing in R1/S1 (Direct) Mode Table 2-16: External Memory Access Write Timing in R1/S1 (Direct) Mode Parameter Symbol MIN. MAX. Unit Address, CSn WR0, WR1 delay time TDAWRD (0.5 + wAS)T - 12 ns Address set up (vs. WR0, WR1) TSAWRD (1.5 + wAS + wD + w)T - 15 ns WR0, WR1 address delay time TDWRAD (0.5 + i)T - 10 ns WR0, WR1 High level width TWWRHD (1 + i + wAS)T - 5 ns WR0, WR1 Low level width TWWRLD (1 + w + wD)T - 10 ns Data output set up time (vs. WR0, WR1) TSODWRD (0.5 + wAS + wD + w)T - 18 ns Data output hold time (vs. WR0, WR1) THWRODD (0.5 + i)T - 5 ns WAIT set up time (vs. address) TSAWD WAIT high level width TWWHD Remarks: 1. T: (1 + wAS)T - 30 T + 10 ns ns 1/fCPU 2. i: Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to WAIT Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 37 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Figure 2-7: External Memory Access Write Timing in R1/S1 (Direct) Mode A0-A25 A0-A25 (output) CSn RD (output) WR0, WR1 (output) D0-D15 D0-D15 (in/output) write write D0-D15 D0-D15 (in/output) read write WAIT (input) 38 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.7 External Memory Access Read Timing in R0/S0 (low EMI) Mode Table 2-17: External Memory Access Read Timing in R0/S0 (low EMI) Mode Parameter Symbol MAX. Unit TSAID (2 + wAS + wD + w)T - 34 ns TSRDID (1.5 + wD + w)T - 22 ns RD Low level width TWRDL (1.5 + wD + w)T - 10 ns RD High level width TWRDH (0.5 + wAS + i)T - 10 ns Address, CSn RD delay time TDARD (0.5 + wAS)T - 20 ns RD address delay time TDRDA iT - 5 ns Data input hold time (vs. RD) THRDID 0 ns RD data output delay time TDRDOD (0.5 + i)T - 6 ns WAIT set up time (vs. address) < 31 > TSAW WAIT high level width TWWH Data input set up time (vs. address) Data input set up time (vs. RD) Remarks: 1. T: MIN. (1 + wAS) T- 37 T + 10 ns ns 1/fCPU 2. i: Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to WAIT Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 39 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Figure 2-8: External Memory Access Read Timing in R0/S0 (low EMI) Mode A0-A25 A0-A25 (output) CSn WR0, WR1 (output) RD (output) D0-D15 D0-D15 (in/out) WAIT (input) 40 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.8 External Memory Access Write Timing in R0/S0 (low EMI) Mode Table 2-18: External Memory Access Write Timing in R0/S0 (low EMI) Mode Parameter Symbol MIN. MAX. Unit Address, CSn WR0, WR1 delay time TDAWR (0.5 + wAS)T - 18 ns Address set up (vs. WR0, WR1) TSAWR (1.5 + wAS + wD + w)T - 19 ns WR0, WR1 address delay time TDWRA (0.5 + i)T - 5 ns WR0, WR1 High level width TWWRH (1 + i + wAS)T - 5 ns WR0, WR1 Low level width TWWRL (1 + w + wD)T - 10 ns Data output set up time (vs. WR0, WR1) TSODWR (0.5 + wAS + wD + w)T - 18 ns Data output hold time (vs. WR0, WR1) THWROD (0.5 + i)T - 5 ns WAIT set up time (vs. address) TSAW WAIT high level width TWWH Remarks: 1. T: (1 + wAS)T - 37 T + 10 ns ns 1/fCPU 2. i: Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to WAIT Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 41 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Figure 2-9: External Memory Access Write Timing in R0/S0 (low EMI) Mode A0-A25 A0-A25 (output) CSn RD (output) WR0, WR1 (output) D0-D15 D0-D15 (in/output) write write D0-D15 D0-D15 (in/output) read write WAIT (input) 42 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.9 RESET (power up/down Sequence) Table 2-19: Parameter Symbol RESET high-level width tWRSL0 tWRSL1 Test Conditions MIN. tWRSH RESET low-level width Reset Timing VDD5x VDD3x power up delay Unit 500 ns STOP or Sub-WATCH Mode release TOSTNote 1 ms except STOP or SubWATCH Mode release 500 ns tDVR VDD5x VDD3x power down delay MAX. tDVF 0 0 RESET hold time tDVRR tWRSLnNote 2 ms RESET setup time tDVRF 0 ns Notes: 1. TOST: Oscillation stabilization time of main oscillator 2. n: Remark: 0, 1. Depending on operation condition It must be guaranteed that a valid RESET signal (low active) is applied to the Reset pin at any time if the voltage power of VDD3x becomes below 3.0 V Figure 2-10: RESET Timing tWRSH tWRSL RESET VDD3 VDD3 VDD5 VDD5 RESET t DVR t DVRR t DVRF Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 tDVF 43 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.10 RESET Output Table 2-20: Parameter Symbol Reset Output Timing Test Conditions MIN. MAX. Unit RESOUT low-level width tWROL 4T Note ms RESOUT to first fetch (CS0 ) tDROHF 5 TNote ms Note: T: 1/fOSC, fOSC = Main oscillator frequency Figure 2-11: Reset Output Timing tWROL RESOUT t DROHF CS0 44 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.5.11 Interrupt Timing Table 2-21: Parameter Symbol Interrupt Timing Test Conditions MIN. MAX. Unit NMI high-level width tWNIH 500 ns NMI low-level width tWNIL 500 ns INTP00 INTP00, INTP05 INTP05, INTP10 INTP10, INTP15 INTP15, INTP20 INTP20, INTP21 INTP21, INTPiNote1 high-level width tWITH 500 ns INTP00 INTP00, INTP05 INTP05, INTP10 INTP10, INTP15 INTP15, INTP20 INTP20, INTP21 INTP21, INTPiNote 1 low-level width tWITL 500 ns TIGmn, TIC0mNote 2 high-level width tWTIH 500 ns TIGmn, TIC0mNote 2 low-level width tWTIL 500 ns Notes: 1. i = 0 to 5 2. m = 0 to 1, n = 0 to 5 Figure 2-12: Interrupt Timing t WNIH t WNIL t WITH t WITL t WTIH t WTIL NMI INTPml, INTP2m, INTPn TIGmn, TIG0i Remarks: 1. n = 0 to 5 2. m = 0 to 1 3. i = 1 to 2 4. l = 0, 5 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 45 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.6 Peripheral Function Characteristics 2.6.1 Timer G/Timer C Table 2-22: Parameter Timer G/Timer C Characteristics Symbol Test Conditions MIN. MAX. Unit TIGmn high-level widthNote1 tWTIGH 100 + TTNote2 ns TIGmn low-level widthNote1 tWTIGL 100 + TTNote2 ns TIC0m high-level widthNote3 tWTICH 100 + TTNote2 ns TIC0m low-level widthNote3 tWTICL 100 + TTNote2 ns Notes: 1. m = 0 to 1, n = 0 to 5 2. TT: Depends on selected clock source for the peripheral clock supply and the setup of the respective timer macro clock and timer channel setup 3. m = 0 to 1 Figure 2-13: t WTIGH Timer G Characteristics t WTIGL TIGmn Figure 2-14: t WTICH Timer C Characteristics t WTICL TICm 46 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.6.2 CSI Table 2-23: Parameter CSI Master Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSKM Output 200 ns SCK high level width tWSKHM Output 0.5 tCYSK - 15 ns SCK low level width tWSKLM Output 0.5 tCYSK - 15 ns SI set up time (to SCK ) tSSISKM 30 ns SI hold time (from SCK ) tHSKSIM 30 ns SO output delay time (from SCK ) tDSKSOM SO output hold time (from SCK ) tHSKSOM Table 2-24: Parameter MAX. 30 0.5 tCYSK - 5 Unit ns ns CSI Slave Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSKS Input 200 ns SCK high level width tWSKHS Input 90 ns SCK low level width tWSKLS Input 90 ns SI set up time (to SCK ) tSSISKS 15 ns SI hold time (from SCK ) tHSKSIS 15 ns SO output delay time (from SCK ) tDSKSOS SO output hold time (from SCK ) tHSKSOS Figure 2-15: MAX. 30 tWSKH Unit ns ns CSI Slave Mode Characteristics tCYSK tWSKL tWSKH SCK tSSISK SI tHSKSI Hi-Z Input Data tDSKSO tHSKSO SO Output Data Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 47 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.6.3 UART Table 2-25: Parameter UART Characteristics Symbol Transfer rate Test Conditions TUART fPeripheral 5 MHz MIN. MAX. Unit 312500 bps MAX. Unit 1 Mbps 2.6.4 FCAN Table 2-26: Parameter FCAN Characteristics Symbol TFCAN Transfer rate Test Conditions MIN. f Peripheral 16 MHz 2.6.5 A/D Converter (TA= -40 ~ +85°C: TA= -40 ~ +110°C: µPD703128 PD703128 (A), µPD703129 PD703129 (A), µPD703129 PD703129 (A1), VDD5x = AVDD = 4.5 V ~ 5.5 V, VDD3x = CVDD = 3.0 V ~ 3.6 V, AVREF AVDD VSS5x = VSS3x = CVSS = AVSS = 0 V) Table 2-27: Parameter Resolution Symbol A/D Converter Characteristics Test Conditions MIN. - Overall ErrorNote1 Conversion timeNote2 Note3 - TYP. MAX. 10 Unit Bit AVREF = AVDD ±3 LSB AVREF = 3 V ±5 LSB 12 µs TCONV 5 Sampling time TSAM TCONV/6 Analog input voltage VIAN Analog supply current IAVDD Reference voltage AVREF Reference voltage input currentNote4 IAVREF AVREF = AVDD Reference voltage input leakageNote5 ILAVREF AVREF = AVDD AVSS µs AVREF V 6.0 mA. AVDD V 2 mA 5 µA 3.0 AVSS 1 Notes: 1. The quantization error is not included 2. The conversion time TCONV depends on the setting of the ADM register 3. The sampling time TSAM depends on the setting of the ADM register 4. The A/D converter reference voltage can be switched off internally by software 5. The leakage current specification becomes valid if the A/D converter's reference voltage is switched off 48 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 2.6.6 Serial "External Flash Memory" Programming Operation Characteristics Table 2-28: Serial "External Flash Memory" Programming Characteristics Test Conditions Parameter Symbol VDD5x setup time to MODE1 TDRPSR 100 ns VDD5x setup time to RESET TDRRR TOSTNote 1 ms MODE1 setup time to RESET TPSRRF TOSTNote 1 ms Count start setup time from RESET TRFCF 5TNote 2 + 500 µs Times of MODE1 counting TCOUNT MODE1 count Hi/Low level width TCH, TCL MODE1 pulse count for UART0 NPUART0 0 - NPCSI0 8 - MODE1 pulse count for CSI0 MIN. TYP. MAX. 10 1 Unit ms µs Notes: 1. TOST: Oscillation stabilization time of main oscillator For power up sequence of VDD5x, VDD3x please refer to Section 2.5.9. 2. T: Remark: 1/fOSC, fOSC = Main oscillator frequency The MODE1 input pin is a Schmitt-Trigger input buffer Figure 2-16: Serial "External Flash Memory" Programming Characteristics Timing VDD5x, VDDxx VDD3x 0V TCOUNT TDRPSR MODE1 TRFCF TCH VDD5x 0V TCL TPSRRF RESET VDD5x TDRRR 0V Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 49 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 3. Package Drawing Figure 3-1: Package Drawing 144-PIN 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 6 3 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C MILLIMETERS 22.0±0.2 20.0±0.2 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 -0.07 N P 0.08 1.4 Q 0.10±0.05 R 3° +4° -3° S 1.5±0.1 S144GJ-50-UEN S144GJ-50-UEN 50 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) 4. Recommended Soldering Conditions Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device: Mounting Technology Manual (C10535E C10535E). For soldering methods and conditions other than those recommended please consult NEC. Table 4-1: Soldering Method Soldering Conditions Soldering Condition Symbol of Recommended Soldering Condition Infrared reflow Package peak temperature: 245 °C, Time: 30 seconds max. (210 °C min.), Number of times: 2 max., Number of days: 7 Note IR45-207-2 IR45-207-2 VPS Package peak temperature: 215 °C, Time: 30 seconds max. (210°C min.), Number of times: 2 max., Number of days: 7Note VP15-207-2 VP15-207-2 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device) - Note: After that, prebaking is necessary at tbd °C for tbd hours. The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been opened. Caution: Do not use two or more soldering methods in combination (except partial heating method). Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 51 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 52 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) · The information in this document is current as of 10.01, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. 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M8E 02.10 Preliminary Data Sheet U16307EE1V0DS00 U16307EE1V0DS00 53 µPD703128 PD703128(A), µPD703129 PD703129(A), µPD703129 PD703129(A1) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: · Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. 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