PD67A U14935E PD67B U16792E U17848EJ5V0DS00 U17848EJ5V0DS PD68A PD68B ASR10 - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µPD6P8, 6P8A, 6P8B 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION DESCRIPTION The µPD6P8, 6P8A, 6P8B are microcontrollers for infrared remote control transmitters and are provided with a one-time PROM as the program memory. Because users can write programs for the µPD6P8, 6P8A, 6P8B, they are ideal for program evaluation and small-scale production of application systems that use the µPD67A PD67A, 67B, 68A, 68B. When reading this document, also refer to the following documents. µPD67, 67A, 68, 68A, 69 Data Sheet: U14935E U14935E µPD67B PD67B, 68B Data Sheet: U16792E U16792E FEATURES · Program memory (one-time PROM): 2026 × 10 bits · Data memory (RAM): · On-chip carrier generator for infrared remote control: 32 × 4 bits The high-level and low-level width can be set separately from 250 ns to 64 µs (@ fX = 4 MHz operation) via modulo registers · 9-bit programmable timer: 1 channel · Instruction execution time: · Stack level: 16 µs (@ fX = 4 MHz) 1 level (stack RAM is for data memory RF as well) · I/O pins (KI/O): 8 units · Input pins (KI): 4 units · Sense input pins (S): 3 units (µPD6P8, 6P8A), 4 units (µPD6P8B) · Remote control transmission display output pin (LED): 1 unit (shared with S1 pin) · Power supply voltage: VDD = 1.9 to 3.6 V · Operating ambient temperature: TA = ­40 to +85°C · Oscillation frequency: fX = 3.5 to 4.5 MHz · On-chip POC circuit and RAM retention detector · On-chip oscillator (µPD6P8B) APPLICATIONS Infrared remote control transmitters (for AV and household electric appliances) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U17848EJ5V0DS00 U17848EJ5V0DS00 (5th edition) Date Published January 2009 N Printed in Japan The mark shows major revised points. © 2006 µPD6P8, 6P8A, 6P8B ORDERING INFORMATION Part Number Package µPD6P8MC-5A4-A 20-pin plastic SSOP (7.62 mm (300) µPD6P8AMC-5A4-A 20-pin plastic SSOP (7.62 mm (300) µPD6P8BMC-5A4-A 20-pin plastic SSOP (7.62 mm (300) Remark Products that have the part numbers suffixed by "-A" are lead-free products. µPD6P8 PIN CONFIGURATION (TOP VIEW) 20-pin plastic SSOP (7.62 mm (300) (1) Normal operation mode KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 XOUT 7 14 KI3 XIN 8 13 KI2 GND 9 12 KI1 10 11 KI0 S2 (2) PROM programming mode D6 1 20 D5 D7 2 19 D4 CLK 3 18 D3 4 17 D2 5 16 D1 VDD 6 15 D0 XOUT 7 14 MD3 XIN 8 13 MD2 GND 9 12 MD1 10 11 MD0 (L) VPP Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. L: Connect each of these pins to GND via a pull-down resistor. 2 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B µPD6P8A PIN CONFIGURATION (TOP VIEW) 20-pin plastic SSOP (7.62 mm (300) (1) Normal operation mode KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 XOUT 7 14 KI3 XIN 8 13 KI2 GND 9 12 KI1 10 11 KI0 (F) 1 20 (F) SO 2 19 (F) SCLK 3 18 (F) SI 4 17 (F) (F) 5 16 (F) VDD 6 15 (F) XOUT 7 14 (F) XIN 8 13 (F) GND 9 12 (F) 10 11 (F) S2 (2) PROM programming mode VPP Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. F: These pins are pulled down internally, so leave them open. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 3 µPD6P8, 6P8A, 6P8B µPD6P8B PIN CONFIGURATION (TOP VIEW) 20-pin plastic SSOP (7.62 mm (300) (1) Normal operation mode KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 IC 7 14 KI3 S3 8 13 KI2 GND 9 12 KI1 10 11 KI0 (F) 1 20 (F) SO 2 19 (F) SCLK 3 18 (F) SI 4 17 (F) (F) 5 16 (F) VDD 6 15 (F) (F) 7 14 (F) (F) 8 13 (F) GND 9 12 (F) 10 11 (F) S2 (2) PROM programming mode VPP Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. F: These pins are pulled down internally, so leave them open. 4 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B BLOCK DIAGRAM 4 CPU core 9-bit timer S1/LED 4 KI0 to KI3 8 Onetime PROM Port KI Port KI/O 8 KI/O0 to KI/O7 4 Carrier generator REM Port S 4 S0, S1/LED, S2, S3Note 1 System control Internal oscillatorNote 1 RAM XINNote 2 XOUTNote 2 VDD GND Notes 1. µPD6P8B only 2. µPD6P8 and 6P8A only LIST OF FUNCTIONS µPD6P8 Item µPD6P8A ROM capacity 2026 × 10 bits One-time PROM RAM capacity 32 × 4 bits Stack 1 level (shared with RF of RAM) I/O pins Key input (KI) 4 pins Key I/O (KI/O) 8 pins Key expansion input (S) 3 pins Remote control transmission display output (LED) µPD6P8B 1 pin (shared with S1 pin) 4 pins Number of keys 32 keys 56 keys (when expanded by key expansion input) 32 keys 64 keys (when expanded by key expansion input) Clock frequency Ceramic oscillation fX = 3.5 to 4.5 MHz Internal oscillation fX = 4 MHz (TYP.) Instruction execution time 16 µs (@ fX = 4 MHz) Carrier frequency The high-level and low-level width can be set separately from 250 ns to 64 µs (@ fX = 4 MHz operation) via modulo registers Timer 9-bit programmable timer: 1 channel, timer clock: fX/64 POC circuit On chip RAM retention detector On chip Internal oscillator Not available Programming method Parallel Supply voltage VDD = 1.9 to 3.6 V Operating ambient T A = ­40 to +85°C On chip Serial temperature Package 20-pin plastic SSOP (7.62 mm (300) Data Sheet U17848EJ5V0DS U17848EJ5V0DS 5 µPD6P8, 6P8A, 6P8B CONTENTS 1. PIN FUNCTIONS . 8 1.1 Normal Operation Mode . 8 1.2 PROM Programming Mode . 10 1.3 Pin I/O Circuits . 11 1.4 Recommended Connection of Unused Pins . 12 1.5 Notes on Using KI Pin After Reset . 12 2. DIFFERENCES BETWEEN µPD67A PD67A, 67B, 68A, 68B, AND µPD6P8, 6P8A, 6P8B . 13 3. INTERNAL CPU FUNCTIONS . 14 3.1 Program Counter (PC): 11 Bits . 14 3.2 Stack Pointer (SP): 1 Bit . 14 3.3 Address Stack Register (ASR (RF): 11 Bits . 14 3.4 Program Memory (One-Time PROM): 2,026 Steps × 10 Bits . 15 3.5 Data Memory (RAM): 32 × 4 Bits . 16 3.6 Data Pointer (DP): 12 Bits . 17 3.7 Accumulator (A): 4 Bits . 17 3.8 Arithmetic and Logic Unit (ALU): 4 Bits . 17 3.9 Flags . 18 3.9.1 Status flag (F) . 18 3.9.2 Carry flag (CY) . 18 4. PORT REGISTERS (PX) . 19 4.1 KI/O Port (P0) . 21 4.2 KI Port/Special Ports (P1) . 21 4.2.1 KI port (P11: bits 4 to 7 of P1) . 21 4.2.2 S0 port (bit 2 of P1) . 21 4.2.3 S2 port (bit 1 of P1) . 22 4.2.5 4.3 S1/LED port (bit 3 of P1) . 22 4.2.4 S3 port (bit 0 of P1) (µPD6P8B only) . 22 Control Register 0 (P3) . 24 4.3.1 4.4 RAM retention flag (bit 3 of P3) . 25 Control Register 1 (P4) . 27 5. TIMER . 28 5.1 Timer Configuration . 28 5.2 Timer Operation . 29 5.3 Carrier Output . 31 5.3.1 5.4 Carrier output generator . 31 5.3.2 Carrier output control . 32 Software Control of Timer Output . 34 6. STANDBY FUNCTION . 35 6.1 Standby Mode Setting and Release . 36 6.3 6 Outline of Standby Function . 35 6.2 Standby Mode Release Timing . 38 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 7. RESET . 39 8. POC CIRCUIT . 40 8.1 8.2 Functions of POC Circuit . 41 Oscillation Check at Low Supply Voltage . 41 9. SYSTEM CLOCK OSCILLATOR (µPD6P8, 6P8A) . 42 10. INSTRUCTION SET . 43 10.1 Machine Language Output by Assembler . 10.2 Circuit Symbol Description . 10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table . 10.4 Accumulator Manipulation Instructions . 10.5 I/O Instructions . 10.6 Data Transfer Instructions . 10.7 Branch Instructions . 10.8 Subroutine Instructions . 10.9 Timer Operation Instructions . 10.10 Others . 43 44 45 49 52 53 55 56 57 60 11. ASSEMBLER RESERVED WORDS . 62 11.1 Mask Option Directives . 62 11.1.1 OPTION and ENDOP quasi-directives . 62 11.1.2 Mask option definition quasi-directives . 62 12. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) (µPD6P8) . 63 12.1 Operating Mode When Writing/Verifying Program Memory . 63 12.2 Program Memory Writing Procedure . 64 12.3 Program Memory Reading Procedure . 65 13. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) (µPD6P8A, 6P8B) . 66 13.1 13.2 13.3 13.4 Initialization . Serial Communication Format . Writing of Program Memory . Reading of Program Memory . 66 67 68 68 14. ELECTRICAL SPECIFICATIONS (µPD6P8) . 69 15. ELECTRICAL SPECIFICATIONS (µPD6P8A) . 76 16. ELECTRICAL SPECIFICATIONS (µPD6P8B) . 82 17. CHARACTERISTIC CURVES (REFERENCE VALUES) (µPD6P8) . 87 18. APPLICATION CIRCUIT EXAMPLE . 88 19. PACKAGE DRAWING . 92 20. RECOMMENDED SOLDERING CONDITIONS . 93 APPENDIX A. DEVELOPMENT TOOLS . 94 APPENDIX B. EXAMPLE OF REMOTE CONTROL TRANSMISSION FORMAT (In the case of NEC transmission format in command one-shot transmission mode) . 95 Data Sheet U17848EJ5V0DS U17848EJ5V0DS 7 µPD6P8, 6P8A, 6P8B 1. PIN FUNCTIONS 1.1 Normal Operation Mode (1) µ PD6P8, 6P8A Pin No. Symbol Function 1 2 15 to 20 KI/O0 to KI/O7 8-bit I/O port. I/O mode can be switched in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as a key scan outputs from the key matrix. Output Format 3 S0 Input port. This pin can also be used as a key return input from the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is released by software, this pin is placed in the OFF mode and enters a high-impedance state. 4 S1/LED I/O port. In input mode (S1), this pin can also be used as a key return input from the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output in synchronization with the REM signal. CMOS push-pull High-level output (LED) 5 REM Infrared remote control transmission output. The output is active high. The carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 µs (@ fX = 4 MHz) using software. CMOS push-pull Low-level output 6 VDD Power supply - - 7 8 XOUT X IN These pins are connected to system clock ceramic resonators. - Low level (oscillation stopped) 9 GND GND pin - - 10 S2 Input port. The use of the STOP mode release of the S2 port can be specified by software. When using this pin as a key input from the key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, this pin can be used as an input port that does not release the STOP mode even if the S2 port satisfies the release condition (at this time, a pull-down resistor is not connected internally.) - Input (high impedance, STOP mode release cannot be used) 11 to 14 KI0 to KI3Note 2 4-bit input port. These pins can be used as key return inputs to the key matrix. The use of pull-down resistors can be specified by software in 4-bit units. - Input (low-level) CMOS push-pullNote 1 - After Reset High-level output High-impedance (OFF mode) Notes 1. Note that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup. 8 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B (2) µ PD6P8B Pin No. Symbol Function 1 2 15 to 20 KI/O0 to KI/O7 8-bit I/O port. I/O mode can be switched in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as a key scan outputs from the key matrix. 3 S0 Input port. This pin can also be used as a key return input from the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is released by software, this pin is placed in the OFF mode and enters a high-impedance state. 4 S1/LED I/O port. In input mode (S1), this pin can also be used as a key return input from the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output in synchronization with the REM signal. CMOS push-pull High-level output (LED) 5 REM Infrared remote control transmission output. The output is active high. The carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 µs (@ f X = 4 MHz) using software. CMOS push-pull Low-level output 6 VDD Power supply - - 7 IC Internally connected pin - - 8 S3 Input port. This pin can also be used as a key return input from the key matrix. In input mode, the use of a pull-down resistor for the S3 port can be specified by software. If input mode is released by software, this pin is placed in the OFF mode and enters a high-impedance state. - 9 GND GND pin - - 10 S2 Input port. The use of the STOP mode release of the S2 port can be specified by software. When using this pin as a key input from the key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, this pin can be used as an input port that does not release the STOP mode even if the S2 port satisfies the release condition (at this time, a pull-down resistor is not connected internally.) - Input (high impedance, STOP mode release cannot be used) 11 to 14 KI0 to 4-bit input port. These pins can be used as key return inputs to the key matrix. The use of pull-down resistors can be specified by software in 4-bit units. - Input (low-level) KI3Note 2 Output Format CMOS push-pullNote 1 - After Reset High-level output High-impedance (OFF mode) High-impedance (OFF mode) Notes 1. Note that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 9 µPD6P8, 6P8A, 6P8B 1.2 PROM Programming Mode (1) µ PD6P8 Pin No. 1, 2 Symbol Function I/O D0 to D7 8-bit data I/O when writing/verifying program memory I/O CLK Clock input for updating address when writing/verifying program Input 15 to 20 3 memory 6 VDD Power supply ­ Supply +3 V to this pin when writing/verifying program memory. 7 XOUT Clock necessary for writing program memory. Connect a 4 MHz ceramic ­ 8 XIN resonator to these pins. 9 GND GND ­ 10 VPP Supplies voltage for writing/verifying program memory. ­ Input Apply +10.5 V to this pin. 11 to 14 MD0 to MD3 Input for selecting operation mode when writing/verifying program memory Input (2) µ PD6P8A Pin No. Symbol Function I/O 2 SO Serial data output when verifying program memory Output 3 SCLK Clock input when writing/verifying program memory Input 4 SI Serial data input when writing program memory Input 6 VDD Power supply ­ Supply +3 V to this pin when writing/verifying program memory. 7 XOUT Clock necessary for writing program memory. Connect a 4 MHz ceramic ­ 8 XIN resonator to these pins. 9 GND GND ­ 10 VPP Supplies voltage for writing/verifying program memory. ­ Input Apply +10.5 V to this pin. (3) µ PD6P8B Pin No. Symbol Function I/O 2 SO Serial data output when verifying program memory Output 3 SCLK Clock input when writing/verifying program memory Input 4 SI Serial data input when writing program memory Input 6 VDD Power supply ­ Supply +3 V to this pin when writing/verifying program memory. 9 GND GND ­ 10 VPP Supplies voltage for writing/verifying program memory. ­ Apply +10.5 V to this pin. 10 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 1.3 Pin I/O Circuits The I/O circuits of the µPD6P8, 6P8A, 6P8B pins are shown in partially simplified forms below. (4) S 0, S 3Note 2 (1) K I/O0 to K I/O7 Input buffer VDD Data Output latch P-ch OFF mode N-chNote 1 Selector Output disable Standby release N-ch Pull-down flag Input buffer N-ch (5) S1/LED VDD (2) K I0 to K I3 REM output latch Standby release P-ch Input buffer Output disable Standby release Pull-down flag N-ch N-ch Input buffer N-ch Pull-down flag (3) REM (6) S 2 Standby release VDD Input buffer P-ch Data Output latch N-ch STOP release ON/OFF N-ch Carrier generator Notes 1. The drive capability is held low. 2. µPD6P8B only Data Sheet U17848EJ5V0DS U17848EJ5V0DS 11 µPD6P8, 6P8A, 6P8B 1.4 Recommended Connection of Unused Pins The following connections are recommended for unused pins in the normal operation mode. Table 1-1. Connections for Unused Pins Connection Pin Inside the Microcontroller KI/O0 to K I/O7 Input mode Output mode - High-level output REM - ICNote - S1/LED Output mode (LED) setting S0, S3Note OFF mode setting S2 - KI0 to K I3 Note Outside the Microcontroller Leave open Directly connect these pins to GND - µPD6P8B only Caution The I/O mode and the pin output level are recommended to be fixed by setting them repeatedly in each loop of the program. 1.5 Notes on Using KI Pin After Reset In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup. 12 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 2. DIFFERENCES BETWEEN µPD67A PD67A, 67B, 68A, 68B, AND µPD6P8, 6P8A, 6P8B Table 2-1 shows the differences between the µPD67A PD67A, 67B, 68A, 68B, and µPD6P8, 6P8A, 6P8B. The only differences between these models are the program memory, RAM retention detection voltage, internal oscillator, POC detection voltage, and supply voltage; the other CPU functions and internal peripheral hardware are the same. The electrical specifications also differ slightly. For the electrical specifications, refer to the data sheet of each model. Table 2-1. Differences Between µPD67A PD67A, 67B, 68A, 68B, and µPD6P8, 6P8A, 6P8B Item ROM µPD6P8 µPD6P8A µPD6P8B µPD67A PD67A One-time PROM 2026 × 10 bits VPOC = 1.85 V (TYP.) detection voltage Internal oscillator µPD68A PD68A 1002 × 10 bits VPOC = 1.8 V POC detection voltage RAM retention µPD67B PD67B µPD68B PD68B Mask ROM 2026 × 10 bits VPOC = 1.5 V VPOC = 1.85 V VPOC = 1.5 V ­ (TYP.) (TYP.) (TYP.) VID = 1.4 V VID = 1.5 V V ID = 1.4 V VID = 1.5 V (TYP.) (TYP.) (TYP.) VID = 1.6 V V ID = 1.8 V (TYP.) (TYP.) (TYP.) (TYP.) VDD = 2.0 to 3.6 V VDD = 1.65 to 3.6 V fX = 4 MHz ­ (TYP.) Supply voltage VDD = 1.9 to 3.6 V VDD = 2.0 to 3.6 V VDD = 1.65 to 3.6 V Electrical specifications Some electrical specifications, such as data retention voltage and current consumption, differ. Refer to data sheet of each model for details. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 13 µPD6P8, 6P8A, 6P8B 3. INTERNAL CPU FUNCTIONS 3.1 Program Counter (PC): 11 Bits The program counter (PC) is a binary counter that holds the address information of the program memory. Figure 3-1. Program Counter Configuration PC PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The PC contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. After reset, the value of the PC becomes "000H". 3.2 Stack Pointer (SP): 1 Bit This is a 1-bit register that holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to 0. When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system reset signal is generated, and the PC becomes 000H. As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program. 3.3 Address Stack Register (ASR (RF): 11 Bits The address stack register saves the return address of the program after a subroutine call instruction is executed. The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM. The register holds the ASR value even after the RET instruction is executed. After reset, it holds the previous data (undefined when turning on the power). Caution If RF is accessed as the data memory, the higher 4 bits become undefined. Figure 3-2. Address Stack Register Configuration RF ASR 14 ASR10 ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 Data Sheet U17848EJ5V0DS U17848EJ5V0DS ASR4 ASR3 ASR2 ASR1 ASR0 µPD6P8, 6P8A, 6P8B 3.4 Program Memory (One-Time PROM): 2,026 Steps × 10 Bits The one-time PROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from FEAH to FFFH cannot be used in the test program area. Figure 3-3. Program Memory Map 10 bits 0 0 0H Page 0 3 F FH 4 0 0H Page 1 7E9H 7 EAH Test program areaNote 7 F FH Note The test program area is designed so that a program or data placed in either of them by mistake is returned to the 000H address. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 15 µPD6P8, 6P8A, 6P8B 3.5 Data Memory (RAM): 32 × 4 Bits The data memory, which is a static RAM consisting of 32 × 4 bits, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer. RF is also used as the ASR. After reset, R0 is cleared to 00H and R1 to RF retain the previous data (undefined when turning on the power). Figure 3-4. Data Memory Configuration R1n (higher 4 bits) R0n (lower 4 bits) Note 1 R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E Note 2 RF R1F R0F Notes 1. R0 alternately functions as the ROM data pointer (refer to 3.6 Data Pointer (DP). 2. RF alternately functions as the PC address stack (refer to 3.3 Address Stack Register (ASR (RF). 16 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 3.6 Data Pointer (DP): 12 Bits The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 4 bits by bits 4 to 7 of the P3 register (CR0). After reset, the pointer contents become 000H. Figure 3-5. Data Pointer Configuration P3 register b7 P3 b6 b5 b4 0 DP10 DP9 DP8 R10 DP7 DP6 R00 DP5 DP4 DP3 DP2 DP1 DP0 R0 3.7 Accumulator (A): 4 Bits The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various operations. After reset, the accumulator contents are left undefined. Figure 3-6. Accumulator Configuration A3 A2 A1 A0 A 3.8 Arithmetic and Logic Unit (ALU): 4 Bits The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple (mainly logical) operations. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 17 µPD6P8, 6P8A, 6P8B 3.9 Flags 3.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. · If the condition specified with the operand is met when the STTS instruction is executed · When standby mode is released. · When the release condition is met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Conversely, the status flag is cleared (to 0) in the following cases: · If the condition specified with the operand is not met when the STTS instruction is executed. · When the status flag has been set (to 1), the HALT instruction is executed, but the release condition is not met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Table 3-1. Conditions for Status Flag (F) to Be Set by STTS Instruction Operand Value of STTS Instruction Condition for Status Flag (F) to Be Set b3 b2 b1 b0 0 0 0 0 High level is input to at least one of KI pins. 0 1 1 High level is input to at least one of KI pins. 1 1 0 High level is input to at least one of KI pins. 1 0 1 The down counter of the timer is 0. 1 Either of the combinations of b2, b1, and b0 above. [The following condition is added in addition to the above.] High level is input to at least one of S0Note 1, S1Note 1, S2Note 2, or S 3Notes 1, 3 pins. Notes 1. The S0, S1, and S3 pins must be set to input mode (bits 0, 2, and 7 of the P4 register are set to 1, 0, and 1, respectively). 2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1). 3. µPD6P8B only 3.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: · If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the operand is 1. · If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1. · If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: · If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is 0. · If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0. · If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. · If the ORL instruction is executed. · When data is written to the accumulator by the MOV instruction or the IN instruction. 18 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 4. PORT REGISTERS (PX) The KI/O port, the KI port, the special ports (S0, S1/LED, S2, S3), and the control registers are treated as port registers. After reset, the port register values are as shown below. Figure 4-1. Port Register Configuration (µPD6P8, 6P8A) Port register After reset P0 FFH P10 KI/O7 P00 KI/O5 KI/O6 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 ××××11×1BNote 1 P1 P11 KI3 KI2 P01 KI1 KI0 S1/LED S0 S2 1 0000×000BNote 2 P3 (control register 0) P03 P13 DP11 DP10 DP9 RAM retention flag DP8 ­ ­ ­ P4 (control register 1) 26H P14 0 P04 KI S0/S1 S2 S1/LED mode KI/O mode Pull-down Pull-down STOP release 0 S0 mode Notes 1. ×: Refers to the value based on the KI and S2 pin state. 2. ×: Refers to the value based on decrease of power supply voltage (0 when VDD VID) Remark VID: RAM retention detection voltage Table 4-1. Relationship Between Ports and Reading/Writing (µPD6P8, 6P8A) Input Mode Port Name Read Output Mode Write Read Write KI/O Pin state Output latch Output latch Output latch KI Pin state - - - S0 Pin state - Note - S1/LED Pin state - Pin state - S2 Pin state - - - Note When in OFF mode, "1" is always read. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 19 µPD6P8, 6P8A, 6P8B Figure 4-2. Port Register Configuration (µPD6P8B) Port register After reset P0 FFH P10 KI/O7 P00 KI/O5 KI/O6 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 ××××11×0BNote 1 P1 P11 KI3 KI2 P01 KI1 KI0 S1/LED S0 S3Note 3 S2 0000×000BNote 2 P3 (control register 0) P03 P13 DP11 DP10 DP9 RAM retention flag DP8 ­ ­ ­ P4 (control register 1) P14 26H P04 S3 KI S0/S1 S3 pullS2 S1/LED mode KI/O mode modeNote 3 downNote 3 pull-down pull-down STOP release S0 mode Notes 1. ×: Refers to the value based on the KI and S2 pin state. 2. ×: Refers to the value based on decrease of power supply voltage (0 when VDD VID) 3. Use an actual device to emulate the S3 pin, because the emulator does not support S3 pin emulation. Remark VID: RAM retention detection voltage Table 4-2. Relationship Between Ports and Reading/Writing (µPD6P8B) Input Mode Port Name Read Output Mode Write Read Write KI/O Pin state Output latch Output latch Output latch KI Pin state - - - S 0, S 3 Pin state - Note S1/LED Pin state - Pin state S2 Pin state - - - - - Note When in OFF mode, "1" is always read for S0 and "0" is always read for S3. 20 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 4.1 K I/O Port (P0) The KI/O port is an 8-bit I/O port for key scan output. I/O mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. If a write instruction is executed, data can be written to the output latch regardless of input or output mode. After reset, the port is placed in output mode and the value of the output latch (P0) becomes 1111 1111B 1111B. The KI/O port incorporates a pull-down resistor, allowing pull-down in input mode only. Caution When a key is double-pressed, a high-level output and a low-level output may conflict at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The K I/O port is designed so that even when connected directly to VDD within the normal supply voltage range (VDD = 1.9 to 3.6 V), no problem occurs. Table 4-3. KI/O Port (P0) Bit b7 b6 b5 b4 b3 b2 b1 b0 Name K I/O7 K I/O6 K I/O5 K I/O4 K I/O3 K I/O2 K I/O1 K I/O0 b 0 to b7: When reading: In input mode, the KI/O pin's state is read. In output mode, the KI/O pin's output latch contents are read. When writing: Data is written to the KI/O pin's output latch regardless of input or output mode. 4.2 K I Port/Special Ports (P1) 4.2.1 K I port (P 11 : bits 4 to 7 of P1) The KI port is a 4-bit input port for key input. The pin state can be read. The use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4 register. After reset, a pull-down resistor is connected. 4.2.2 S 0 port (bit 2 of P1) The S0 port is an input/OFF mode port. The pin state can be read by setting this port to input mode using bit 0 of the P4 register. In input mode, the use of a pull-down resistor for the S0 and S1/LED port can be specified in 2-bit units by software using bit 4 of the P4 register. If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state. After reset, S0 is set to OFF mode, thus becoming high-impedance. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 21 µPD6P8, 6P8A, 6P8B 4.2.3 S 1/LED port (bit 3 of P1) The S1/LED port is an I/O port. Input or output mode can be set using bit 2 of the P4 register. The pin state can be read in both input mode and output mode. When in input mode, the use of a pull-down resistor for the S 0 and S 1 /LED ports can be specified in 2-bit units by software using bit 4 of the P4 register. When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote control transmission display pin (refer to 5. TIMER). After reset, S1/LED is placed in output mode, and a high level is output. 4.2.4 S2 port (bit 1 of P1) The S2 port is an input port. Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register. When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled (bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if the release condition is met (at this time, a pull-down resistor is not connected internally.) The state of the pin can be read in both cases. After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance state. 4.2.5 S 3 port (bit 0 of P1) ( µ PD6P8B only) The S3 port is an input/OFF mode port. The pin state can be read by setting this port to input mode using bit 7 of the P4 register. In input mode, the use of a pull-down resistor for the S3 port can be specified using bit 6 of the P4 register. If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that through current does not flow internally. In OFF mode, 0 can be read regardless of the pin state. After reset, S3 is set to OFF mode, thus becoming high-impedance. 22 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B Table 4-4. KI/Special Port Register (P1) (1) µ PD6P8 and 6P8A Bit b7 b6 b5 b4 b3 b2 b1 Name KI3 KI2 KI1 KI0 S1/LED S0 S2 Bit b7 b6 b5 b4 b3 b2 b1 Name KI3 KI2 KI1 KI0 S1/LED S0 S2 b0 Fixed to "1" (2) µ PD6P8B b0 : b0 S3 µPD6P8, 6P8A: Fixed to 1 µPD6P8B: In input mode, the state of the S3 pin is read (read only). In OFF mode, this bit is fixed to 0. b1 : The state of the S2 pin is read (read only). b2 : In input mode, the state of the S0 pin is read (read only). b3 : The state of the S1/LED pin is read regardless of input/output mode (read only). In OFF mode, this bit is fixed to 1. b4 to b7: The state of the KI pin is read (read only). Caution In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pulldown resistor connected). Data Sheet U17848EJ5V0DS U17848EJ5V0DS 23 µPD6P8, 6P8A, 6P8B 4.3 Control Register 0 (P3) Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0000 ×000BNote. Note ×: Refers to the value based on a decrease of power supply voltage (0 when VDD VID) Remark VID: RAM retention detection voltage Table 4-5. Control Register 0 (P3) b7Note Bit DP11 DP10 DP9 DP8 b3 RAM retention flag 0 0 0 0 0 Not retainable Fixed to 0 1 1 1 1 1 Retainable 0 0 0 0 0 Name Setting After reset b3 : b6 b5 b4 DP (Data Pointer) b2 b0 - 0 0 0 RAM retention flag. For function details, refer to 4.3.1 RAM retention flag (bit 3 of P3). b4 to b7: Specify the higher bits of the ROM data pointer (DP8 to DP11). Note Set b7 to 0 in the case of the µPD6P8, 6P8A, 6P8B. 24 b1 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 4.3.1 RAM retention flag (bit 3 of P3) The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped. This flag is at bit 3 of control register 0 (P3). It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage. If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it, set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM. Figure 4-3. Supply Voltage Transition and Detection Voltage (µPD6P8) VDD VPOC/VID POC detection voltage/ RAM retention detection voltage VPOC = VID = 1.8 V (TYP.) (A) 0V t (1) (2) (3) (4) RAM retention flag Set to 1 Flag contents are read (1) If the supply voltage rises after the battery has been set, and exceeds V POC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below V POC . At point (A) in the figure, the voltage is lower than V ID . Consequently, the RAM retention flag is cleared to 0. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this case, initialize the RAM by software. Cautions 1. The software developed for the µPD67A PD67A, 68A and 69A (using the RAM retention flag) can be used for the µPD6P8 as is. 2. Unlike the µPD67A PD67A, 68A and 69A, the RAM retention detection voltage of the µPD6P8 is the same as the POC detection voltage. When software is newly developed, it is not necessary to use the RAM retention flag if only the RAM is initialized by reset. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 25 µPD6P8, 6P8A, 6P8B Figure 4-4. Supply Voltage Transition and Detection Voltage (µPD6P8A, 6P8B) VDD POC detection voltage (Refer to 8. POC CIRCUIT) VPOC = 1.8 V (TYP.) RAM retention detection voltage VID = 1.6 V (TYP.) VPOC (A) VID (B) 0V t (1) (2) (3) (4) (5) (6) RAM retention flag Set to 1 Flag contents are read Flag contents are read (1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below V POC. At point (A) in the above figure, the RAM retention flag remains 1 because the supply voltage is higher than VID at this point. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that the contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software. (5) The device is reset if the supply voltage drops below V POC. At point (B) in the figure, the voltage is lower than V ID. Consequently, the RAM retention flag is cleared to 0. (6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this case, initialize the RAM by software. 26 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 4.4 Control Register 1 (P4) Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0010 0110B 0110B. Table 4-6. Control Register 1 (P4) (1) µ PD6P8 and 6P8A Bit b7 Name b6 b5 b4 KI S0/S1 b3 - - 0 Fixed Fixed 1 to 0 to 0 ON ON 0 0 1 0 b7 b6 b4 b2 S2 b3 b1 b0 S1/LED KI/O S0 Pull-down Pull-down STOP release mode Setting After reset OFF OFF mode mode S1 IN OFF Enable LED OUT IN 0 1 1 0 b2 b1 b0 S1/LED KI/O S0 Disable (2) µ PD6P8B Bit Name S3 mode S3 b5 KI S0/S1 S2 Pull-down Pull-down Pull-down STOP release mode mode OFF OFF OFF OFF Disable S1 IN OFF 1 After reset mode 0 Setting IN ON ON ON Enable LED OUT IN 0 0 1 0 0 1 1 0 b0: Specifies the input mode of the S0 port. 0 = OFF mode (high impedance); 1 = IN (input mode). b1: Specifies the I/O mode of the KI/O port. 0 = IN (input mode); 1 = OUT (output mode). b2: Specifies the I/O mode of the S1/LED port. 0 = S1 (input mode); 1 = LED (output mode). b3: Specifies the use of STOP mode release by S2 port (with/without pull-down resistor). 0 = disable (without pull-down); 1 = enable (with pull-down). b4: Specifies the use of a pull-down resistor in S0/S1 port input mode. 0 = OFF (not used); 1 = ON (used). b5: Specifies the use of a pull-down resistor for the KI port. 0 = OFF (not used); 1 = ON (used). b6: µPD6P8, 6P8A: Fixed to 0 µPD6P8B: Specifies the use of a pull-down resistor in S3 port input mode. 0 = OFF (not used); 1 = ON (used). b7: µPD6P8, 6P8A: Fixed to 0 µPD6P8B: Specifies the input mode of the S3 port. 0 = OFF mode (high impedance); 1 = IN (input mode). Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 27 µPD6P8, 6P8A, 6P8B 5. TIMER 5.1 Timer Configuration The timer is the block used for creating a remote control transmission pattern. As shown in Figure 5-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. Figure 5-1. Timer Configuration T T1 t9 t8 T0 t7 t6 t5 t4 t3 t2 9-bit down counter Zero detector Carrier synchronous circuit 28 t0 fX/64 Timer operation end signal (HALT # 101B release signal) S1/LED REM t1 Count clock Carrier signal Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 5.2 Timer Operation The timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (­1) in the cycle of 64/fX. If the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #×101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. The following relational expression applies between the timer's output time and the down counter's set value. Timer output time = (Set value + 1) × 64/f X ­ 4/f X In addition, when the timer is set successively, the timer output time is also 4/fX shorter than the total time. An example is shown below. Example When fX = 4 MHz MOV T, #3FFH STTS #05H HALT #05H MOV T, #232H STTS #05H HALT #05H In the case above, the timer output time is as follows. (Set value + 1) × 64/f X + (Set value + 1) × 64/f X ­ 4/f X = (511 + 1) × 64/4 + (50 + 1) × 64/4 ­ 4/4 = 9.007 ms Data Sheet U17848EJ5V0DS U17848EJ5V0DS 29 µPD6P8, 6P8A, 6P8B By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/ LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 5-1. Timer Output (at t9 = 1) S 1/LED Pin REM Pin Timer operating Low level High level (or carrier outputNote) Timer halting High level Low level Note The carrier output results if bit 9 (CARY) of the high-level period setting modulo register (MOD1) is cleared (to 0). Figure 5-2. Timer Output (When Carrier Is Not Output) 4/fX Timer output time: (Set value + 1) × 64/fX ­ 4/fX LED REM 30 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 5.3 Carrier Output 5.3.1 Carrier output generator The carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level periods (MOD1 and MOD0 respectively). Figure 5-3. Configuration of Remote Controller Carrier Generator M1 M11 M0 M10 M01 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 CARY Modulo register for setting the high-level period (MOD1) Carrier signal 0 t8 t7 t6 M00 t5 t4 t3 t2 t1 t0 Modulo register for setting the low-level period (MOD0)Note 1 Selector F/F Match Comparator 9-bit counter 2fX Multiplier fX Clear t9Note 2 fX Notes 1. Bit 9 of the modulo register for setting the low-level period (MOD0) is fixed to 0. 2. t9: Flag that enables timer output (timer block) (see Figure 5-1 Timer Configuration) The carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using the respective modulo registers. Each of these widths can be set in a range of 250 ns to 64 µs (@ f X = 4 MHz). The system clock multiplied by 2 is used for the 9-bit counter input (8 MHz when fX = 4 MHz). MOD0 and MOD1 are read and written using timer manipulation instructions. MOV A, M00 MOV M00, A MOV M0, #data10 MOV A, M01 MOV M01, A MOV M1, #data10 MOV A, M10 MOV M10, A MOV M0, @R0 MOV A, M11 MOV M11, A MOV M1, @R0 The values of MOD0 and MOD1 can be calculated from the following expressions. MOD0 = (2 × fX × (1 ­ D) × T) ­ 1 MOD1 = (2 × fX × D × T) ­ 1 Caution Be sure to input values in range of 001H to 1FFH to MOD0 and MOD1. Remark D: Carrier duty ratio (0 < D < 1) fX: Input clock (MHz) T: Carrier cycle (µs) Data Sheet U17848EJ5V0DS U17848EJ5V0DS 31 µPD6P8, 6P8A, 6P8B 5.3.2 Carrier output control Remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register for setting the high-level period (MOD1). When performing carrier output, be sure to set the timer operation after setting the MOD0 and MOD1 values. Note that a malfunction may occur if the values of MOD0 and MOD1 are changed while carrier is being output from the REM pin. Executing the timer manipulation instruction starts the carrier output from the low level. If the timer's down counter reaches 0 during carrier output, carrier output is stopped and the REM pin becomes low level. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after first becoming low level following the set period of high level. Figure 5-4. Timer Output (When Carrier Is Output) Timer manipulation instruction Timer output time: (Set value + 1) × 64/fX ­ 4/fX LED REM 4/fX tL tH Note Note If the down counter reaches 0 while the carrier output is high level, carrier output will stop after becoming low level. 32 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B Output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of MOD1 and the timer output enable flag (t9), and the value of the timer block's 9-bit down counter (t0 to t8). Table 5-2. REM Pin Output MOD1 Bit 9 (CARY) Timer Output Enable Flag (Timer Block t9) 9-bit Down Counter (Timer Block t0 to t8) REM Pin - - - 0 Low-level output 0 Other than 0 0 1 Carrier outputNote 1 High-level output Note Input values in the range of 001H to 1FFH to MOD0 and MOD1. Caution MOD0 and MOD1 must be set while the REM pin is low level (t9 = 0 or t 0 to t8 = 0). Table 5-3. Example of Carrier Frequency Settings (fX = 4 MHz) tH ( µs) Setting Value MOD1 tL (µs) T (µs) fC (kHz) Duty MOD0 01H 01H 0.25 0.25 0.5 2,000 1/2 07H 0BH 1.0 1.5 2.5 400 2/5 13H 13H 2.5 2.5 5.0 200 1/2 27H 27H 5.0 5.0 10 100 1/2 41H 41H 8.25 8.25 16.5 60.6 1/2 41H 85H 8.25 16.75 25 40 1/3 45H 89H 8.75 17.25 26.0 38.5 1/3 45H 8BH 8.75 17.5 26.25 38.10 1/3 45H 8CH 8.75 17.625 26.375 37.9 1/3 47H 91H 9.0 18.25 27.25 36.7 1/3 48H 94H 9.125 18.625 27.75 36.0 1/3 69H D5H 13.25 26.75 40.0 25 1/3 77H 77H 15.0 15.0 30.0 33.3 1/2 C7H C7H 25.0 25.0 50.0 20 1/2 FFH FFH 32.0 32.0 64.0 15.6 1/2 tH tL Carrier signal T Data Sheet U17848EJ5V0DS U17848EJ5V0DS 33 µPD6P8, 6P8A, 6P8B 5.4 Software Control of Timer Output The timer output can be controlled by software. As shown in Figure 4-5, a pulse with a minimum width of 64/f X ­ 4/fX can be output. Figure 5-5. Output of Pulse of 1-Instruction Cycle Width . . . MOV T, #0000000000B 0000000000B; low-level output from the REM pin . . . MOV T, #1000000000B 1000000000B; high-level output from the REM pin MOV T, #0000000000B 0000000000B; low-level output from the REM pin . . . 4/fX 64/fX ­ 4/fX LED REM 34 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 6. STANDBY FUNCTION 6.1 Outline of Standby Function To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, have been provided available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed to a low level. In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port registers, etc. immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 6-1. Statuses During Standby Mode STOP Mode Setting instruction HALT instruction Clock oscillator Oscillation stopped HALT Mode CPU · Operation halted Data memory Oscillation continued · Immediately preceding status retained Operation Accumulator statuses Flag · Immediately preceding status retained · 0 (When 1, the flag is not placed in the standby mode.) CY Port register Timer F · Immediately preceding status retained · Immediately preceding status retained · Operation halted · Operable (The count value is reset to "0") Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released. 2. When standby mode is released, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its release condition is met, then the system does not enter the standby mode. However, the status flag (F) is set (1). Data Sheet U17848EJ5V0DS U17848EJ5V0DS 35 µPD6P8, 6P8A, 6P8B 6.2 Standby Mode Setting and Release The standby mode is set with the HALT #b3b 2b1b 0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT instruction. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has been already met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, the system does not enter HALT mode as long as the status flag (F) remains set (to 1) and thus sometimes performs an unintended operation. In this case, the intended operation can be realized by executing the STTS instruction immediately after setting the timer to clear (to 0) the status flag. #03H ;To check the KI pin status. MOV T, #0xxH ;To set the timer STTS #05H ;To clear the status flag STTS . . Example HALT (During this time, be sure not to execute an instruction that may set the status flag.) #05H ;To set HALT mode Table 6-2. Addresses Executed After Standby Mode Release Release Condition Address Executed After Release Reset Release condition shown in Table 6-3 36 Address 0 The address following the HALT instruction Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B Table 6-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions Operand Value of HALT Instruction Setting Mode Precondition for Setup Release Condition b3 b2 b1 b0 0 0 0 0 STOP All KI/O pins are high-level output. High level is input to at least one of KI pins. 0 1 1 STOP All KI/O pins are high-level output. High level is input to at least one of KI pins. 1 1 0 STOPNote 1 The KI/O0 pin is high-level output. High level is input to at least one of KI pins. 1 Any of the STOP [The following condition is added in addition to the above.] combinations of - of S0, S1, S2, and S3Note 3 pinsNote 2. b2b1b0 above 0/1 1 0 High level is input to at least one 1 HALT - When the timer's down counter is 0 Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the standby mode can be released. 2. At least one of the S0, S1, S 2, and S3 pins (the pin used for releasing the standby mode) must be specified as follows: S0, S1, S3 pins: Input mode (specified by bits 0, 2, and 7 of the P4 register) S2 pin: Use of STOP mode release enabled (specified by bit 3 of the P4 register) 3. µPD6P8B only Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer's down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer's down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 37 µPD6P8, 6P8A, 6P8B 6.3 Standby Mode Release Timing (1) STOP mode release timing Figure 6-1. STOP Mode Release by Release Condition WaitNote HALT instruction (STOP mode) Standby release signal Operation mode STOP mode Oscillation Oscillation stopped HALT mode Operation mode Oscillation Clock Note The wait time is as follows. · µPD6P8: 10 + 286/fX + Oscillation growth time (µs) · µPD6P8A: 10 + 1024/fX + Oscillation growth time (µs) · µPD6P8B: 10 + 1024/fX (µs) Caution When a release condition is met in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time. (2) HALT mode release timing Figure 6-2. HALT Mode Release by Release Condition Standby release signal HALT instruction (HALT mode) Operation mode HALT mode Oscillation Clock 38 Data Sheet U17848EJ5V0DS U17848EJ5V0DS Operation mode µPD6P8, 6P8A, 6P8B 7. RESET A system reset is effected by the following causes: · When the POC circuit has detected low power-supply voltage · When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed · When the accumulator is 0H when the RLZ instruction is executed · When stack pointer overflows or underflows Table 7-1. Hardware Statuses After Reset · Reset by On-Chip POC Circuit During Operation · Reset by the On-Chip POC Circuit During · Reset by Other Factors Note 1 Standby Mode Hardware PC 000H SP (1 bit) 0B Data R0 = DP 000H memory R1 to RF Undefined Accumulator (A) Undefined Status flag (F) 0B Carry flag (CY) 0B Timer (10 bits) Port register 000H P0 FFH P1 µPD6P8, 6P8A: ×××× 11×1BNote 2, µPD6P8B: ×××× 11×0BNote 2 Control register P3 P4 0000 ×000BNote 3 26H Notes 1. The following resets are available. · Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) · Reset when executing the RLZ instruction (when A = 0) · Reset by stack pointer's overflow or underflow 2. ×: Refers to the value by the KI or S2 pin status. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 3. ×: Refers to the value based on a decrease of power supply voltage (0 when VDD VID). Remark VID: RAM retention detection voltage Data Sheet U17848EJ5V0DS U17848EJ5V0DS 39 µPD6P8, 6P8A, 6P8B 8. POC CIRCUIT The POC circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the battery is replaced. Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 2. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 3. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released due to supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 40 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 8.1 Functions of POC Circuit The POC circuit has the following functions: · Generates an internal reset signal when VDD V POC. · Cancels an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC detection voltage. VDD Operating ambient temperature TA = ­ 40 to + 85°C 3.6 V Clock frequency fX = 3.5 to 4.5 MHz 1.9 V POC detection voltage VPOC = 1.8 V (TYP.)Note 3 VPOC Approx. 1.7 V 0V t Internal reset signal Operation mode Reset Note 1 Reset Note 2 Notes 1. Actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode. The oscillation stabilization wait time is about 534/fX to 918/fX (when about 134 to 230 µs; @ fX = 4 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect. 3. The POC detection voltage (VPOC) varies between approximately 1.7 to 1.9 V; thus, the reset may be canceled at a power supply voltage smaller than the guaranteed range (VDD = 1.9 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC detection voltage. Therefore, there is no malfunction occurring due to a shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Caution 3 in 8. POC CIRCUIT). 8.2 Oscillation Check at Low Supply Voltage A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status in a product that actually includes a POC circuit, as follows. Connect a storage oscilloscope to the X OUT pin so that the oscillation status can be measured. Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage V DD from 0 V (making sure to avoid V DD > 3.6V). At first (during VDD < approx. 1.7 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC detection voltage (VPOC = 1.8 V (TYP.), the voltage of the XOUT pin jumps to about 0.5VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If by any chance the oscillation start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 41 µPD6P8, 6P8A, 6P8B 9. SYSTEM CLOCK OSCILLATOR (µPD6P8, 6P8A) The system clock oscillator consists of oscillators for ceramic resonators (fX = 3.5 to 4.5 MHz). Figure 9-1. System Clock XOUT XIN GND Ceramic resonator The system clock oscillator stops oscillating when a reset is applied or in STOP mode. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. 42 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 10. INSTRUCTION SET 10.1 Machine Language Output by Assembler The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. Figure 10-1. Example of Assembler Output (10 Bits Extended to 16 Bits) In the case of "ANL A, @R0H" 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 Extended bits 0 0 0 0 1 0 0 0 0 = FAF0 1 0 0 0 = E6F8 Extended bits In the case of "OUT P0, #data8" 0 1 1 1 Extended bits 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 Extended bits Data Sheet U17848EJ5V0DS U17848EJ5V0DS 43 µPD6P8, 6P8A, 6P8B 10.2 Circuit Symbol Description A: Accumulator ASR: Address stack register addr: Program memory address CY: Carry flag data4: 4-bit immediate data data8: 8-bit immediate data data10: 10-bit immediate data F: Status flag M0: Modulo register for setting the low-level period M00: Modulo register for setting the low-level period (lower 4 bits) M01: Modulo register for setting the low-level period (higher 4 bits) M1: Modulo register for setting the high-level period M10: Modulo register for setting the high-level period (lower 4 bits) M11: Modulo register for setting the high-level period (higher 4 bits) PC: Program Counter Pn: Port register pair (n = 0, 1, 3, 4) P0n: Port register (lower 4 bits) P1n: Port register (higher 4 bits) ROMn: Bit n of the program memory's (n = 0 to 9) Rn: Register pair R0n: Data memory (General-purpose register; n = 0 to F) R1n: Data memory (General-purpose register; n = 0 to F) SP: Stack Pointer T: Timer register T0: Timer register (lower 4 bits) T1: 44 Timer register (higher 4 bits) (×): Content addressed with × Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table Accumulator Operation Instructions Mnemonic Instruction Code Operand 1st Word 2nd Word A, R0n FBEn (A) (A) A, R1n FAEn Instruction Cycle CY A3 · Rmn3 A, @R0H FAF0 (A) (A) ANL Instruction Length Operation 3rd Word (Rmn) m = 0, 1 n = 0 to F 1 1 (P13), (R0)7-4 CY A3 · ROM7 (A) (A) FBF0 A, @R0L (P13), (R0)3-0 CY A3 · ROM3 FBF1 data4 (A) (A) A, #data4 data4 2 CY A3 · data4 3 A, R0n FDEn (A) (A) (Rmn) m = 0, 1 n = 0 to F A, R1n FCEn CY 0 A, @R0H ORL FCF0 1 (A) (A) (P13), (R0)7-4 CY 0 A, @R0L (A) (A) (P13), (R0)3-0 FDF0 CY 0 A, #data4 FDF1 data4 (A) (A) data4 2 CY 0 A, R0n F5En (A) (A) (Rmn) m = 0, 1 n = 0 to F A, R1n F4En CY A3 · Rmn3 A, @R0H XRL F4F0 (A) (A) (P13), (R0)7-4 1 CY A3 · ROM7 A, @R0L (A) (A) (P13), (R0)3-0 F5F0 CY A3 · ROM3 A, #data4 F5F1 data4 (A) (A) data4 2 CY A3 · data4 3 INC A F4F3 (A) (A) + 1 if (A) = 0 1 CY 1 else CY 1 RL A FCF3 (An+1) (A n), (A 0) (A3) RLZ A FEF3 if A = 0 CY A3 reset else (An+1) (An), (A0) (A3) CY A3 Data Sheet U17848EJ5V0DS U17848EJ5V0DS 45 µPD6P8, 6P8A, 6P8B I/O Instructions Mnemonic Instruction Code Operand - - (A) (Pmn) FEF8 + n - - CY 0 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 Mnemonic FBF8 + n - - (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 FAF8 + n - - CY A3 · Pmn3 A, P0n FDF8 + n - - (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 FCF8 + n - - CY 0 A, P0n F5F8 + n - - (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 F4F8 + n - - CY A3 · Pmn3 Instruction Code Operand 1st Word OUT Remark Instruction - A, P0n 1 Instruction - - A, P1n XRL - A, P1n ORL E5F8 + n E4F8 + n A, P1n ANL P0n, A P1n, A 1 OUT FFF8 + n Cycle 3rd Word A, P0n Instruction Length 2nd Word A, P1n IN Instruction Operation 1st Word Pn, #data8 E6F8 + n 2nd Word Operation 3rd Word Length (Pn) data8 data8 n = 0, 1, 3, 4 2 Cycle 1 Pn: P1n to P0n are handled in pairs. Data Transfer Instruction Mnemonic Instruction Code Operand 1st Word 2nd Word Instruction Length A, R0n FFEn (A) (Rmn) A, R1n FEEn Cycle CY 0 A, @R0H MOV Instruction Operation 3rd Word FEF0 (A) (P13), (R0)7-4 m = 0, 1 n = 0 to F 1 1 CY 0 A, @R0L (A) (P13), (R0)3-0 FFF0 CY 0 A, #data4 R0n, A (A) data4 CY 0 E5En R1n, A Mnemonic FFF1 data4 E4En (Rmn) (A) Instruction Code Operand 2 1st Word 2nd Word m = 0, 1 n = 0 to F Instruction Remark 46 Rn, #data8 E6En data8 - (R1n to R0n) data8 - - (R1n to R0n) (P13), (R0)n = 1 to F E7En Instruction Length Operation Cycle 3rd Word Rn, @R0 MOV 1 Rn: R1n to R0n are handled in pairs. Data Sheet U17848EJ5V0DS U17848EJ5V0DS n = 0 to F 2 1 1 µPD6P8, 6P8A, 6P8B Branch Instructions Mnemonic Instruction Code Operand 1st Word JMP 2nd Word 2 addr addr if CY = 1 addr else PC PC + 2 addr (Page 2) ECF4 addr addr (Page 3) EAF4 addr PC addr addr (Page 0) EDF1 addr if CY = 0 addr (Page 1) EBF1 addr else PC PC + 2 addr (Page 2) EDF4 addr addr (Page 0) EEF1 addr if F = 1 addr (Page 1) F0F1 addr else PC PC + 2 addr (Page 2) EEF4 addr addr (Page 3) F0F4 addr addr (Page 0) EFF1 addr if F = 0 addr (Page 1) F1F1 addr else PC PC + 2 addr (Page 2) EFF4 addr addr (Page 3) F1F4 JNF addr addr (Page 3) EBF4 JF 1 PC addr addr (Page 0) ECF1 addr (Page 1) EAF1 JNC Cycle addr addr (Page 3) E9F4 Instruction addr addr (Page 2) E8F4 PC addr addr addr (Page 1) E9F1 JC addr (Page 0) E8F1 Instruction Length Operation 3rd Word addr PC addr PC addr Caution 0 to 4, which refer to PAGE0 to 4, are not written when describing mnemonics. Subroutine Instructions Mnemonic Instruction Code Operand 1st Word E8F1 addr E9F1 E8F4 addr addr (Page 3) E6F2 E9F4 Cycle addr addr (Page 2) E6F2 RET addr (Page 0) E6F2 Instruction 3rd Word addr (Page 1) E6F2 CALL Instruction Length Operation 2nd Word addr E8F2 SP SP + 1, ASR PC, PC addr 3 2 PC ASR, SP SP ­ 1 1 1 Caution 0 to 4, which refer to PAGE0 to 4, are not written when describing mnemonics. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 47 µPD6P8, 6P8A, 6P8B Timer Operation Instructions Mnemonic Instruction Code Operand 1st Word 2nd Word A, T0 FFFF (A) (Tn) FEFF FFF6 (A) (M0n) A, M01 FEF6 CY 0 A, M10 FFF7 (A) (M1n) A, M11 FEF7 CY 0 T0, A E5FF (Tn) (A) T1, A F4FF (T) n 0 M00, A E5F6 E4F6 n = 0, 1 1 1 Instruction Instruction n = 0, 1 n = 0, 1 n = 0, 1 (M0n) (A) M01, A CY 0 M10, A E5F7 E4F7 n = 0, 1 (M1n) (A) M11, A CY 0 n = 0, 1 Instruction Code Operand Operation 1st Word 2nd Word T, #data10 E6FF data10 (T) data10 M0, #data10 E6F6 data10 (M0) data10 M1, #data10 MOV Cycle CY 0 A, M00 Mnemonic Instruction Length A, T1 MOV Instruction Operation 3rd Word 3rd Word Length E6F7 data10 (M1) data10 2 T, @R0 F4FF (T) (P13), (R0) M0, @R0 E7F6 (M0) (P13), (R0) M1, @R0 E7F7 Cycle 1 (M1) (P13), (R0) 1 Others Mnemonic Instruction Code Operand Instruction Operation 1st Word 2nd Word HALT #data4 E2F1 data4 3rd Word Standby mode STTS #data4 E3F1 data4 if statuses match Length else R0n E3En FAF3 NOP 48 E0E0 F1 F1 F0 if A = 0FH else 2 F0 if statuses match else SCAF Instruction 1 n = 0 to F CY 1 CY 0 PC PC + 1 Data Sheet U17848EJ5V0DS U17848EJ5V0DS Cycle 1 µPD6P8, 6P8A, 6P8B 10.4 Accumulator Manipulation Instructions ANL A, R0n ANL A, R1n Instruction code: 1 1 0 1 R4 0 R3 R2 R1 R0 1 Function: (A) (A) Cycle count: (Rmn) m = 0, 1 n = 0 to F CY A 3 · Rmn 3 The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L Instruction code: 1 1 0 1 0/1 1 0 0 0 0 Cycle count: 1 Function: (A) (A) (P13), (R0) 7-4 (in the case of ANL A, @R0H) CY A 3 · ROM 7 (A) (A) (P13), (R0) 3-0 (in the case of ANL A, @R0L) CY A 3 · ROM 3 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10 to R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. · Program memory (ROM) organization b7 b9 b6 b5 b4 b8 H b3 b2 b1 b0 L Valid bits at the time of accumulator manipulation ANL A, #data4 Instruction code: 1 1 0 1 1 1 0 0 0 1 Cycle count: 1 Function: (A) (A) 0 0 0 0 0 0 d3 d2 d1 d0 data4 CY A3 · data4 3 The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 49 µPD6P8, 6P8A, 6P8B ORL A, R0n ORL A, R1n Instruction code: 1 1 1 0 R4 0 R3 R2 R1 R0 Cycle count: 1 Function: (A) (A) (Rmn) m = 0, 1 n = 0 to F CY 0 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L Instruction code: 1 1 1 0 0/1 1 0 0 0 0 Cycle count: 1 Function: (A) (A) (P13), (R0) 7-4 (in the case of ORL A, @R0H) (A) (A) (P13), (R0) 3-0 (in the case of ORL A, @R0L) CY 0 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. ORL A, #data4 Instruction code: 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 Cycle count: 1 Function: (A) (A) data4 CY 0 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n Instruction code: 1 0 1 0 R4 0 R3 R2 R1 R0 Cycle count: 1 Function: (A) (A) (Rmn) m = 0, 1 n = 0 to F CY A 3 · Rmn 3 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. 50 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B XRL A, @R0H XRL A, @R0L Instruction code: 1 0 1 0 0/1 1 0 0 0 0 Cycle count: 1 Function: (A) (A) (P13), (R0)7-4 (in the case of XRL A, @R0H) CY A 3 · ROM 7 (A) (A) (P13), (R0)3-0 (in the case of XRL A, @R0L) CY A 3 · ROM 3 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 Instruction code: 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 Cycle count: 1 Function: (A) (A) data4 CY A 3 · data43 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A Instruction code: 1 0 1 0 0 1 0 0 1 1 Cycle count: 1 Function: (A) (A) + 1 if A = 0 else CY 1 CY 0 The accumulator contents are incremented (+1). RL A Instruction code: 1 1 1 0 0 1 0 0 1 1 Cycle count: 1 Function: (A n + 1) (An), (A 0) (A3) CY A 3 The accumulator contents are rotated anticlockwise bit by bit. RLZ A Instruction code: 1 1 1 1 0 1 0 0 1 1 Cycle count: 1 Function: if A = 0 else reset (A n + 1) (An), (A 0) (A3) CY A 3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 51 µPD6P8, 6P8A, 6P8B 10.5 I/O Instructions IN A, P0n IN A, P1n Instruction code: 1 1 1 1 P4 1 1 P2 P1 P0 Cycle count: 1 Function: (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY 0 The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A Instruction code: 0 0 1 0 P4 1 1 P2 P1 P0 Cycle count: 1 Function: (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4 The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n Instruction code: 1 1 0 1 P4 1 1 P2 P1 P0 Cycle count: 1 Function: (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A 3 · Pmn The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n Instruction code: 1 1 1 0 P4 1 1 P2 P1 P0 Cycle count: 1 Function: (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY 0 The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n Instruction code: 1 0 1 0 P4 1 1 P2 P1 P0 Cycle count: 1 Function: (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A 3 · Pmn The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator. 52 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B OUT Pn, #data8 Instruction code: 0 0 1 1 0 1 1 P2 P1 P0 : 0 d7 d6 d5 d4 0 d3 d2 d1 d0 Cycle count: 1 Function: (Pn) data8 n = 0, 1, 3, 4 The immediate data is transferred to port Pn. In this case, port Pn refers to P1n to P0n operating in pairs. 10.6 Data Transfer Instructions MOV A, R0n MOV A, R1n Instruction code: 1 1 1 1 R4 0 R3 R2 R1 R0 Cycle count: 1 Function: (A) (Rmn) m = 0, 1 n = 0 to F CY 0 The register Rmn contents are transferred to the accumulator. MOV A, @R0H Instruction code: 1 1 1 1 0 1 0 0 0 0 Cycle count: 1 Function: (A) (P13), (R0) 7-4 CY 0 The higher 4 bits (b7 b6 b5 b4) of the program memory specified by control register P13 and register pair R10-R00 R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L Instruction code: 1 1 1 1 1 1 0 0 0 0 Cycle count: 1 Function: (A) (P13), (R0) 3-0 CY 0 The lower 4 bits (b3 b2 b1 b0) of the program memory specified by control register P13 and register pair R10 to R00 are transferred to the accumulator. b8 is ignored. · Program memory (ROM) contents @R0H b9 b7 b6 @R0L b5 b4 b8 b3 b2 b1 b0 MOV A, #data4 Instruction code: : 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 Cycle count: 1 Function: (A) data4 CY 0 The immediate data is transferred to the accumulator. Data Sheet U17848EJ5V0DS U17848EJ5V0DS 53 µPD6P8, 6P8A, 6P8B MOV R0n, A MOV R1n, A Instruction code: 0 0 1 0 R4 0 R3 R2 R1 R0 Cycle count: 1 Function: (Rmn) (A) m = 0, 1 n = 0 to F The accumulator contents are transferred to register Rmn. MOV Rn, #data8 Instruction code: 0 0 1 1 0 0 R3 R2 R1 R0 : 0 d7 d6 d5 d4 0 d3 d2 d1 d0 Cycle count: 1 Function: (R1n-R0n) data8 n = 0 to F The immediate data is transferred to the register. Using this instruction, registers operate as register pairs. The pair combinations are as follows: R0: R10 - R00 R1: R11 - R01 : RE: R1E - R0E RF: R1F - R0F Lower column Higher column MOV Rn, @R0 Instruction code: 0 0 1 1 1 0 R3 R2 R1 R0 Cycle count: 1 Function: (R1n-R0n) (P13), R0) n = 1 to F The program memory contents specified by control register P13 and register pair R10 to R00 are transferred to register pair R1n to R0n. The program memory consists of 10 bits and has the following state after the transfer to the register. Program memory b9 b7 b6 b5 b4 b8 b3 b2 b1 b0 b9 @R0 b7 b6 b5 R1n b4 b8 b3 b2 b1 b0 R0n The higher 2 to 4 bits of the program memory address are specified by the control register (P13). 54 Data Sheet U17848EJ5V0DS U17848EJ5V0DS µPD6P8, 6P8A, 6P8B 10.7 Branch Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows. µPD6P8, 6P8A, 6P8B (ROM: 2K steps): Pages 0, 1 JMP addr Page 0 0 1 0 0 0 1 0 0 0 1 ; page 1 0 1 0 0 1 1 0 0 0 1 Page 2 Instruction code: 0 1 0 0 0 1 0 1 0 0 ; page 3 0 1 0 0 1 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 Cycle count: 1 Function: PC addr The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to a0). JC addr Page 0 0 1 1 0 0 1 0 0 0 1 ; page 1 0 1 0 1 0 1 0 0 0 1 Page 2 Instruction code: 0 1 1 0 0 1 0 1 0 0 ; page 3 0 1 0 1 0 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 Cycle count: 1 Function: if CY = 1 else PC addr PC PC + 2 If the carry flag CY