PD4516421A M12939EJ3V0DS00 PD4516421AG5-A80-9NF PD4516421AG5-A10-9NF - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD4516421A, 4516821A, 4516161A for Rev. P 16M-bit Synchronous DRAM Description The

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 16M-bit Synchronous DRAM Description The µPD4516421A PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 × 4 × 2, 1,048,576 × 8 × 2 and 524,288 × 16 × 2 (word × bit × bank), respectively. The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). The synchronous DRAMs are packaged in 44-pin TSOP (II) (×4, ×8) and 50-pin TSOP (II) (×16). Features · Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge · Pulsed interface · Possible to assert random column address in every cycle · Dual internal banks controlled by A11 (Bank Select) · Programmable burst-length (1, 2, 4, 8, Full Page) · Programmable wrap sequence (Sequential/Interleave) · Programmable CAS latency (2, 3) · Automatic precharge and controlled precharge · CBR (Auto) refresh and self refresh · ×4, ×8, ×16 organization · Single + 3.3 ±0.3 V power supply · LVTTL compatible · Byte control (×16) by LDQM and UDQM · 2,048 refresh cycles/32 ms · Burst termination by Burst Stop command and Precharge command The information in this document is subject to change without notice. Document No. M12939EJ3V0DS00 M12939EJ3V0DS00 (3rd edition) Date Published April 1998 N CP(K) Printed in Japan The mark shows major revised points. © 1997 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Ordering Information Part number Organization (word × bit × bank) µPD4516421AG5-A80-9NF PD4516421AG5-A80-9NF µPD4516421AG5-A10-9NF PD4516421AG5-A10-9NF µPD4516421AG5-A10B-9NF PD4516421AG5-A10B-9NF Clock frequency MHz (MAX.) 125 100 44-pin Plastic TSOP(II) 100 2M×4×2 (400 mil) µPD4516421AG5-A12-9NF PD4516421AG5-A12-9NF 83 µPD4516821AG5-A80-9NF PD4516821AG5-A80-9NF 125 µPD4516821AG5-A10-9NF PD4516821AG5-A10-9NF µPD4516821AG5-A10B-9NF PD4516821AG5-A10B-9NF 100 44-pin Plastic TSOP(II) 100 1M×8×2 (400 mil) µPD4516821AG5-A12-9NF PD4516821AG5-A12-9NF 83 µPD4516161AG5-A80-9NF PD4516161AG5-A80-9NF 125 µPD4516161AG5-A10-9NF PD4516161AG5-A10-9NF µPD4516161AG5-A10B-9NF PD4516161AG5-A10B-9NF 100 50-pin Plastic TSOP(II) 100 512 K × 16 × 2 (400 mil) µPD4516161AG5-A12-9NF PD4516161AG5-A12-9NF 83 µPD4516421AG5-A80L-9NF PD4516421AG5-A80L-9NF 125 µPD4516421AG5-A10L-9NF PD4516421AG5-A10L-9NF µPD4516421AG5-A10BL-9NF PD4516421AG5-A10BL-9NF 100 44-pin Plastic TSOP(II) 100 2M×4×2 (400 mil) µPD4516421AG5-A12L-9NF PD4516421AG5-A12L-9NF 83 µPD4516821AG5-A80L-9NF PD4516821AG5-A80L-9NF 125 µPD4516821AG5-A10L-9NF PD4516821AG5-A10L-9NF µPD4516821AG5-A10BL-9NF PD4516821AG5-A10BL-9NF 100 44-pin Plastic TSOP(II) 100 1M×8×2 (400 mil) µPD4516821AG5-A12L-9NF PD4516821AG5-A12L-9NF 83 µPD4516161AG5-A80L-9NF PD4516161AG5-A80L-9NF 125 µPD4516161AG5-A10L-9NF PD4516161AG5-A10L-9NF µPD4516161AG5-A10BL-9NF PD4516161AG5-A10BL-9NF µPD4516161AG5-A12L-9NF PD4516161AG5-A12L-9NF 2 Package 512 K × 16 × 2 100 50-pin Plastic TSOP(II) 100 (400 mil) 83 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Part Number [ ×4, ×8 ] µ PD4516821AG5 PD4516821AG5 - A10L NEC Memory Synchronous DRAM Low Power Memory Density Minimum Cycle Time 16 : 16M bits 80 : 8 ns (125 MHz) 10 : 10 ns (100 MHz) 12 : 12 ns (83 MHz) Organization 4 : ×4 8 : ×8 Number of Banks RNote( 1 : 1Bank) 2 : 2Bank Low Voltage Interface A : 3.3 ± 0.3 V 1 : LVTTL Package Version [ ×16 ] G5 : TSOP(II) 161 Organization 16 : ×16 Number of Banks & Interface 1 : 2Bank, LVTTL Note R: Reserved 3 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Pin Configurations [µPD4516421A PD4516421A] 44-pin Plastic TSOP(II) (400 mil) µPD4516421AG5-9NF PD4516421AG5-9NF VCC 1 44 VSS NC 2 43 NC VSSQ 3 42 VSSQ DQ0 4 41 DQ3 VCCQ 5 40 VCCQ NC 6 39 NC VSSQ 7 38 VSSQ DQ1 8 37 DQ2 VCCQ 9 36 VCCQ NC 10 35 NC NC 11 34 NC WE 12 33 DQM CAS 13 32 CLK RAS 14 31 CKE CS 15 30 NC A11 16 29 A9 A10 17 28 A8 A0 18 27 A7 A1 19 26 A6 A2 20 25 A5 A3 21 24 A4 VCC 22 23 VSS A0 to A11Note : Address inputs DQ0 to DQ3 : Data inputs/outputs CLK : System clock input CKE : Clock enable CS : Chip select RAS : Row address strobe CAS : Column address strobe WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A9 : Column address inputs NC : No connection A11 4 Note A0 to A10 : Row address inputs : Bank select µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P [µPD4516821A PD4516821A] 44-pin Plastic TSOP(II) (400 mil) µPD4516821AG5-9NF PD4516821AG5-9NF VCC 1 44 VSS DQ0 2 43 DQ7 VSSQ 3 42 VSSQ DQ1 4 41 DQ6 VCCQ 5 40 VCCQ DQ2 6 39 DQ5 VSSQ 7 38 VSSQ DQ3 8 37 DQ4 VCCQ 9 36 VCCQ NC 10 35 NC NC 11 34 NC WE 12 33 DQM CAS 13 32 CLK RAS 14 31 CKE CS 15 30 NC A11 16 29 A9 A10 17 28 A8 A0 18 27 A7 A1 19 26 A6 A2 20 25 A5 A3 21 24 A4 VCC 22 23 VSS A0 to A11 Note : Address inputs DQ0 to DQ7 : Data inputs/outputs CLK : System clock input CKE : Clock enable CS : Chip select RAS : Row address strobe CAS : Column address strobe WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A8 : Column address inputs NC : No connection A11 Note A0 to A10 : Row address inputs : Bank select 5 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P [µPD4516161A PD4516161A] 50-pin Plastic TSOP(II) (400 mil) µPD4516161AG5-9NF PD4516161AG5-9NF VCC 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VCCQ 7 44 VCCQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VCCQ 13 38 VCCQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 VSS A0 to A11 Note : Address inputs DQ0 to DQ15 : Data inputs/outputs CLK : System clock input CKE : Clock enable CS : Chip select RAS : Row address strobe CAS : Column address strobe WE : Write enable UDQM : Upper DQ mask enable LDQM : Lower DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A7 : Column address inputs NC : No connection A11 6 Note A0 to A10 : Row address inputs : Bank select µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Block Diagram Clock Generator Address CAS WE Bank A Column Address Buffer & Burst Counter DQM Column Decoder & Latch Circuit Data Control Circuit Input & Output Buffer RAS Bank B Sense Amplifier Control Logic CS Command Decoder Mode Register Row Address Buffer & Refresh Counter Latch Circuit CKE Row Decoder CLK DQ 7 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CONTENTS 1. Input/Output Pin Function . 10 2. Commands . 11 3. Simplified State Diagram . 14 4. Truth Table . 15 4.1 Command Truth Table . 15 4.2 DQM Truth Table . 15 4.3 CKE Truth Table . 15 4.4 Operative Command Table . 16 4.5 Command Truth Table for CKE . 19 4.6 Command Truth Table for Two Banks Operation . 20 5. Initialization . 21 6. Programming the Mode Register . 22 7. Mode Register . 23 7.1 Burst Length and Sequence . 24 8. Address Bits of Bank-Select and Precharge . 25 9. Precharge . 26 10. Auto Precharge . 27 10.1 Read with Auto Precharge . 27 10.2 Write with Auto Precharge . 28 11. Read/Write Command Interval . 29 11.1 Read to Read Command Interval . 29 11.2 Write to Write Command Interval . 29 11.3 Write to Read Command Interval . 30 11.4 Read to Write Command Interval . 31 12. Burst Termination . 32 12.1 Burst Stop Command . 32 12.2 Precharge Termination . 33 12.2.1 Precharge Termination in READ cycle . 33 12.2.2 Precharge Termination in WRITE cycle . 34 13. Electrical Specifications . 35 13.1 13.2 AC Parameters for Read Timing . 42 13.3 Relationship between Frequency and Latency . 43 13.4 8 AC Parameters for Write Timing . 41 Mode Register Write . 44 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 13.5 Power on Sequence and Auto Refresh . 45 13.6 CS Function . 46 13.7 Clock Suspension during Burst Read (using CKE Function) . 47 13.8 Clock Suspension during Burst Write (using CKE Function) . 49 13.9 Power Down Mode and Clock Mask . 51 13.10 CBR Refresh . 52 13.11 Self Refresh (entry and exit) . 53 13.12 Random Column Read (Page with same bank) . 54 13.13 Random Column Write (Page with same bank) . 56 13.14 Random Row Read (Pingpong banks) . 58 13.15 Random Row Write (Pingpong banks) . 60 13.16 READ and WRITE . 62 13.17 Interleaved Column READ Cycle . 64 13.18 Interleaved Column WRITE Cycle . 66 13.19 Auto Precharge after Read Burst . 68 13.20 Auto Precharge after Write Burst . 70 13.21 Full Page READ Cycle . 72 13.22 Full Page WRITE Cycle . 74 13.23 Byte Write Operation . 76 13.24 Burst Read and Single Write (Option) . 77 13.25 Full Page Random Column Read . 78 13.26 Full Page Random Column Write . 79 13.27 PRE (Precharge) Termination of Burst . 80 14. Package Drawings . 82 15. Recommended Soldering Conditions . 84 9 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 1. Input/Output Pin Function Pin name Input/Output Function CLK Input CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE Input CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the µPD4516 PD4516×××A suspends operation. When the µPD4516 PD4516×××A is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. CS Input CS low starts the command input cycle. When CS is high, commands are ignored but operations continue. RAS, CAS, WE Input RAS, CAS and WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 - A11 Input Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the activate command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A9 at the CLK rising edge in the read or write command cycle. It depends on the bit organization: A0 - A9 for ×4 device, A0 - A8 for ×8 device and A0 - A7 for ×16 device. A11 is the bank select signal (BS). In command cycle, A11 low selects bank A and A11 high selects bank B. A10 defines the precharge mode. When A10 is high in the precharge command cycle, both banks are precharged; when A10 is low, only the bank selected by A11 is precharged. When A10 high in read or write command cycle, the precharge start automatically after the burst access. DQM UDQM LDQM Input DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 - DQ15 Input/Output DQ pins have the same function as I/O pins on a conventional DRAM. VCC VSS VCCQ VSSQ (Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. 10 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 2. Commands Mode register set command Fig. 1 Mode register set command (CS, RAS, CAS, WE = Low) CLK The µPD4516 PD4516×××A has a mode register that defines how the device CKE operates. In this command, A0 through A11 are the data input pins. After CS power on, the mode register set command must be executed to initialize the device. The mode register can be set only when both banks are in idle state. During 2CLK (tRSC) following this command, the µPD4516 PD4516×××A cannot accept any other commands. H RAS CAS WE A11 A10 Add Activate command Fig. 2 Row address strobe and bank active command (CS, RAS = Low, CAS, WE = High) CLK The µPD4516 PD4516×××A has two banks, each with 2,048 rows. This command activates the bank selected by A11 (BS) and a row address selected by A0 through A10. This command corresponds to a conventional DRAM's RAS falling. CKE H CS RAS CAS WE A11 (Bank select) A10 Add Precharge command (CS, RAS, WE = Low, CAS = High) Row Row Fig. 3 Precharge command CLK CKE This command begins precharge operation of the bank selected by A11 (BS). When A10 is High, both banks are precharged, regardless of A11. When A10 is Low, only the bank selected by A11 is precharged. A11 low selects bank A and A11 high selects bank B. After this command, the µPD4516 PD4516×××A can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's RAS rising. H CS RAS CAS WE A11 (Bank select) A10 (Precharge select) Add 11 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Write command Fig. 4 Column address and write command (CS, CAS, WE = Low, RAS = High) CLK If the mode register is in the burst write mode, this command sets the CKE burst start address given by the column address to begin the burst write CS operation. The first write data in burst can be input with this command with H RAS subsequent data on following clocks. CAS WE A11 (Bank select) A10 Add Read command Col. Fig. 5 Column address and read command (CS, CAS = Low, RAS, WE = High) CLK Read data is available after CAS latency requirements have been met. CKE This command sets the burst start address given by the column address. CS H RAS CAS WE A11 (Bank select) A10 Add CBR (auto) refresh command (CS, RAS, CAS= Low, WE, CKE = High) Fig. 6 Auto refresh command CLK CKE This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, both banks must be precharged. CS RAS CAS After this cycle, both banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the µPD4516 PD4516×××A cannot accept any other command. WE A11 (Bank select) A10 Add 12 Col. H µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Self refresh entry command Fig. 7 Self refresh entry command (CS, RAS, CAS, CKE = Low, WE = High) CLK After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the µPD4516 PD4516×××A exits the self CKE CS refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, both banks must be precharged. RAS CAS WE A11 (Bank select) A10 Add Burst stop command Fig. 8 Burst stop command in Full Page mode (CS, WE = Low, RAS, CAS = High) CLK This command terminates the current burst operation. CKE H CS RAS CAS WE A11 (Bank select) A10 Add No operation Fig. 9 No operation (CS = Low, RAS, CAS, WE = High) CLK CKE This command is not a execution command. No operations begin or terminate by this command. H CS RAS CAS WE A11 (Bank select) A10 Add 13 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 3. Simplified State Diagram Self Refresh LF SE t LF exi SE MRS Mode Register Set REF IDLE CBR Refresh CK E ACT CK E Power Down CKE ROW ACTIVE CKE ST CKE to Read WRITE CKE CKE CKE Write ina tio n) erm CKE cha Pre E( WRITEA CKE READA SUSPEND E( PR n) atio min Pre ch ter arg rge Precharge CKE READA READ SUSPEND et CKE POWER ON Read READ PR WRITEA SUSPEND Au Wr WRITE SUSPEND T ad h wit e ad rg Re cha pre to PRE W BS Re Au Write ite wi pre th ch arg e B rite Active Power Down Precharge Automatic sequence Manual input 14 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 4. Truth Table 4.1 Command Truth Table CKE Function CS Symbol n-1 RAS CAS WE A11 A10 A9A0 n Device deselect DESL H × H × × × × × × No operation NOP H × L H H H × × × Burst stop BST H × L H H L × × × Read READ H × L H L H V L V Read with auto precharge READA H × L H L H V H V Write WRIT H × L H L L V L V Write with auto precharge WRITA H × L H L L V H V Bank activate ACT H × L L H H V V V Precharge select bank PRE H × L L H L V L × Precharge all banks PALL H × L L H L × H × Mode register set MRS H × L L L L L L V CS RAS CAS WE Address 4.2 DQM Truth Table CKE Function DQM Symbol n-1 n U L Data write/output enable ENB H × L Data mask/output disable MASK H × H Upper byte write enable/output enable ENBU H × L × Lower byte write enable/output enable ENBL H × × L Upper byte write inhibit/output disable MASKU H × H × Lower byte write inhibit/output disable MASKL H × × H 4.3 CKE Truth Table CKE Current state Function Symbol n-1 n Activating Clock suspend mode entry H L × × × × × Any Clock suspend L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle CBR refresh command REF H H L L L H × Idle Self refresh entry SELF H L L L L H × Self refresh Self refresh exit L H L H H H × L H H × × × × Idle Power down entry H L × × × × × Power down Power down exit L H × × × × × H: High level, L: Low level ×: High or Low level (Don't care), V: Valid Data input 15 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 4.4 Operative Command TableNotes1, 2 Current state (1/3) CAS WE H × × × × DESL Nop or Power down 3 H H × × NOP or BST Nop or Power down 3 L H L H BA, CA, A10 READ/READA ILLEGAL 4 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF/SELF Refresh or Self refresh L L L L Op-Code MRS Mode register accessing H × × × × DESL Nop L H H × × NOP or BST Nop L H L H BA, CA, A10 READ/READA Begin read:Determine AP 6 L H L L BA, CA, A10 WRIT/WRITA Begin write:Determine AP 6 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Precharge 7 L Row active RAS L Idle CS Address Command Action Notes L L H × REF/SELF ILLEGAL 5 L L Op-Code MRS ILLEGAL × × × DESL Continue burst to end Row active H H H × NOP Continue burst to end Row active H H L × BST Burst stop Row active L H L H BA, CA, A10 READ/READA Term burst, new read:Determine AP 8 L H L L BA, CA, A10 WRIT/WRITA Term burst, start write:Determine AP 8, 9 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Term burst, precharging L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end Write recovering L H H H × NOP Continue burst to end Write recovering L H H L × BST Burst stop Row active L H L H BA, CA, A10 READ/READA Term burst, start read:Determine AP 8, 9 L H L L BA, CA, A10 WRIT/WRITA Term burst, new write:Determine AP 8 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Term burst, precharging 10 L L L H × REF/SELF ILLEGAL L 16 L × L Write L H L Read L L L Op-Code MRS ILLEGAL µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P (2/3) Current state CS RAS CAS WE Read with auto H × × × × DESL Continue burst to end Precharging L H H H × NOP Continue burst to end Precharging L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 4 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL ILLEGAL 4 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end Write L H H H × NOP precharge Write with auto Address Command precharge Action Notes recovering with auto precharge Continue burst to end Write recovering with auto precharge L H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 4 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL ILLEGAL 4 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop Enter idle after tRP L H H H × NOP Nop Enter idle after tRP L H H L × BST Nop Enter idle after tRP L H L H BA, CA, A10 READ/READA ILLEGAL 4 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Nop Enter idle after tRP L Precharging H L L H × REF/SELF ILLEGAL L Row activating L L L Op-Code MRS ILLEGAL H × × × × DESL Nop Enter row active after tRCD L H H H × NOP Nop Enter row active after tRCD L H H L × BST Nop Enter row active after tRCD L H L H BA, CA, A10 READ/READA ILLEGAL 4 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4, 11 L L H L BA, A10 PRE/PALL ILLEGAL 4 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 17 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P (3/3) Current state CAS WE × × × × DESL Nop Enter row active after tDPL L H H H × NOP Nop Enter row active after tDPL L H H L × BST Nop Enter row active after tDPL L H L H BA, CA, A10 READ/READA Start read, Determine AP L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL ILLEGAL 4 L L L H × REF/SELF ILLEGAL L recovering RAS H Write CS Address Command Action Notes L L L Op-Code MRS ILLEGAL 9 H × × × × DESL Nop Enter precharge after tDPL H H H × NOP Nop Enter precharge after tDPL H H L × BST Nop Enter precharge after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL 4, 9 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL ILLEGAL 4 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop Enter idle after tRC L H H × × NOP/BST Nop Enter idle after tRC L H L × × READ/WRIT ILLEGAL L L H × × ACT/PRE/PALL ILLEGAL L L L × × REF/SELF/MRS ILLEGAL H × × × × DESL Nop Enter idle after tRSC L H H H × NOP Nop Enter idle after tRSC L H H L × BST ILLEGAL L H L × × READ/WRITE ILLEGAL L recovering with L L Write L × × × ACT/PRE/PALL/ ILLEGAL auto precharge Refreshing Mode register accessing REF/SELF/MRS Notes 1. H: High level, L: Low level, ×: High or Low level (Don't care), V: Valid data input 2. All entries assume that CKE was active (High level) during the preceding clock cycle. 3. If both banks are idle, and CKE is inactive (Low level), µPD4516 PD4516×××A will enter Power down mode. All input buffers except CKE will be disabled. 4. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 5. If both banks are idle, and CKE is inactive (Low level), µPD4516 PD4516×××A will enter Self refresh mode. All input buffers except CKE will be disabled. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied. 18 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 4.5 Command Truth Table for CKENote 1 Current state CKE CKE n-1 n H INVALID, CLK(n-1) would exit S.R. H H × × × × S.R. Recovery H L H H × × S.R. Recovery H L H L × × ILLEGAL H L L × × × ILLEGAL L × × × × × Maintain S.R. H H H × × × × Idle after tRC H L H H × × Idle after tRC H L H L × × ILLEGAL H L L × × × ILLEGAL L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL H L L L × × × ILLEGAL H × × × × × L H × × × × × EXIT P.D. Idle L L × × × × × Maintain power down mode H H H × × × Refer to operations in Operative Command Table H H L H × × Refer to operations in Operative Command Table H H L L H × Refer to operations in Operative Command Table H H L L L H × Refresh H H L L L L Op-Code Refer to operations in Operative Command Table H L H × × × Refer to operations in Operative Command Table H L L H × × Refer to operations in Operative Command Table H L L L H × Refer to operations in Operative Command Table H L L L L H × Self refresh H L L L L L Op-Code Refer to operations in Operative Command Table L × × × × × × Power down H × × × × × Refer to operations in Operative Command Table L than listed × H Any state other × H Row active × H Both banks idle × H (P.D.) × L Power down × L recovery WE L Self refresh CAS L (S.R.) RAS L Self refresh CS Address Action × × × × × Power down H H × × × × Notes INVALID, CLK(n-1) would exit P.D. × 2 2 3 Refer to operations in Operative Command Table H L × × × × × Begin clock suspend next cycle L H × × × × × Exit clock suspend next cycle L L × × × × × Maintain clock suspend above 3 Notes 1. H: High level, L: Low level, X: High or low level (Don't care) 2. Self refresh can be entered only from the both banks idle state. Power down can be entered from the both banks idle state or row active state. 3. Must be legal command as defined in Operative Command Table. 19 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 4.6 Command Truth Table for Two Banks Operation Notes 1, 2 CS H × × × × × × NOP Any Any L H H H × × × NOP Any Any L H H L × × × BST (R/W/A)0(I/A)1 A0(I/A)1 I0(I/A)1 I0(I/A)1 (R/W/A)1(I/A)0 A1(I/A)0 I1(I/A)0 I1(I/A)0 (R/W/A)1(I/A)0 RP1(I/A)0 Action H CA H CA A1(R/W)0 RP1A0 L CA (R/W/A)1(I/A)0 R1(I/A)0 L CA A1(R/W)0 R1A0 L H CA (R/W/A)0(I/A)1 RP0(I/A)1 L H CA A0(R/W)1 RP0A1 L L CA (R/W/A)0(I/A)1 R0(I/A)1 L Read L CA A0(R/W)1 R0A1 (R/W/A)1(I/A)0 W1(I/A)0 L CA A1(R/W)0 W1A0 H CA (R/W/A)0(I/A)1 WP0(I/A)1 H CA A0(R/W)1 WP0A1 L CA (R/W/A)0(I/A)1 W0(I/A)1 L CA A0(R/W)1 W0A1 H RA I1Any0 A1Any0 L RA I0Any1 A0Any1 × H × (R/W/A/I)0(I/A)1 I0I1 × H × (R/W/A/I)1(I/A)0 I1I0 H L × (R/W/A/I)1(I/A)0 I1(I/A)0 H L × (I/A)1(R/W/A/I)0 I1(R/W/A/I)0 L L × (R/W/A/I)0(I/A)1 I0(I/A)1 L L CA L H L L L WP1(I/A)0 WP1A0 L L (R/W/A)1(I/A)0 A1(R/W)0 L H CA CA H H H H H L H H L L H H L H A9 - A0 H H L A10 H L H BA "TO" State Note 4 CAS L WE "FROM" State Note 3 RAS L × (I/A)0(R/W/A/I)1 I0(R/W/A/I)1 × × Refresh I0I1 I0I1 Mode Register I0I1 I0I1 L L L H × L L L L Op-Code Write Activate Row Precharge Access Notes 1. Logic level abbreviations H: High level, L: Low level, ×: High or low level (Don't care) Pin name abbreviation BA: Bank address (A11) 20 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 2. State abbreviations I = Idle A = Row active R = Read with No precharge (No precharge is posted) W = Write with No precharge (No precharge is posted) RP = Read with auto precharge (Precharge is posted) WP = Write with auto precharge (Precharge is posted) Any = Any State X0Y1 = Y1X0 = Bank A is in state "X", Bank B is in state "Y" (X/Y)0Z1 = Z1(X/Y)0 = Bank A is in state "X" or "Y", Bank B is in state "Z" 3. If the µPD4516 PD4516×××A is in a state other than above listed in the "From State" column, the command is illegal. 4. The states listed under "To" might not be entered on the next clock cycle. Timing restrictions apply. 5. Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100-µs or longer pause must precede any signal toggling. (2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2CLK minimum) pause must be satisfied as well. (4) Two or more CBR (Auto) refresh must be performed. Remarks 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the Precharge command is issued to ensure data bus Hi-Z. 21 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A11 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options : A11 through A7 CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2CLK have elapsed. CAS Latency CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. The table on page 43 shows the relationship of CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. The table on the page 24 shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequential sequence supports the full page length. 22 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 7. Mode Register 11 10 9 8 7 0 0 0 0 1 11 10 9 8 7 × × 1 0 0 11 10 9 8 7 1 6 5 4 3 2 1 0 0 JEDEC Standard Test Set (refresh counter test) 6 5 4 LTMODE 6 5 3 2 WT 4 3 1 0 BL 2 1 Burst Read and Single Write (for Write Through Cache) 0 Use in future 11 10 9 8 7 6 5 4 3 2 1 0 × × × 1 1 V V V V V V V 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 LTMODE WT BL Vender Specific V = Valid × = Don't care Mode Register Set Burst length Bits2-0 000 001 010 011 100 101 110 111 Wrap type 0 1 Latency mode WT = 0 1 2 4 8 R R R Full page WT = 1 1 2 4 8 R R R R Sequential Interleave Bits6-4 000 001 010 011 100 101 110 111 CAS latency R R 2 3 R R R R Remark R: Reserved Mode Register Write Timing CLK CKE CS RAS CAS WE A0 - A11 Mode Register Write 23 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 7.1 Burst Length and Sequence [Burst of Two] Starting Address (column address A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [Burst of Four] Starting Address (column address A1 - A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [Burst of Eight] Starting Address (column address A2 - A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 (for 2 M × 8 device), 1,024 (for 4 M × 4 device) and 256 (for 1 M × 16 device). 24 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 8. Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (Activate command) A0 A1 Select Bank A "Activate" command Select Bank B "Activate" command 0 1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A10 0 0 1 (Precharge command) A11 0 1 × Result Precharge Bank A Precharge Bank B Precharge All Banks × : Don't care disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst) 0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 1 (CAS strobes) enables Read/Write commands for Bank A enables Read/Write commands for Bank B 0 1 Precharge for Bank A CLK CKE Precharge for Bank B CLK H CKE Precharge for All Banks CLK H CKE CS CS CS RAS RAS RAS CAS CAS CAS WE WE WE A10 A10 A10 A11 A11 H A11 25 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 9. Precharge The precharge command can be issued anytime after tRAS(MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. CAS latency = 2 : One clock earlier than the last read data. CAS latency = 3 : Two clocks earlier than the last read data. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 CLK CAS latency = 2 PRE Read Command Q1 DQ Q2 Q3 Hi-Z Q4 CAS latency = 3 Command Read PRE DQ Q1 Q2 Q3 Q4 Hi-Z (tRAS must be satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter "tDPL" must be satisfied. The tDPL(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks are calculated by dividing tDPL (MIN.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency Write 2 ­1 +tDPL (MIN.) 3 26 Read ­2 +tDPL (MIN.) µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 10. Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and precharge begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on both the CAS latency programmed into the mode register and whether read or write cycle. 10.1 Read with Auto Precharge During a read cycle, the auto precharge begins one clock earlier (CAS latency of 2) or two clocks earlier (CAS latency of 3) the last data word output. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CAS latency = 2 Command Auto precharge starts READA B Hi-Z QB1 DQ QB2 QB3 QB4 CAS latency = 3 Command READA B Auto precharge starts Hi-Z DQ QB1 QB2 QB3 QB4 (tRAS must be satisfied) Remark READA means Read with Auto precharge 27 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 10.2 Write with Auto Precharge During a write cycle, the auto precharge begins one clock after the last data word input to the device (CAS latency of 2 or 3). Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CAS latency = 2 Auto precharge starts Command WRITA B Hi-Z DQ DB1 DB2 DB3 DB4 CAS latency = 3 Command Auto precharge starts WRITA B Hi-Z DQ DB1 DB2 DB3 DB4 (tRAS must be satisfied) Remark WRITA means Write with Auto precharge In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency Write 2 ­1 +1 3 28 Read ­2 +1 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 11. Read/Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after CAS latency, even if the previous READ operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction. Burst length = 4, CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 QA1 QB1 QB2 QB3 T8 QB4 CLK Command Read A Read B Hi-Z DQ 1cycle 11.2 Write to Write Command Interval During a write cycle, when new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write commnad. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1. Each Write command can be issued in every clock without any restriction. Burst length = 4, CAS latency = 2 T0 T1 T2 T3 T4 T5 DB2 DB3 T6 T7 T8 DB4 CLK Command Write A Write B DA1 DB1 Hi-Z DQ 1cycle 29 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 11.3 Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 QB1 QB2 QB3 QB4 QB1 QB2 QB3 T8 CLK CAS latency = 2 Command Write A Read B Hi-Z DQ DA1 1cycle CAS latency = 3 Command Write A Read B Hi-Z DQ 30 DA1 QB4 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 11.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The data bus must be Hi-Z using DQM before WRITE. Burst length = 4 T0 T1 T2 Read T3 T4 T5 D2 D3 T6 T7 T8 Write D4 CLK Command DQM Hi-Z DQ D1 1cycle READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command. Burst length = 8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 D2 D3 D2 D3 CLK CAS latency = 2 Command Read Write DQM DQ Q1 Q2 Q3 D1 Hi-Z is necessary CAS latency = 3 Command Read Write DQM DQ Q1 Q2 D1 Hi-Z is necessary 31 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 12. Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. 12.1 Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to Hi-Z after the CAS latency from the burst stop command. Burst length = X, CAS latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read BST CAS latency = 2 Hi-Z DQ Q1 Q2 Q3 Q1 Q2 CAS latency = 3 Hi-Z DQ Q3 Remark BST: Burst stop command During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command. Burst length = X, CAS latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Write BST CAS latency = 2, 3 DQ Hi-Z D1 Remark BST: Burst stop command 32 D2 D3 D4 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 12.2 Precharge Termination 12.2.1 Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2, the read data will remain valid until one clock after the precharge command. Burst length = X, CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK Read Command PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) When CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Burst length = X, CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Read PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) 33 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 12.2.2 Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X, CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK Write Command PRE ACT DQM Hi-Z DQ D1 D2 D3 D4 D5 tRP (tRAS must be satisfied) When CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X, CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Write ACT PRE DQM DQ D1 D2 D3 D4 D5 Hi-Z tRP (tRAS must be satisfied) 34 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 13. Electrical Specifications · All voltage are referenced to VSS (GND). · After power up, wait more than 100 µs and then, execute Power on sequence and Auto Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Rating Unit VCC, VCCQ ­1.0 to +4.6 V Voltage on input pin relative to GND VT ­1.0 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 1 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg ­55 to +125 °C Voltage on power supply pin relative to GND Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage Condition High level input voltage TYP. MAX. Unit 3.0 VCC MIN. 3.3 3.6 V 0.3Note 1 V VIH 2.0 Low level input voltage VIL ­0.3Note 2 VCC + +0.8 V Operating ambient temperature TA 0 70 °C Notes 1. VIH (MAX.) = VCC + 2.0 V (Pulse width 3 ns) 2. VIL (MIN.) = ­2.0 V (Pulse width 3 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Symbol Condition MIN. TYP. MAX. Unit A0 to A11 2.5 4 pF CI2 Data input/output capacitance CI1 CLK, CKE, CS, RAS, CAS, WE, DQM, UDQM, LDQM 2.5 4 pF CI/O DQ0 to DQ15 4 6 pF 35 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Operating current Symbol ICC1 Test condition Burst length=1 Maximum CAS Grade Unit Notes latency ×4 ×8 ×16 CL = 2 tRC tRC (MIN.) ­80 100 105 110 ­10 100 105 110 IO = 0 mA ­10B 85 90 One bank active ­12 85 90 95 95 mA CL = 3 1 ­80 110 115 120 ­10 110 115 120 ­10B 90 95 100 ­12 90 95 100 Active standby current in Power down mode Active standby current in Non power down mode Operating current (Burst mode) CKE VIL (MAX.) tCK = 15 ns 3 3 3 ICC2PS CKE VIL (MAX.) tCK = 2 2 2 ICC2N CKE VIH (MIN.) tCK = 15 ns CS VIH (MIN.) Input signals are changed one time during 30 ns. 25 25 25 CKE VIH (MIN.) tCK = Input signals are stable. 6 6 6 ICC3P CKE VIL (MAX.) tCK = 15 ns 3 3 3 ICC3PS CKE VIL (MAX.) tCK = 2 2 2 ICC3N CKE VIH (MIN.) tCK = 15 ns CS VIH (MIN.) Input signals are changed one time during 30 ns. 28 28 30 ICC3NS Precharge standby current in Non power down mode ICC2P ICC2NS Precharge standby current in Power down mode CKE VIH (MIN.) tCK = Input signals are stable. 12 12 ICC4 tCK tCK (MIN.) mA mA mA CL = 2 mA 15 ­80 95 105 110 ­10 75 85 90 ­10B 75 85 IO = 0 mA 90 All banks active ­12 65 75 80 mA CL = 3 2 mA 3 ­80 110 120 125 ­10 90 100 105 ­10B 90 100 105 ­12 ICC5 tRC = 100 ns ­80 90 90 90 ­10 CL = 2 tCK = MIN. 95 90 90 90 ­10B 90 90 Refresh current 80 90 90 ­12 90 ­80 90 90 90 ­10 90 90 90 ­10B 90 90 CL = 3 90 90 90 ­12 Self refresh Current ICC6 CKE 0.2V 90 90 90 ­* 1 1 1 mA ­*L 250 250 250 µA 36 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current II (L) 0 VI VCC, VCCQ = VCC, all other pins not under test = 0 V ­1.0 +1.0 µA Output leakage current IO(L) DOUT is disabled, 0 VO VCCQ ­1.5 +1.5 µA High level output voltage VOH IO = ­4 mA 2.4 Low level output voltage VOL IO = +4 mA V 0.4 V 37 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions · AC measurements assume tT = 1 ns. · Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. · If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). · An access time is measured at 1.4 V. tCK tCH CLK 2.0 V 1.4 V 0.8 V tSetup Input tHold 2.0 V 1.4 V 0.8 V tAC tOH Output 38 tCL µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Synchronous Characteristics ­80 Parameter ­10 ­10B ­12 Symbol Unit MIN. Clock cycle time MAX. MIN. MAX. MIN. MAX. MIN. Note MAX. CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) 10 (100 MHz) 12 (83 MHz) ns CAS latency = 2 tCK2 10 (100 MHz) 13 (77 MHz) 13 (77 MHz) 15 (67 MHz) ns Access time from CAS latency = 3 tAC3 6 6 7 8 ns 1 CLK CAS latency = 2 tAC2 6 8 8 8 ns 1 CLK high level width tCH 3 3 3.5 4 ns CLK low level width tCL 3 3 3.5 4 ns Data-out hold time tOH 3 3 3 3 ns Data-out low-impedance time tLZ 0 0 0 0 ns CAS latency = 3 tHZ3 3 6 3 6 3 7 3 8 ns CAS latency = 2 tHZ2 3 6 3 8 3 8 3 8 ns Data-in setup time tDS 2.0 2.0 2.5 3.0 ns Data-in hold time tDH 1.0 1.0 1.0 1.5 ns Address setup time tAS 2.0 2.0 2.5 3.0 ns Address hold time tAH 1.0 1.0 1.0 1.5 ns CKE setup time tCKS 2.0 2.0 2.5 3.0 ns CKE hold time tCKH 1.0 1.0 1.0 1.5 ns CKE setup time (Power down exit) tCKSP 2.0 2.0 2.5 3.0 ns Command (CS, RAS, CAS, WE, DQM) setup time tCMS 2.0 2.0 2.5 3.0 ns Command (CS, RAS, CAS, WE, DQM) hold time tCMH 1.0 1.0 1.0 1.5 ns Data-out highimpedance time 1 Notes 1. Output load 1.4 V Z = 50 50 Output 50 pF 39 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P Asynchronous Characteristics ­80 Parameter ­10 ­10B Unit MIN. MAX. MIN. REF to REF/ACT Command period tRC 70 ACT to PRE Command period tRAS 48 PRE to ACT Command period tRP 20 Delay time ACT to READ/WRITE Command tRCD 20 ACT(0) to ACT(1) Command period tRRD Data-in to PRE Command period Data-in to ACT (REF) CAS latency = 3 Command (Auto CAS latency = 2 precharge) period Mode register set cycle time MAX. 20 ­* ­*L 40 MAX. MAX. ns 60 120,000 ns 26 30 ns 20 26 30 ns 16 20 20 24 ns tDPL 8 10 10 12 ns tDAL3 1CLK + 20 1CLK + 20 1CLK + 26 1CLK + 30 ns tDAL2 1CLK + 20 1CLK + 20 1CLK + 26 1CLK + 30 ns tRSC 2 2 2 2 CLK 0.5 120,000 30 50 1 90 MIN. 90 tREF 70 MIN. tT Transition time Refresh time ­12 Symbol 120,000 30 60 1 120,000 30 1 30 ns 32 32 32 32 ms 64 64 64 64 ms Note 13.1 AC Parameters for Write Timing (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE Auto Precharge Start for Bank A tCKS tCMS tCMH tCKH Auto Precharge Start for Bank B CS CAS WE A11 A10 ADD tAS tAH DQM DQ tDS tDH L Hi-Z tRCD tRRD tDAL tDPL tRP tRC Bank A Activate Command Bank A Precharge Command Bank A Write Command without Auto precharge Bank A Activate Command Bank B Write Command with Auto precharge Bank B Activate Command Bank A Write Command with Auto precharge Bank A Activate Command 41 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 42 13.2 AC Parameters for Read Timing (Burst length = 2, CAS latency = 2) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL Auto precharge Start for Bank B CKE tCKS tCMS tCMH tCKH CS RAS WE A11 A10 ADD tAS tAH L DQM tAC DQ tAC tHZ Hi-Z tRCD tLZ tOH tOH tRAS tRP tRRD tRC Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command with Auto precharge Bank A Activate Command µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 13.3 Relationship between Frequency and Latency Speed version Clock cycle time [ns] ­80 ­10 ­10B ­12 8 10 10 13 10 13 12 15 125 100 100 77 100 77 83 67 CAS latency 3 2 3 2 3 2 3 2 [tRCD] 3 2 2 2 3 2 3 2 RAS latency (CAS latency + [tRCD]) 6 4 5 4 6 4 6 4 [tRC] 9 7 7 6 9 7 8 6 [tRAS] 6 5 5 4 6 5 5 4 [tRRD] 2 2 2 2 2 2 2 2 [tRP] 3 2 2 2 3 2 3 2 [tDPL] 1 1 1 1 1 1 1 1 [tDAL] 4 3 3 3 4 3 4 3 [tRSC] 2 2 2 2 2 2 2 2 Frequency [MHz] 43 44 13.4 Mode Register Write (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE tRSC H 2CLK (MIN.) CS RAS WE A11 A10 ADDRESS KEY ADD DQM Hi-Z DQ All Banks Precharge Command Register Write Command tRP Activate Command is valid µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.5 Power on Sequence and Auto Refresh T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK Clock signal is necessary CKE tRSC High level is necessary 2 refresh cycles are necessary CS CAS WE A11 A10 ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ All Banks Precharge Command is necessary Register Write Command is necessary 45 tRP Refresh Command is necessary Refresh Command is necessary tRC Activate Command tRC µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 46 13.6 CS Function (at 100 MHz, Burst length = 4, CAS latency = 3) Only CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE L A11 A10 RAa ADD RAa DQM CAa CAb L QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 QAa4 DAb1 Write Command for Bank A DAb2 DAb3 DAb4 Precharge Command for Bank A µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE CS CAS WE A11 A10 RAa ADD RAa DQM CAa L QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 1-CLOCK SUSPENDED QAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at end of burst 47 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 48 Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 QAa1 T9 QAa2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE CS RAS WE A11 A10 RAa ADD RAa DQM CAa L DQ Activate Command for Bank A Read Command for Bank A 1-CLOCK SUSPENDED QAa3 QAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at end of burst µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE CS CAS WE A11 A10 RAa ADD RAa DQM CAa L DAa1 DQ Activate Command for Bank A DAa2 DAa3 DAa4 Write Command for Bank A 1-CLOCK SUSPENDED 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED 49 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 50 Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE CS RAS WE A11 A10 RAa ADD RAa DQM CAa L DAa1 DQ Activate Command for Bank A DAa2 1-CLOCK SUSPENDED Write command for Bank A DAa3 2-CLOCK SUSPENDED DAa4 3-CLOCK SUSPENDED µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.9 Power Down Mode and Clock Mask (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE VALID CS CAS WE A11 A10 RAa ADD RAa DQM CAa L QAa1 DQ Activate Command for Bank A QAa2 QAa3 QAa4 Read Command for Bank A Power Down Mode Entry Power Down Mode Exit 51 ACTIVE STANDBY Precharge Command Clock Mask Start Clock Mask End Power Down Mode Entry Power Down Mode Exit PRECHARGE STANDBY µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 52 13.10 CBR Refresh T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 ADD DQM DOM L Q1 DQ Precharge Command if necessary CBR refresh tRP CBR refresh tRC Activate Command tRC Read Command µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.11 Self Refresh (entry and exit) T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T17 T18 T19 T20 T21 CLK CKE CS CAS WE A11 A10 ADD DQM DOM L DQ Precharge Command if necessary Self refresh entry 53 tRP Self refresh Exit Self refresh entry or Next (Activate clock Command) enable tRC Self refresh Exit Activate Command Next clock enable tRC µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 54 13.12 Random Column Read (Page with same bank) (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM RAd CAa CAc CAb RAd CAd L QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 Read Command for Bank A QAa4 QAb1 Read Command for Bank A QAb2 QAc1 QAc2 QAc3 Precharge Command for Bank A QAc4 Activate Command for Bank A QAd1 Read Command for Bank A QAd2 QAd3 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Random Column Read (Page with same bank) (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM RAa CAa CAb CAc RAa CAa Activate Command for Bank A Read Command for Bank A L DQ QAa1 Activate Command for Bank A Read Command for Bank A QAa2 QAa3 QAa4 QAb1 Read Command for Bank A Read Command for Bank A QAb2 QAc1 QAc2 QAc3 QAc4 Precharge Command for Bank A 55 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 56 13.13 Random Column Write (Page with same bank) (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RBa ADD RBa DQM RBd CBa CBb CBc RBd CBd L DBa1 DQ Activate Command for Bank B Write Command for Bank B DBa2 DBa3 DBa4 DBb1 Write Command for Bank B DBb2 DBc1 Write Command for Bank B DBc2 DBc3 DBc4 DBd1 Precharge Command for Bank B Activate Command for Bank B Write Command for Bank B DBd2 DBd3 DBd4 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Random Column Write (Page with same bank) (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RBa ADD RBa DQM RBd CBa CBb CBc RBd CBd L DQ DBa1 Activate Command for Bank B DBa2 Write Command for Bank B DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 Write Command for Bank B Write Command for Bank B DBc3 DBd1 DBc4 Precharge Command for Bank B Activate Command for Bank B DBd2 Write Command for BankB 57 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 58 13.14 Random Row READ (Pingpong banks) (1/2) (Burst length = 8, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RBa ADD RBa DQM RAa CBa RBb RAa CAa RBb CBb L QBa1 DQ Activate Command for Bank B Read Command for Bank B QBa2 QBa3 QBa4 QBa5 QBa6 Activate Command for Bank A QBa7 QBa8 QAa1 Read Command for Bank A QAa3 Activate Command for Bank B Precharge Command for Bank B tRCD QAa2 tRP QAa4 QAa5 QAa6 QAa7 QAa8 Read Command for Bank B µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Random Row READ (Pingpong banks) (2/2) (Burst length = 8, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RBa ADD RBa DQM DOM RAa CBa RBb RAa CAa RBb CBb L QBa1 DQ Activate Command for Bank B Read Command for Bank B 59 tRCD QBa2 QBa3 Activate Command for Bank A QBa4 QBa5 QBa6 Read Command for Bank A QBa7 QBa8 QAa1 Precharge Command for Bank B QAa2 QAa3 Activate Command for Bank B tRP QAa4 QAa5 QAa6 QAa7 Read Precharge Command Command for Bank B for Bank A µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 60 13.15 Random Row Write (Pingpong banks) (1/2) (Burst length = 8, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM RBa CAa RAb RBa CBa RAb CAb L DAa1 DQ Activate Command for Bank A Write Command for Bank A DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 Activate Command for Bank B DAa8 DBa1 DBa2 DBa3 Write Command for Bank B DBa4 Activate Command for Bank A DBa5 DBa6 DBa7 DBa8 DAb1 Write Command for Bank A Precharge Command for Bank A tRCD tDPL DAb2 Precharge Command for Bank B tRP tDPL DAb3 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Random Row Write (Pingpong banks) (2/2) (Burst length = 8, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM RBa CAa RAb RBa CBa RAb CAb L DQ DAa1 Activate Command for Bank A Write Command for Bank A DAa2 DAa3 DAa4 DAa5 DAa6 Activate Command for Bank B DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 Write Command for Bank B DBa5 Activate Command for Bank A DBa6 DBa7 DBa8 DAb1 Write Command for Bank A Precharge Command for Bank A 61 tRCD tDPL DAb2 Precharge Command for Bank B tRP tDPL µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 62 13.16 READ and WRITE (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa CAa CAb CAc Write latency = 0 DQM Word Masking QAa1 DQ QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 QAc4 Hi-Z Activate Command for Bank A Read Command for Bank A Write Command for Bank A Hi-Z at the end of wrap function Read Command for Bank A 0-clock latency 2-clock latency µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS READ and WRITE (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa CAa CAb CAc Write latency = 0 DQM Word Masking DQ QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 Hi-Z Activate Command for Bank A Read Command for Bank A Write Command for Bank A 63 Hi-Z at the end of wrap function Read Command for Bank A 0-clock latency 2-clock latency µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 64 13.17 Interleaved Column READ Cycle (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM RBa CAa RBa CBb CBa CBc CAb CBd L Aa1 DQ Activate Command for Bank A Read Command for Bank A tRRD Aa3 Read Command for Bank B Activate Command for Bank B tRCD Aa2 Aa4 Ba1 Read Command for Bank B Ba2 Bb1 Read Command for Bank B Bb2 Bc1 Read Command for Bank A Bc2 Ab1 Ab2 Read Command for Bank B Precharge Command for Bank A Bd1 Bd2 Bd3 Precharge Command for Bank B Bd4 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Interleaved Column READ Cycle (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM RBa CAa RBa CBa CBb CBc CAb L Aa1 DQ Activate Command for Bank A Read Command for Bank A Activate Command for Bank B tRCD 65 tRRD Aa2 Read Command for Bank B Aa3 Aa4 Read Command for Bank B Ba1 Ba2 Read Command for Bank B Bb1 Bb2 Bc1 Bc2 Ab1 Ab2 Ab3 Read Command for Bank A Precharge Command for Bank B Precharge Command for Bank A Ab4 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 66 13.18 Interleaved Column WRITE Cycle (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM RBa CAa RBa CBb CBa CBc CAb CBd L Aa1 DQ Activate Command for Bank A Aa2 Aa3 Write Command for Bank A Aa4 Ba1 Write Command for Bank B Activate Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Bd2 Write Command for Bank B Precharge Command for Bank A Bd3 Bd4 Precharge Command for Bank B tRCD tRRD tDPL tDPL µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Interleaved Column WRITE Cycle (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM RBa CAa RBa Aa1 Aa2 CBb CBa CAb CBc CBd L DQ Activate Command for Bank A Write Command for Bank A Activate Command for Bank B Aa3 Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A tRCD 67 tRRD Bd2 tDPL Precharge Command for Bank B tDPL µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 68 13.19 Auto Precharge after Read Burst (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa RBb CBa CAb RBb RAc CBb RAc CAc L Hi-Z Activate Command for Bank A Activate Command for Bank B Bank A Read Command without Auto Precharge Bank B Read Command with Auto Precharge Bank A Read Command with Auto Precharge Auto Precharge Start for Bank B Activate Command for Bank B Auto Precharge Start for Bank A Activate Command for Bank A Bank B Read Command with Auto Precharge Bank A Auto Precharge Read Command Start for Bank B with Auto Precharge µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Auto Precharge after Read Burst (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa RBb CBa CAb RBb CBb L Hi-Z Activate Command for Bank A Activate Command for Bank B 69 Bank A Read Command without Auto Precharge Bank B Read Command with Auto Precharge Bank A Read Command with Auto Precharge Auto Precharge Start for Bank B Auto Precharge Start for Bank A Activate Command for Bank B Bank B Read Command with Auto Precharge µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 70 13.20 Auto Precharge after Write Burst (1/2) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa RBb CBa CAb RAc RBb CBb RAc CAc L Hi-Z Activate Command for Bank A Activate Command for Bank B Bank A Write Command without Auto Precharge Activate Command for Bank B Bank B Write Command with Auto Precharge Bank A Write Command with Auto Precharge Activate Command for Bank A Bank B Write Command with Auto Precharge Auto Precharge Start for Bank B Bank A Write Command with Auto Precharge Auto Precharge Start for Bank A Auto Precharge Start for Bank B µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Auto Precharge after Write Burst (2/2) (Burst length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa RBb CBa CAb RBb CBb L Hi-Z Activate Command for Bank A Activate Command for Bank B Bank A Write Command without Auto Precharge Bank B Write Command with Auto Precharge Bank A Write Command with Auto Precharge 71 Auto Precharge Start for Bank B Activate Command for Bank B Auto Precharge Start for Bank A Bank B Write Command with Auto Precharge µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 72 13.21 Full Page READ Cycle (1/2) (CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBb RBa CBa RBb L Hi-Z Activate Command for Bank A Aa Read Command for Bank A Activate Command for Bank B Aa+1 Aa+2 Aa­2 Aa­1 Aa Aa+1 Ba Ba+1 Ba+2 Ba+3 Read Command for Bank B Ba+4 Ba+5 Ba+6 Precharge Command for Bank B Burst stop Command Activate Command for Bank B µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Full Page READ Cycle (2/2) (CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBb RBa CBa RBb L Hi-Z Activate Command for Bank A Aa Read Command for Bank A Activate Command for Bank B Aa+1 Aa­3 Aa­2 Aa­1 Aa Aa+1 Ba Ba+1 Ba+2 Ba+3 Ba+4 Ba+5 Read Command for Bank B Burst stop Command Precharge Command for Bank B Activate Command for Bank B 73 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 74 13.22 Full Page WRITE Cycle (1/2) (CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBb RBa CBa RBb L Hi-Z Activate Command for Bank A Aa Write Command for Bank A Aa+1 Aa+2 Activate Command for Bank B Aa­2 Aa­1 Aa Aa+1 Ba Ba+1 Ba+2 Ba+3 Ba+4 Ba+5 Write Command for Bank B Precharge Command for Bank B Burst stop Command Activate Command for Bank B µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS Full Page WRITE Cycle (2/2) (CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBb RBa CBa RBb L Hi-Z Activate Command for Bank A Aa Write Command for Bank A Aa+1 Aa+2 Activate Command for Bank B Aa+3 Aa­1 Aa Aa+1 Ba Ba+1 Ba+2 Ba+3 Ba+4 Write Command for Bank B Precharge Command for Bank B Burst stop Command Activate Command for Bank B 75 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 76 13.23 Byte Write Operation (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 ADD LDQM UDQM DQ lower DQ upper Activate Command Read Command U-byte not Read L-byte not Read L-byte not Write U-byte not Write L-byte not Write L-byte not Read L-byte not Read µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.24 Burst Read and Single Write (Option) (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 ADD LDQM UDQM DQ lower DQ upper 77 Activate Command Read Command Single Write Command Single Write Command Read Command Single Write Command µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 78 13.25 Full Page Random Column Read (Burst length = Full Page, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RBa RAa RBa CAa CBa CAb CBb CAc CBc tRCD DQM L tRRD tRCD QAa1 DQ Activate Command for Bank A Activate Command for Bank B Read Command for Bank A QBa1 Read Command for Bank A Read Command for Bank B QAb1 Read Command for Bank B QAb2 QBb1 QBb2 Read Command for Bank A QAc1 QAc2 Read Command for Bank B QAc3 QBc1 QBc2 QBc3 Precharge Command for Bank B (PRE Termination) Hi-Z µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS 13.26 Full Page Random Column Write (Burst length = Full Page, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa RBa RBa CAa CBa CAb DBa1 DAb1 CBb CAc CBc tRCD DQM L tRRD tRCD DAa1 DQ Activate Command for Bank A DAb2 DBb1 DBb2 DAc1 DAc2 DAc3 DBc1 Activate Command for Bank B Write Command for Bank A Write Command for Bank A 79 Write Command for Bank B Write Command for Bank B Write Command for Bank A Write Command for Bank B DBc2 DBc3 DBc4 Precharge Command for Bank B (PRE Termination) µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS 80 13.27 PRE(Precharge)Termination of Burst (1/2) (Burst length = 8, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS RAS WE A11 A10 RAa ADD RAa DQM RAb CAa RAb L CAb Write Masking DQ DAa1 Activate Command for Bank A DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 QAb3 QAb4 QAb5 Write Command for Bank A Read Command for Bank A PRE Command Termination tRCD Precharge Command for Bank A tDPL tRAS Activate Command for Bank A tRP PRE Command Termination tRAS Precharge Command for Bank A Hi-Z µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P CAS PRE(Precharge)Termination of Burst (2/2) (Burst length = 8, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H CS CAS WE A11 A10 RAa ADD RAa DQM RAb CAa RAb L CAb Write Masking DQ DAa1 Activate Command for Bank A DAa2 DAa3 DAa4 Hi-Z DAa5 Write Command for Bank A PRE Command Termination 81 tRCD Read Command for Bank A Bank A Precharge Command tDPL tRAS QAb1 QAb2 QAb3 QAb4 tRP Activate Command for Bank A PRE Command Termination tRAS Bank A Precharge Command µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P RAS µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 14. Package Drawings [µPD4516421AG5-9NF PD4516421AG5-9NF, 4516821AG5-9NF 4516821AG5-9NF] 44PIN 44PIN PLASTIC TSOP(II) (400 mil) 44 23 detail of lead end S T R 1 22 A3 L Q U H G I S N C S B D M J K M NOTE 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 3. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm(0.006inch) per side. ITEM MILLIMETERS INCHES A 18.32±0.04 0.721±0.002 B 0.905 MAX. 0.036 MAX. C 0.8 (T.P.) 0.031 (T.P.) D 0.32 +0.08 ­0.07 0.013±0.003 G 1.0±0.05 0.039 +0.003 ­0.002 H 11.76±0.2 0.463±0.008 I 10.11±0.04 0.398±0.002 J 0.825±0.2 0.032 +0.009 ­0.008 K 0.145 +0.025 ­0.015 0.006±0.001 0.020 L 0.5 M 0.13 0.005 N 0.10 0.004 Q 0.1±0.05 0.004±0.002 R 3° +5° ­3° 3° +5° ­3° S 1.2MAX. 0.048MAX 048MAX. T 0.25(T.P.) 0.010(T.P.) U 0.60±0.15 0.024 +0.006 ­0.007 S44G5-80-9NF S44G5-80-9NF 82 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P [µPD4516161AG5-9NF PD4516161AG5-9NF] 50PIN 50PIN PLASTIC TSOP(II) (400 mil) 50 26 detail of lead end S T R 1 25 A3 L Q U H I S G N C S J B K D M M NOTE 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 3. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm(0.006inch) per side. ITEM MILLIMETERS INCHES A 20.86±0.04 0.821±0.002 B 1.0 MAX. 0.040 MAX. C 0.8 (T.P.) 0.031 (T.P.) D 0.32 +0.08 ­0.07 0.013±0.003 G 1.0±0.05 0.039 +0.003 ­0.002 H 11.76±0.2 0.463±0.008 I 10.11±0.04 0.398±0.002 J 0.825±0.2 0.032 +0.009 ­0.008 K 0.145 +0.025 ­0.015 0.006±0.001 0.020 L 0.5 M 0.13 0.005 N 0.10 0.004 Q 0.1±0.05 0.004±0.002 R 3° +5° ­3° 3° +5° ­3° S 1.2MAX. 0.048MAX 048MAX. T 0.25(T.P.) 0.010(T.P.) U 0.60±0.15 0.024 +0.006 ­0.007 S50G5-80-9NF S50G5-80-9NF 83 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P 15. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4516421A PD4516421A, 4516821A, 4516161A. Types of Surface Mount Device 4516421AG5-9NF 4516421AG5-9NF, 4516821AG5-9NF 4516821AG5-9NF: 44-pin plastic TSOP (II) (400 mil) µPD4516161AG5-9NF PD4516161AG5-9NF: 50-pin plastic TSOP (II) (400 mil) 84 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 85 µPD4516421A PD4516421A, 4516821A, 4516161A for Rev. P [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5