PD4516161D PD4516161DG5-A70-9NF PD4516161DG5-A75-9NF PD4516161DG5-A10-9NF - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL EO Description The µPD4516161D is

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD4516161D PD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL EO Description The µPD4516161D PD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words × 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). This product is packaged in 50-pin TSOP (II). L Features · Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge · Pulsed interface · Possible to assert random column address in every cycle u od Pr · Dual internal banks controlled by A11 · Byte control by LDQM and UDQM · Programmable Wrap sequence: Sequential / Interleave · Programmable burst length: 1, 2, 4, 8 and full page · /CAS latency: 3 · CBR (Auto) refresh and self refresh · ×16 organization · Single 3.3 V ± 0.3 V power supply · LVTTL compatible · 2,048 refresh cycles / 32 ms · Burst termination by Burst stop command and Precharge command Ordering Information Part number µPD4516161DG5-A70-9NF PD4516161DG5-A70-9NF µPD4516161DG5-A75-9NF PD4516161DG5-A75-9NF Organization (word × bit × bank) Clock frequency MHz (MAX.) Package 512K × 16 × 2 143 50-pin PLASTIC TSOP (II) 133 (10.16mm(400) 125 µPD4516161DG5-A10-9NF PD4516161DG5-A10-9NF 100 ct µPD4516161DG5-A80-9NF PD4516161DG5-A80-9NF The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0143N10 E0143N10 (Ver.1.0) (Previous No. M14888EJ2V0DS00 M14888EJ2V0DS00) Date Published May 2001 CP (K) Printed in Japan This product became EOL in September, 2002. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. µPD4516161D PD4516161D Part Number µPD4516161DG5 PD4516161DG5 - A80 NEC Memory Synchronous DRAM EO Memory density 16 : 16M bits Minimum cycle time Organization 70 75 80 10 16 : x16 Number of banks and Interface : 7 ns (143 MHz) : 7.5 ns (133 MHz) : 8 ns (125 MHz) : 10 ns (100 MHz) L Low voltage A : 3.3 V ± 0.3 V 1 : 2 banks, LVTTL Version Package ct u od Pr G5 : TSOP (II) 2 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D Pin Configuration /xxx indicates active low signal. [ µPD4516161DG5 PD4516161DG5 ] 50-pin PLASTIC TSOP (II) (10.16mm (400) 512K words × 16 bits × 2 banks L EO VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ LDQM /WE /CAS /RAS /CS A11 A10 A0 A1 A2 A3 VCC Note Vss DQ15 DQ14 VssQ DQ13 DQ12 VccQ DQ11 DQ10 VssQ DQ9 DQ8 VccQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss u od Pr A0 to A11 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 : Address inputs DQ0 to DQ15 : Data inputs / outputs CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe : Write enable LDQM : Lower DQ mask enable UDQM : Upper DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A7 : Column address inputs NC : No connection A11 ct /WE Note A0 to A10 : Row address inputs Data Sheet E0143N10 E0143N10 : Bank select 3 µPD4516161D PD4516161D Block Diagram Clock Generator Bank B Address L /WE Column Address Buffer & Burst Counter DQM Column Decoder & Latch Circuit Data Control Circuit Input & Output Buffer /CAS Bank A Sense Amplifier Control Logic /RAS Command Decoder EO /CS Mode Register Row Address Buffer & Refresh Counter Latch Circuit CKE Row Decoder CLK DQ ct u od Pr 4 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D CONTENTS 1. Input / Output Pin Function . 7 2. Commands . 8 3. Simplified State Diagram . 11 EO 4. Truth Table . 12 4.1 Command Truth Table . 12 4.2 DQM Truth Table . 12 4.3 CKE Truth Table . 12 4.4 Operative Command Table . 13 4.5 Command Truth Table for CKE . 16 4.6 Command Truth Table for Two Banks Operation . 17 L 5. Initialization . 18 6. Programming the Mode Register . 19 7. Mode Register . 20 u od Pr 7.1 Burst Length and Sequence . 21 8. Address Bits of Bank-Select and Precharge . 22 9. Precharge . 23 10. Read / Write Command Interval . 24 10.1 Read to Read Command Interval . 24 10.2 Write to Write Command Interval . 24 10.3 Write to Read Command Interval . 25 10.4 Read to Write Command Interval . 26 11. Burst Termination . 27 11.1 Burst Stop Command . 27 11.2 Precharge Termination . 28 Precharge Termination in READ Cycle . 28 11.2.2 Precharge Termination in WRITE Cycle . 28 ct 11.2.1 Data Sheet E0143N10 E0143N10 5 µPD4516161D PD4516161D 12. Electrical Specifications . 29 12.1 Mode Register Set . 34 12.2 Power On Sequence and CBR (Auto) Refresh . 35 12.3 /CS Function .36 12.4 Clock Suspension during Burst Read (Using CKE Function) . 37 12.5 Clock Suspension during Burst Write (Using CKE Function) . 38 12.6 Power Down Mode and Clock Mask . 39 12.7 CBR (Auto) Refresh . 40 EO 12.8 Self Refresh (Entry and Exit) . 41 12.9 Random Column Read (Page with Same Bank) . 42 12.10 Random Column Write (Page with Same Bank) . 43 12.11 Random Row Read (Ping-Pong Banks) . 44 12.12 Random Row Write (Ping-Pong Banks) . 45 12.13 Read and Write . 46 12.14 Interleaved Column Read Cycle . 47 12.15 Interleaved Column Write Cycle. 48 12.16 Full Page Read Cycle . 49 L 12.17 Full Page Write Cycle . 50 12.18 Byte Write Operation . 51 12.19 Burst Read and Single Write (Option) . 52 12.20 Full Page Random Column Read . 53 12.21 Full Page Random Column Write. 54 u od Pr 12.22 PRE (Precharge) Termination of Burst . 55 13. Package Drawing . 56 14. Recommended Soldering Condition . 57 15. Revision History . 58 ct 6 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 1. Input / Output Pin Function Pin name CLK Input / Output Input Function CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE Input CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the µPD4516161D PD4516161D suspends operation. When the µPD4516161D PD4516161D is not in burst mode and CKE is negated, the device enters EO /CS /RAS, /CAS, /WE A0 - A11 power down mode. During power down mode, CKE must remain low. Input /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. Input /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. Input Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the activate command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A7 at the CLK rising edge in the read or write command cycle. L A11 is the bank select signal (BS). In command cycle, A11 low selects bank A and A11 high selects bank B. A10 defines the precharge mode. When A10 is high in the precharge command cycle, both banks are precharged; when A10 is low, only the bank selected by A11 is precharged. u od Pr When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. UDQM, LDQM Input UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 - DQ15 Input / Output DQ pins have the same function as I/O pins on a conventional DRAM. VCC, VSS, VCCQ, VSSQ (Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. ct Data Sheet E0143N10 E0143N10 7 µPD4516161D PD4516161D 2. Commands Mode register set command Fig.1 Mode register set command CLK (/CS, /RAS, /CAS, /WE = Low) CKE The µPD4516161D PD4516161D has a mode register that defines how the device /CS operates. In this command, A0 through A11 are the data input pins. H /RAS EO After power on, the mode register set command must be executed to initialize the device. /CAS /WE The mode register can be set only when both banks are in idle state. A11 During 2 CLK (tRSC) following this command, the µPD4516161D PD4516161D A10 cannot accept any other commands. Add Activate command Fig.2 Row address strobe and bank activate command L (/CS, /RAS = Low, /CAS, /WE = High) CLK The µPD4516161D PD4516161D has two banks, each with 2,048 rows. This command activates the bank selected by A11(BS) and a row address selected by A0 through A10. CKE H /CS /RAS u od Pr This command corresponds to a conventional DRAM's /RAS falling. /CAS /WE A11 (Bank select) A10 Add Precharge command Row Row Fig.3 Precharge command CLK (/CS, /RAS, /WE = Low, /CAS = High) CKE This command begins precharge operation of the bank selected by /CS A11(BS). When A10 is High, both banks are precharged, regardless /RAS of A11. When A10 is Low, only the bank selected by A11 is H /CAS precharged. A11 low selects bank A and A11 high selects bank B. After this command, the µPD4516161D PD4516161D can't accept the activate command to the precharging bank during tRP (precharge to activate A11 (Bank select) ct A10 (Precharge select) command period). Add This command corresponds to a conventional DRAM's /RAS rising. 8 /WE Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D Write command Fig.4 Column address and write command CLK (/CS, /CAS, /WE = Low, /RAS = High) CKE If the mode register is in the burst write mode, this command sets the H /CS burst start address given by the column address to begin the burst /RAS write operation. The first write data in burst mode can be input with /CAS EO this command with subsequent data on following clocks. /WE A11 (Bank select) A10 Add Read command Col. Fig.5 Column address and read command CLK (/CS, /CAS = Low, /RAS, /WE = High) L CKE Read data is available after /CAS latency requirements have been H /CS met. This command sets the burst start address given by the column /RAS address. /CAS /WE u od Pr A11 (Bank select) A10 Add CBR (auto) refresh command Fig.6 CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) CLK CKE This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, both banks must be precharged. Col. H /CS /RAS /CAS /WE After this cycle, both banks will be in the idle (precharged) state and A11 (Bank select) ready for a row activate command. A10 During tRC period (from refresh command to refresh or activate command), the µPD4516161D PD4516161D cannot accept any other command. Add ct Data Sheet E0143N10 E0143N10 9 µPD4516161D PD4516161D Self refresh entry command Fig.7 Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) CLK CKE After the command execution, self refresh operation continues while /CS CKE remains low. When CKE goes high, the µPD4516161D PD4516161D exits the /RAS self refresh mode. /CAS EO During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, both banks must be precharged. /WE A11 (Bank select) A10 Add Burst stop command Fig.8 Burst stop command in Full Page Mode (/CS, /WE = Low, /RAS, /CAS = High) L CLK This command terminates the current burst operation. CKE H /CS /RAS /CAS u od Pr /WE A11 (Bank select) A10 Add No operation Fig.9 No operation CLK (/CS = Low, /RAS, /CAS, /WE = High) CKE This command is not an execution command. No operations begin or terminate by this command. H /CS /RAS /CAS /WE A11 (Bank select) A10 Add ct 10 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 3. Simplified State Diagram Self Refresh LF SE xit Fe L SE MRS Mode Register Set REF IDLE CBR (Auto) Refresh EO CK E ACT CK E Power Down CKE L ROW ACTIVE BS T BS T Re ad e rit Write Active Power Down CKE Read W PRE CKE u od Pr Read CKE READ Write n) atio min ter rge cha Pre E( PR POWER ON CKE WRITE Precharge CKE READ SUSPEND PR E( Pre cha rge ter min atio n) WRITE SUSPEND Precharge ct Automatic sequence Manual input Data Sheet E0143N10 E0143N10 11 µPD4516161D PD4516161D 4. Truth Table 4.1 Command Truth Table Function Symbol CKE /CS n­1 /RAS /CAS /WE A11 A10 A9 - A0 n DESL H × H × × × × × × No operation NOP H × L H H H × × × Burst stop BST H × L H H L × × × Read READ H × L H L H V L V Write WRIT H × L H L L V L V Bank activate ACT H × L L H H V V V Precharge select bank PRE H × L L H L V L × Precharge both banks PALL H × L L H L × H × Mode register set MRS H × L L L L L L V EO Device deselect Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input L 4.2 DQM Truth Table Function Symbol CKE DQM n­1 n U L Data write / output enable ENB H × L Data mask / output disable MASK H × H u od Pr Upper byte write enable / output enable ENBU H × L × Lower byte write enable / output enable ENBL H × × L Upper byte write inhibit / output disable MASKU H × H × Lower byte write inhibit / output disable MASKL H × × H Remark H = High level, L = Low level, × = High or Low level (Don't care) 4.3 CKE Truth Table Current state Function Symbol CKE /CS n­1 /RAS /CAS /WE Address n Clock suspend mode entry H L × × × × × Any Clock suspend mode L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle CBR (auto) refresh command REF H H L L L H × Idle Self refresh entry SELF H L L L L H × Self refresh Self refresh exit L H L H H H × L H H × Idle Power down entry H L × × Power down Power down exit L H × × Remark H = High level, L = Low level, × = High or Low level (Don't care) 12 Data Sheet E0143N10 E0143N10 ct Activating × × × × × × × × × µPD4516161D PD4516161D 4.4 Operative Command Table Current state Note1 (1/2) /CS /RAS /CAS /WE Address Command Action Notes × × × × DESL Nop or power down 3 H H × × NOP or BST Nop or power down 3 L H L H BA, CA, A10 READ ILLEGAL 4 L H L L BA, CA, A10 WRIT ILLEGAL 4 L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF/SELF CBR (auto) refresh or self refresh EO H L Idle 5 L L L Op-Code MRS Mode register accessing H × × × × DESL Nop L H H × × NOP or BST Nop L H L H BA, CA, A10 READ Begin read : Determine AP L H L L BA, CA, A10 WRIT Begin write : Determine AP 6 L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Precharge 7 L L L H × REF/SELF ILLEGAL L L Row active 6 L L Op-Code MRS ILLEGAL × × × × DESL Continue burst to end Row active L H H H × NOP Continue burst to end Row active L H H L × BST Burst stop Row active L H L H BA, CA, A10 READ Terminate burst, new read : Determine AP 8 L H L L BA, CA, A10 WRIT Terminate burst, start write : Determine AP 8, 9 L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL Terminate burst, precharging L L L H × REF/SELF ILLEGAL L Write L H L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end Write recovering L H H H × NOP Continue burst to end Write recovering L H L H L H L L L L L L L L u od Pr L Read 4 H L × BST Burst stop Row active L H BA, CA, A10 READ Terminate burst, start read : Determine AP 8, 9 L L BA, CA, A10 WRIT Terminate burst, new write : Determine AP 8 H H BA, RA ACT ILLEGAL 4 H L BA, A10 PRE/PALL Terminate burst, precharging 10 L H × REF/SELF ILLEGAL L L Op-Code MRS ILLEGAL ct Data Sheet E0143N10 E0143N10 13 µPD4516161D PD4516161D (2/2) Current state /CS /RAS /CAS /WE Address Command Action H × × × × DESL Nop Enter idle after tRP L H H H × NOP Nop Enter idle after tRP L Precharging H H L × BST Notes Nop Enter idle after tRP Row activating H L H BA, CA, A10 READ ILLEGAL 4 H L L BA, CA, A10 WRIT ILLEGAL 4 L EO L L L H H BA, RA ACT ILLEGAL 4 L L H L BA, A10 PRE/PALL Nop Enter idle after tRP L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop Enter row active after tRCD L H H H × NOP Nop Enter row active after tRCD H H L × BST Nop Enter row active after tRCD H L H BA, CA, A10 READ ILLEGAL 4 L H L L BA, CA, A10 WRIT ILLEGAL 4 L L H H BA, RA ACT ILLEGAL 4, 11 4 L L L L H L BA, A10 PRE/PALL ILLEGAL L L H × REF/SELF ILLEGAL L Write recovering L L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop Enter row active after tDPL H H H × NOP Nop Enter row active after tDPL H H L × BST Nop Enter row active after tDPL H L H BA, CA, A10 READ Start read H L L BA, CA, A10 WRIT New write L H H BA, RA ACT ILLEGAL 4 L H L BA, A10 PRE/PALL ILLEGAL 4 L L H × REF/SELF ILLEGAL L L L Op-Code MRS ILLEGAL L u od Pr L H L × × READ/WRIT ILLEGAL L L × × × ACT/PRE/PALL/ ILLEGAL L L L L L L L Refreshing H L L L L Mode register H accessing L L × × × × DESL Nop Enter idle after tRC H H × × NOP/BST Nop Enter idle after tRC H L × × READ/WRIT ILLEGAL L H × × ACT/PRE/PALL ILLEGAL L L × × REF/SELF/MRS ILLEGAL × × × × DESL Nop Enter idle after tRSC H H H × NOP Nop Enter idle after tRSC H H L × BST ILLEGAL Data Sheet E0143N10 E0143N10 ct REF/SELF/MRS 14 9 µPD4516161D PD4516161D Notes 1. H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input 2. All entries assume that CKE was active (High level) during the preceding clock cycle. 3. If both banks are idle, and CKE is inactive (Low level), µPD4516161D PD4516161D will enter Power down mode. All input buffers except CKE will be disabled. 4. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 5. If both banks are idle, and CKE is inactive (Low level), µPD4516161D PD4516161D will enter Self refresh mode. All input buffers except CKE will be disabled. 6. Illegal if tRCD is not satisfied. EO 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied. L ct u od Pr Data Sheet E0143N10 E0143N10 15 µPD4516161D PD4516161D 4.5 Command Truth Table for CKE Current State CKE n­1 Note1 /CS /RAS /CAS /WE Address Action Notes n H × × × × × × INVALID, CLK (n ­ 1) would exit self refresh L H H × × × × Self refresh recovery L Self refresh H L H H × × Self refresh recovery EO L Self refresh recovery H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Maintain self refresh H H H × × × × Idle after tRC H H L H H × × Idle after tRC H H L H L × × ILLEGAL H H L L × × × ILLEGAL H L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL × ILLEGAL L L L × × × × × × × H × × × × × EXIT power down Idle × Maintain power down mode L H H L Power down INVALID, CLK (n ­ 1) would exit power down L × × × × H H H × × × Refer to operations in Operative Command Table H H L H × × Refer to operations in Operative Command Table u od Pr L Both banks idle H H L L H × H H L L L H × CBR (auto) refresh H H L L L L Op-Code Refer to operations in Operative Command Table H L H × × × Refer to operations in Operative Command Table H L L H × × Refer to operations in Operative Command Table H L L L H × Refer to operations in Operative Command Table Refer to operations in Operative Command Table L L L H × Self refresh L L L L Op-Code Refer to operations in Operative Command Table × × × × × Power down × × × × × × × × × × × × × Refer to operations in Operative Command Table × × × × × Begin clock suspend next cycle H × × × × × Exit clock suspend next cycle L × × × × × Maintain clock suspend H L H L L × Row active H × L × Any state other than H H listed above H L L L 2 2 Refer to operations in Operative Command Table Power down 3 3 Notes 1. H = High level, L = Low level, × = High or Low level (Don't care) ct 2. Self refresh can be entered only from the both banks idle state. Power down can be entered from the both banks idle state or row active state. 3. Must be legal command as defined in Operative Command Table. 16 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 4.6 Command Truth Table for Two Banks Operation /CS /RAS /CAS /WE BA A10 Note1, 2 A9 - A0 Action "FROM" State Note3 "TO" State Note4 H × × × × × × NOP Any Any L H H H × × × NOP Any Any L H H L × × × BST (R/W/A)0(I/A)1 A0(I/A)1 I0(I/A)1 I0(I/A)1 (R/W/A)1(I/A)0 A1(I/A)0 I1(I/A)0 I1(I/A)0 (R/W/A)1(I/A)0 R1(I/A)0 H L EO L L H L H H L CA Read H CA A1(R/W)0 R1A0 L CA (R/W/A)0(I/A)1 R0(I/A)1 L L CA A0(R/W)1 R0A1 H L CA (R/W/A)1(I/A)0 W1(I/A)0 H L CA A1(R/W)0 W1A0 L L L L L CA (R/W/A)0(I/A)1 W0(I/A)1 CA Write RA H H × (R/W/A/I)1(I/A)0 I1I0 L × (R/W/A/I)1(I/A)0 I1(I/A)0 H L × (I/A)1(R/W/A/I)0 I1(R/W/A/I)0 L RA × H L H H L × L L H L L L H L A0(R/W)1 × Precharge W0A1 I1Any0 A1Any0 I0Any1 Activate Row A0Any1 (R/W/A/I)0(I/A)1 I0I1 u od Pr L L L L H L L L L L × (R/W/A/I)0(I/A)1 I0(I/A)1 L L × (I/A)0(R/W/A/I)1 I0(R/W/A/I)1 × × × Refresh I0I1 I0I1 Mode Register Access I0I1 I0I1 Op-Code Notes 1. Logic level abbreviations H: High level, L: low level, ×: High or Low level (Don't care) Pin name abbreviation BA: Bank address (A11) 2. State abbreviations I = Idle A = Row active R = Read with No precharge (No precharge is posted) W = Write with No precharge (No precharge is posted) X0Y1 = Y1X0 = Bank A is in state "X", Bank B is in state "Y" (X/Y)0Z1 = Z1(X/Y)0 = Bank A is in state "X" or "Y". Bank B is in state "Z" ct Any = Any State 3. If the µPD4516161D PD4516161D is in a state other than above listed the "From State" column, the command is illegal. 4. The state listed under "To" might not be entered on the next clock cycle. Timing restrictions apply. Data Sheet E0143N10 E0143N10 17 µPD4516161D PD4516161D 5. Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) (2) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling. After the pause, both banks must be precharged using the Precharge command (The Precharge both banks command is convenient). EO (3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well. (4) Tow or more CBR(Auto) refresh must be performed. Remarks 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the Precharge command is issued to ensure data bus Hi-Z. L ct u od Pr 18 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A11 through A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power. The mode register has four fields; Options : A11 through A7 EO /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters to be set. It tells the device how many clocks must elapse before L the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. The table on page 33 shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length u od Pr Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. The table on the page 21 shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Only the sequential burst supports the full page length. ct Data Sheet E0143N10 E0143N10 19 µPD4516161D PD4516161D 7. Mode Register 11 10 9 8 7 0 0 0 0 1 11 10 9 8 7 x x 1 0 0 11 10 9 8 7 x 0 0 0 0 6 5 4 3 2 1 0 Reserved Test Set 6 5 4 LTMODE 6 5 LTMODE 3 2 WT 4 3 0 BL 2 WT 1 1 Burst Read and Single Write 0 BL Mode Register Set EO x = Don't care L Burst length Bits2-0 000 001 010 011 100 101 110 111 Wrap type 0 1 WT = 0 1 2 4 8 R R R Full page WT = 1 1 2 4 8 R R R R Sequential Interleave /CAS latency R R R 3 R R R R u od Pr Bits6-4 000 001 010 011 100 101 110 111 Latency mode Remark R : Reserved Mode Register Set Timing CLK CKE /CS /RAS /WE A0 - A11 Mode Register Set 20 Data Sheet E0143N10 E0143N10 ct /CAS µPD4516161D PD4516161D 7.1 Burst Length and Sequence [ Burst of Two ] Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting address (column address A1 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 Starting address (column address A2 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 EO Starting address (column address A0, binary) [ Burst of Four ] L [ Burst of Eight ] 010 011 100 101 110 111 u od Pr 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Full page burst is an extension of the above tables of sequential addressing, with the length being 256. ct Data Sheet E0143N10 E0143N10 21 µPD4516161D PD4516161D 8. Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A11 (Activate command) 0 1 EO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A10 A11 0 0 1 0 x 1 (Precharge command) A0 A1 A2 A3 A4 A5 A10 0 A6 A7 A8 A9 A10 A11 A11 0 1 Precharge for Bank A CLK CKE /CS /RAS /CAS /WE A10 22 CKE Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B Precharge for Both banks CLK H CKE /CS /CS /RAS /RAS /CAS /CAS /WE /WE A10 A10 A11 A11 H Data Sheet E0143N10 E0143N10 ct A11 Precharge for Bank B CLK H Result disables Auto-Precharge (End of Burst) u od Pr (/CAS strobes) Result Precharge Bank A Precharge Bank B Precharge Both Banks x : Don't care L Col. Result Select Bank A "Activate" command Select Bank B "Activate" command µPD4516161D PD4516161D 9. Precharge The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed. The synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. EO /CAS latency = 3: Two clocks earlier than the last read data. Burst length=4 T0 T1 T2 T3 T4 T5 T6 T7 Q3 Q4 T8 CLK /CAS latency = 3 Command Read PRE L DQ Q1 Q2 Hi-Z (tRAS must be satisfied) u od Pr In order to write all data to the memory cell correctly, the asynchronous parameter "tDPL" must be satisfied. The tDPL (MIN.) specification defines the earliest time that a precharge command can be issued. The minimum number of clocks is calculated by dividing tDPL (MIN.) by the clock cycle time. In summary, the precharge command can be issued relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. /CAS latency 3 Read Write ­2 +tDPL (MIN.) ct Data Sheet E0143N10 E0143N10 23 µPD4516161D PD4516161D 10. Read / Write Command Interval 10.1 Read to Read Command Interval When a new Read command is issued during a read cycle, it will be effective after the /CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each read command can be issued in every clock without any restriction. EO T0 Burst length = 4, /CAS latency = 3 T1 T2 T3 T4 T5 T6 T7 T8 QA1 QB1 QB2 QB3 T9 QB4 CLK Command Read B L DQ Read A Hi-Z 1cycle u od Pr 10.2 Write to Write Command Interval When a new Write command is issued during a write cycle, the previous burst will be terminated and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1. Each write command can be issued in every clock without any restriction. Burst length = 4, /CAS latency = 3 T0 T1 T2 CLK Command Write A T3 T4 T5 DB2 DB3 DB4 T6 DB1 Data Sheet E0143N10 E0143N10 ct DA1 1cycle 24 T8 Write B Hi-Z DQ T7 µPD4516161D PD4516161D 10.3 Write to Read Command Interval The write command to Read command interval is a minimum of 1 cycle. Only the write data preceding Read command will be written. The data bus must be in high-impedance at least one cycle prior to the first DOUT. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 QB1 QB2 QB3 QB4 CLK EO /CAS latency = 3 Command DQ Write A Read B Hi-Z DA1 L 1cycle ct u od Pr Data Sheet E0143N10 E0143N10 25 µPD4516161D PD4516161D 10.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The data bus be Hi-Z using DQM before WRITE. Burst length = 4 T0 T1 T2 T3 Read T4 T5 D2 D3 T6 T7 T8 Write D4 CLK EO Command DQM Hi-Z DQ D1 1cycle L READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command. T0 T1 T2 Burst length = 8 T3 T4 T5 T6 T7 T8 T9 CLK Command DQM DQ u od Pr /CAS latency = 3 Read Write Q1 D1 Q2 D2 D3 Hi-Z is necessary ct 26 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 11. Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. 11.1 Burst Stop Command EO During a read burst, when the burst stop command is issued, the burst read outputs are terminated and the data bus goes to high-impedance after the /CAS latency from the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read BST L /CAS latency = 3 Hi-Z DQ Q1 Q2 Q3 Remark BST : Burst stop command u od Pr During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command. Burst length = X T0 CLK Command /CAS latency = 3 DQ T1 T2 T3 T4 Write T5 T6 T7 BST Hi-Z D1 D2 D3 D4 Remark BST : Burst stop command ct Data Sheet E0143N10 E0143N10 27 µPD4516161D PD4516161D 11.2 Precharge Termination 11.2.1 Precharge Termination in READ Cycle During a read cycle, the burst read operation can be terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. EO When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Read ACT PRE L Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) u od Pr 11.2.2 Precharge Termination in WRITE Cycle During a write cycle, the burst write operation can be terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP(MIN.) from the precharge command. When /CAS latency is 3, the write data written 2 clock prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock and one clock before the precharge command. To prevent this from happening, DQM must be high at the same clock and one clock before the precharge command. This will mask the invalid data. Burst length = X, /CAS latency = 3 T0 CLK Command T1 T2 T3 T4 Write T5 T6 T7 ACT PRE Hi-Z D1 D2 D3 D4 D5 tRP ct DQM DQ T8 (tRAS must be satisfied) 28 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 12. Electrical Specifications · All voltages are referenced to VSS (GND). · After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Rating Unit VCC, VCCQ -0.5 to +4.6 V Voltage on any pin relative to GND VT -0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 1 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg -55 to + 125 °C Voltage on power supply pin relative to GND EO Caution Condition Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits L described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter High level input voltage Low level input voltage Operating ambient temperature Condition MIN. TYP. MAX. u od Pr Supply voltage Symbol VCC, VCCQ 3.0 VIH 3.3 2.0 VIL V Note1 VCC+0.3 V +0.8 V 70 °C -0.3 TA 3.6 Unit 0 Note2 Notes 1. VIH (MAX.) = VCC + 2.0 V (Pulse width 3 ns) 2. VIL (MIN.) = ­2.0 V (Pulse width 3 ns) Pin Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Symbol Condition MIN. TYP. MAX. Unit pF A0 - A11 2.5 4 CI2 Data input / output capacitance CI1 CLK, CKE, /CS, /RAS, /CAS, /WE, UDQM, LDQM 2.5 4 CI/O DQ0 - DQ15 4 6 pF ct Data Sheet E0143N10 E0143N10 29 µPD4516161D PD4516161D DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition /CAS Grade Max. Unit Notes -A70 140 mA 1 tRC tRC (MIN.), I/O = 0 mA, -A75 130 One bank active -A80 120 -A10 120 latency Operating current EO Precharge standby current in power down mode Precharge standby current ICC1 ICC2P ICC2PS ICC2N in non power down mode Active standby current Burst length = 1 CL = 3 CKE VIL (MAX.), tCK = 15 ns 3 CKE VIL (MAX.), tCK = 2 CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), 25 Active standby current mA Input signals are changed one time during 30 ns. ICC2NS CKE VIH (MIN.), tCK = , 6 Input signals are stable. ICC3P CKE VIL (MAX.) , tCK = 15 ns 3 CKE VIL (MAX.) , tCK = 2 CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), 30 L in power down mode mA ICC3PS ICC3N in non power down mode mA mA Input signals are changed one time during 30 ns. ICC3NS CKE VIH (MIN.), tCK = , 15 Operating current u od Pr Input signals are stable. tCK tCK (MIN.), IO = 0 mA, -A75 130 120 100 tCK = tCK (MIN.) -A70 90 tRC = 100 ns -A75 90 -A80 90 -A10 90 tCK = tCK (MIN.) -A70 140 tRC = tRC (MIN.) -A75 130 -A80 120 -A10 Self refresh current 140 -A10 CBR (auto) refresh current -A70 -A80 (Burst mode) ICC4 CL=3 120 Both banks active ICC5 ICC6 CKE 0.2 V 1 mA 2 mA 3 mA ct Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 30 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current II (L) 0 VI VCCQ, VCCQ = VCC All other pins not under test = 0 V -1.0 +1.0 µA Output leakage current IO (L) 0 VO VCCQ, DOUT is disabled -1.5 +1.5 µA High level output voltage VOH IO = -4 mA 2.4 Low level output voltage VOL IO = +4 mA Note V 0.4 V EO AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter Value 2.4 / 0.4 L Output timing measurement reference level ns 1.4 Transition time (Input rise and fall time) V 1 Input timing measurement reference level V 1.4 AC high level input voltage / low level input voltage Unit V tCK tCL u od Pr tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V tAC tOH Output ct Data Sheet E0143N10 E0143N10 31 µPD4516161D PD4516161D Synchronous Characteristics Parameter Symbol -A70 -A 75 -A80 -A 10 Unit MIN. Clock cycle time /CAS latency = 3 tCK3 Access time from CLK /CAS latency = 3 MAX. MIN. MAX. MIN. MAX. MIN. 7 (143 MHz) 7.5 (133 MHz) 8 (125 MHz) 10 (100 MHz) ns 6 ns tAC3 CLK high level width Note MAX. 5.4 5.4 6 2.5 2.5 3 3 ns CLK low level width tCL 2.5 2.5 3 3 ns Data-out hold time tOH 2 2 2 2 ns Data-out low-impedance time tLZ 0 0 0 0 ns Data-out high-impedance time /CAS latency = 3 tHZ3 2 Data-in setup time tDS 2 2 2 2 ns Data-in hold time tDH 1 1 1 1 ns Address setup time tAS 2 2 2 2 ns Address hold time tAH 1 1 1 1 ns CKE setup time tCKS 2 2 2 2 ns CKE hold time tCKH 1 1 1 1 ns CKE setup time (Power down exit) tCKSP 2 2 2 2 ns Command (/CS, /RAS, /CAS, /WE, DQM) setup time Command (/CS, /RAS, /CAS, /WE, DQM) hold time tCMS 2 2 2 2 ns tCMH 1 1 1 1 ns L EO tCH 1 2 5.4 2 6 2 6 ns u od Pr Notes 1. Output load 5.4 1 1.4 V Z = 50 50 Output 50 pF ct 32 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D Asynchronous Characteristics Parameter Symbol -A 70 -A 75 MIN. MAX. MIN. -A80 MAX. MIN. MAX. MIN. Note MAX. 63 ACT to PRE command period tRAS 42 PRE to ACT command period tRP 21 22.5 24 30 ns Delay time ACT to READ/WRITE command tRCD 21 22.5 24 30 ns ACT (one) to ACT (another) command period tRRD 14 15 16 20 ns Data-in to PRE command period tDPL 2 2 2 2 CLK Mode register set cycle time tRSC 2 2 2 2 CLK tT 0.5 EO tRC Refresh time (2,048 refresh cycles) tREF 45 10,000 30 0.5 32 72 Unit ACT to REF/ACT command period (operation) Transition time 67.5 -A 10 48 10,000 30 0.5 32 80 50 10,000 30 1 ns 10,000 ns ns 32 32 30 ms Relationship between Frequency and Latency Speed version -75 -80 -10 7 7.5 8 10 143 133 125 100 /CAS latency 3 3 3 3 [tRCD] 3 3 3 3 6 6 6 6 L -70 Clock cycle time [ns] Frequency [MHz] /RAS latency (/CAS latency + [tRCD]) [tRAS] [tRRD] [tRP] [tDPL] [tRSC] u od Pr [tRC] 9 9 9 8 6 6 6 5 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 ct Data Sheet E0143N10 E0143N10 33 34 EO L 12.1 Mode Register Set T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; tRSC 2 CLK (MIN.) /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 ADDRESS KEY ADD Pr o DQM Hi-Z DQ Mode Register Set Command tRP Activate Command is valid ct µ µ µPD4516161D PD4516161D µ Precharge All Banks Command du EO L 12.2 Power On Sequence and CBR (Auto) Refresh CLK Clock cycle is necessary ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE tRSC High level is necessary 2 refresh cycles are necessary /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 ADDRESS KEY ADD DQM Pr o DQ Precharge All Banks Command is necessary Mode Register Set Command is necessary tRP CBR (Auto) Refresh Command is necessary CBR (Auto) Refresh Command is necessary tRC 35 ct tRC Activate Command µ µ µPD4516161D PD4516161D µ du High level is necessary 36 EO L 12.3 /CS Function (Burst Length = 4, /CAS Latency = 3) Only /CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE L A11 A10 RAa ADD RAa DQM Pr o CAa CAb L Hi-Z QAa1 DQ Read Command for Bank A QAa2 QAa3 QAa4 DAb1 Write Command for Bank A DAb2 DAb3 ct DAb4 Precharge Command for Bank A µ µ µPD4516161D PD4516161D µ Activate Command for Bank A du EO L 12.4 Clock Suspension during Burst Read (using CKE Function) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM Pr o CAa L Hi-Z QAa1 DQ Read Command for Bank A 1-CLOCK SUSPENDED QAa3 QAa4 2-CLOCK SUSPENDED 37 ct 3-CLOCK SUSPENDED Hi-Z (turn off) at the end of burst µ µ µPD4516161D PD4516161D µ Activate Command for Bank A QAa2 du 38 EO L 12.5 Clock Suspension during Burst Write (using CKE Function) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM CAa Pr o L Hi-Z DQ DAa1 Write 1-CLOCK Command SUSPENDED for Bank A DAa3 2-CLOCK SUSPENDED DAa4 3-CLOCK SUSPENDED ct µ µ µPD4516161D PD4516161D µ Activate Command for Bank A DAa2 du EO L 12.6 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE VALID /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa ADD RAa Pr o DQM Hi-Z QAa1 QAa2 QAa3 DQ Activate Command for Bank A Read Command for Bank A Power Down Mode Entry Power Down Mode Exit ACTIVE STANDBY QAa4 Precharge Command for Bank A Clock Mask Start Clock Mask End 39 ct Power Down Mode Entry PRECHARGE STANDBY Power Down Mode Exit µ µ µPD4516161D PD4516161D µ du CAa 40 EO L 12.7 CBR (Auto) Refresh T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 CLK CKE H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 ADD DQM DQ Pr o L Hi-Z tRP CBR (Auto) Refresh tRC tRC ct Activate Command Read Command Q1 µ µ µPD4516161D PD4516161D µ Precharge CBR (Auto) Refresh Command (if necessary) du EO L 12.8 Self Refresh (Entry and Exit) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; T0 T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 CLK CKE /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 ADD DQM Pr o Hi-Z DQ Precharge Command (if necessary) Self Refresh Entry Self Refresh Self Refresh Entry Exit (or Activate Command) Self Refresh Exit Next Clock Enable 41 tRP tRC ct Activate Command Next Clock Enable tRC µ µ µPD4516161D PD4516161D µ du L 42 EO L 12.9 Random Column Read (Page with Same Bank) (Burst Length = 4, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; T0 CLK H CKE /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM Pr o CAb CAa CAc L Hi-Z QAa1 DQ Read Command for Bank A Read Command for Bank A QAa3 QAa4 Read Command for Bank A QAb1 RAa Precharge Command for Bank A Activate Command for Bank A QAb2 QAc1 QAc2 QAc3 ct CAa QAc4 Read Command for Bank A µ µ µPD4516161D PD4516161D µ Activate Command for Bank A QAa2 du RAa EO L 12.10 Random Column Write (Page with Same Bank) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE H Pr o /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RBa ADD RBa DQM DQ CBa CBb CBc L Hi-Z Write Command for Bank B DBa2 DBa3 DBa4 DBb1 Write Command for Bank B DBb2 DBc1 Write Command for Bank B DBc2 DBc3 DBc4 Precharge Command for Bank B RBd 43 ct Activate Command for Bank B CBd DBd1 DBd2 Write Command for Bank B µ µ µPD4516161D PD4516161D µ Activate Command for Bank B DBa1 du RBd 44 EO L 12.11 Random Row Read (Ping-Pong Banks) (Burst Length = 8, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE H /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RBa ADD RBa DQM DQ Pr o RAa CBa RAa L Hi-Z Read Command for Bank B QBa3 QBa4 Activate Command for Bank A QBa5 QBa6 Read Command for Bank A QBa7 QBa8 Precharge Command for Bank B QAa1 RBb CBb ct QAa2 QAa3 QAa4 Activate Command for Bank B QAa5 QAa6 QAa7 Read Command for Bank B Precharge Command for Bank A µ µ µPD4516161D PD4516161D µ Activate Command for Bank B QBa1 QBa2 du CAa RBb EO L 12.12 Random Row Write (Ping-Pong Banks) (Burst Length = 8, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H Pr o /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa CBa L Hi-Z DAa2 Write Command for Bank A DAa3 DAa4 DAa5 DAa6 DAa7 Activate Command for Bank B DAa8 DBa1 DBa2 Write Command for Bank B DBa3 Precharge Command for Bank A DBa4 DBa5 RAb CAb 45 ct DBa6 Activate Command for Bank A DBa7 DBa8 DAb1 Write Command for Bank A DAb2 Precharge Command for Bank B µ µ µPD4516161D PD4516161D µ Activate Command for Bank A DAa1 du RAb 46 EO L 12.13 Read and Write (Burst Length = 4, /CAS Latency = 3) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa ADD RAa CAa Pr o du CAb CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z Read Command for Bank A QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 Write Command for Bank A Hi-Z at the end of wrap function ct QAc1 QAc2 Read Command for Bank A 0-Clock Latency 2-Clock Latency µ µ µPD4516161D PD4516161D µ Activate Command for Bank A QAa1 EO L 12.14 Interleaved Column Read Cycle (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RDa L Hi-Z Pr o CBa Aa1 Read Command for Bank A Activate Command for Bank B tRCD 47 tRRD Read Command for Bank B Aa3 Aa4 Read Command for Bank B Ba1 du CAb CBc Ba2 Read Command for Bank B Bb1 Bb2 Read Command for Bank A Bc1 ct Bc2 Precharge Command for Bank B Ab1 Ab2 Precharge Command for Bank A Ab3 Ab4 µ µ µPD4516161D PD4516161D µ Activate Command for Bank A Aa2 CBb 48 EO L 12.15 Interleaved Column Write Cycle (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa Aa1 Aa2 Pr o CBa CBb L Hi-Z Write Command for Bank A Activate Command for Bank B Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A CBd Ab2 ct Bd1 Bd2 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B µ µ µPD4516161D PD4516161D µ Activate Command for Bank A Aa3 du CAb CBc EO L 12.16 Full Page Read Cycle (/CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 RAa ADD RAa DQM DQ Pr o RBa CAa RBa CBa L Hi-Z Read Command for Bank A Activate Command for Bank B Aa+1 Aa-3 Aa-2 Aa-1 Read Command for Bank B Aa Aa+1 Ba Ba+1 RBb 49 ct Ba+2 Ba+3 Burst Stop Command Ba+4 Ba+5 Precharge Command for Bank B Activate Command for Bank B µ µ µPD4516161D PD4516161D µ Activate Command for Bank A Aa du RBb 50 EO L 12.17 Full Page Write Cycle (/CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS Pr o /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa ADD RAa DQM DQ RBa CAa RBa CBa L Hi-Z Aa+1 Write Command for Bank A Aa+2 Activate Command for Bank B Aa+3 Aa-1 Aa Aa+1 Ba Ba+1 Write Command for Bank B Ba+2 Ba+3 Ba+4 RBb ct Ba+5 Burst Stop Command Burst is not completed in the Full Page Mode Precharge Command for Bank B Activate Command for Bank B µ µ µPD4516161D PD4516161D µ Activate Command for Bank A Aa du RBb EO L 12.18 Byte Write Operation (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 Pr o ADD LDQM UDQM DQ (lower) DQ (upper) Activate Command for Bank B Read Command for Bank B Upper Byte not Read Lower Byte not Read Lower Byte not Write Upper Byte not Write Lower Byte not Write Read Command for Bank B 51 ct Lower Byte not Read Lower Byte not Read µ µ µPD4516161D PD4516161D µ du A10 52 EO L 12.19 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CKE H /CS /RAS Data Sheet E0143N10 E0143N10 /CAS /WE A11 A10 ADD Pr o DQM DQ Hi-Z Read Command for Bank B Qa2 Qa3 Qa4 D1 Single Write Command for Bank B Single Write Command for Bank B Read Command for Bank B ct Qb1 Qb2 Qb4 µ µ µPD4516161D PD4516161D µ Activate Command for Bank B Qa1 du EO L 12.20 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS Pr o /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa RBa ADD RAa RBa DQM DQ CAa CBa CAb CBb CAc L Hi-Z Activate Command for Bank B Read Command for Bank A Read Command for Bank A 53 Read Command for Bank B Read Command for Bank B QAb1 QAb2 Read Command for Bank A QBb1 QBb2 QAc1 Read Command for Bank B QAc2 QAc3 ct QBc1 QBc2 Precharge Command for Bank B (PRE Termination of Burst) QBc3 Hi-Z µ µ µPD4516161D PD4516161D µ Activate Command for Bank A QAa1 QBa1 du CBc 54 EO L 12.21 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 3) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS Pr o /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa RBa ADD RAa RBa DQM DQ CAa CBa CAb DAa1 DBa1 DAb1 CBb CAc L Hi-Z Activate Command for Bank B Write Command for Bank A Write Command for Bank A Write Command for Bank B DBb1 DBb2 Write Command for Bank B DAc1 Write Command for Bank A DAc2 DAc3 DBc1 Write Command for Bank B DBc2 DBc3 ct DBc4 Precharge Command for Bank B (PRE Termination of Burst) µ µ µPD4516161D PD4516161D µ Activate Command for Bank A DAb2 du CBc EO L 12.22 PRE (Precharge) Termination of Burst (Burst Length = 8, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; T0 CLK CKE H /CS /RAS /CAS Data Sheet E0143N10 E0143N10 /WE A11 A10 RAa ADD RAa DQM Pr o RAb CAa RAb Write Masking L Hi-Z DAa1 DQ DAa2 DAa3 DAa4 tRCD Read Command for Bank A Precharge Command for Bank A tDPL 55 tRAS Activate Command for Bank A tRP RAc ct PRE Termination of Burst tRAS QAb1 QAb2 QAb3 QAb4 Precharge Command for Bank A Activate Command for Bank A µ µ µPD4516161D PD4516161D µ PRE Termination of Burst CAb Hi-Z DAa5 Write Command for Bank A Activate Command for Bank A du RAc µPD4516161D PD4516161D 13. Package Drawing 50-PIN 50-PIN PLASTIC TSOP(II) (10.16 mm (400) 50 26 detail of lead end EO S T R L 1 Q 25 A2 L H NOTES M M J u od Pr N S B D I S G C U K ITEM 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. MILLIMETERS A 20.86±0.04 B 1.0 MAX. C 0.8 (T.P.) D 0.32 +0.08 -0.07 G 1.0±0.05 H 11.76±0.2 10.11±0.04 I J 0.825±0.2 K 0.145+0.025 -0.015 L M ct N Q 0.5 0.13 0.10 R S T U 0.1±0.05 3°+5° -3° 1.2 MAX. 0.25 (T.P.) 0.60±0.15 S50G5-80-9NF-1 S50G5-80-9NF-1 56 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D 14. Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD4516161D PD4516161D. Type of Surface Mount Device µPD4516161DG5 PD4516161DG5 : 50-pin Plastic TSOP (II) (10.16 mm(400) L EO ct u od Pr Data Sheet E0143N10 E0143N10 57 µPD4516161D PD4516161D 15. Revision History Edition / Date Page This edition Description Previous edition Type of revision Location - - - - 2nd edition / p.1 p.1 Addition Dec. 2000 p.2 p.2 p.30 p.30 p.32 p.32 p.33 p.33 NEC Corporation (M14888E M14888E) 1st edition / May 2000 EO -A70 Elpida Memory, Inc. (E0143N E0143N) Ver.1.0 / - - - Republished by Elpida Memory, Inc. May. 2001 L ct u od Pr 58 Data Sheet E0143N10 E0143N10 µPD4516161D PD4516161D NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using EO insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided L to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and 3 u od Pr related specifications governing the devices. STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. ct Data Sheet E0143N10 E0143N10 59 µPD4516161D PD4516161D EO L · The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. · Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. · Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above). ct u od Pr M8E 00. 4