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PD3747 PD3747D-A S14892EJ4V0DS00 S7400 S7399 S14892EJ4V0DS C-500S HA-50 74AC04 - Datasheet Archive
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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD3747 PD3747 7400 PIXELS CCD LINEAR IMAGE SENSOR The PD3747 PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The PD3747 PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on. FEATURES · Valid photocell : 7400 pixels · Photocell pitch : 4.7 m · Photocell size : 4.7 × 4.7 m2 · Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side) · Data rate : 44 MHz MAX. (22 MHz/1 output) · Output type : 2 outputs in phase · High sensitivity : 19.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp) · Low image lag : 1 % MAX. · Power supply : +12 V · Drive clock level : CMOS output under 5 V operation · On-chip circuits : : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package PD3747D-A PD3747D-A CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400) Remark The PD3747D-A PD3747D-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S14892EJ4V0DS00 S14892EJ4V0DS00 (4th edition) Date Published October 2006 NS CP (K) Printed in Japan The mark shows major revised points. 2000 The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field. PD3747 PD3747 BLOCK DIAGRAM GND CP 2L 2 1 21 VOUT2 (Even) GND 11 20 18 14 13 22 CCD analog shift register ··· D140 D135 S7400 S7400 Photocell S7399 S7399 S2 S1 ··· D134 D33 Transfer gate Transfer gate VOUT1 (Odd) 1 CCD analog shift register 2 5 9 10 VOD 2 4 R 2L 1 2 Data Sheet S14892EJ4V0DS S14892EJ4V0DS 12 TG PD3747 PD3747 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400) · PD3747D-A PD3747D-A Output signal 1 (Odd) VOUT1 1 22 VOUT2 Output signal 2 (Even) Output drain voltage VOD 2 21 GND Ground No connection NC 3 20 CP Reset feed-through level clamp clock Reset gate clock R 4 19 NC No connection Last stage shift register clock 2 2L 5 18 2L Last stage shift register clock 2 No connection NC 6 17 NC No connection No connection NC 7 16 NC No connection No connection NC 8 15 NC No connection Shift register clock 1 1 9 14 2 Shift register clock 2 Shift register clock 2 2 10 13 1 Shift register clock 1 Ground GND 11 12 TG Transfer gate clock Caution Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM 3.2 m 4.7 m 1.5 m Channel stopper Aluminum shield Data Sheet S14892EJ4V0DS S14892EJ4V0DS 3 PD3747 PD3747 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD -0.3 to +14 V Shift register clock voltage V 1, V 2, V 2L -0.3 to +8 V Reset gate clock voltage V R -0.3 to +8 V Reset feed-through level clamp clock voltage V CP -0.3 to +8 V Transfer gate clock voltage V TG -0.3 to +8 V TA -25 to +55 °C Tstg -40 to +100 °C Operating ambient temperature Note Storage temperature Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol MIN. TYP. MAX. Unit 11.4 12.0 12.6 V Output drain voltage Shift register clock high level V 1H, V 2H, V 2LH 4.5 5.0 5.5 V Shift register clock low level V 1L, V 2L, V 2LL -0.3 0 +0.5 V Reset gate clock high level V RH 4.5 5.0 5.5 V Reset gate clock low level V RL -0.3 0 +0.5 V Reset feed-through level clamp clock high level V CPH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level V CPL -0.3 0 +0.5 V Transfer gate clock high level V TGH 4.5 5.0 5.5 V Transfer gate clock low level V TGL -0.3 0 +0.5 V Data rate 4 VOD 2f R 1 2 44 MHz Data Sheet S14892EJ4V0DS S14892EJ4V0DS PD3747 PD3747 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, f R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S C-500S (infrared cut filter, t = 1 mm) + HA-50 HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 1.5 2.0 - V - 0.10 - lx·s Saturation voltage Vsat Saturation exposure SE Daylight color fluorescent lamp Photo response non-uniformity PRNU VOUT = 500 mV - 5 10 % Average dark signal ADS Light shielding - 0.5 3.0 mV Dark signal non-uniformity DSNU Light shielding - 8.0 14.0 mV Power consumption PW - 350 600 mW Output impedance ZO Response RF Daylight color fluorescent lamp IL VOUT = 500 mV Image lag Offset level Note 1 - 0.3 k 19.0 24.7 V/lx·s - 0.5 1.0 % 3.7 VOS Note 2 0.2 13.3 4.7 5.7 V td VOUT = 500 mV - 14 - ns Register imbalance RI VOUT = 500 mV 0 1.0 4.0 % Total transfer efficiency TTE VOUT = 1 V, data rate = 44 MHz 94 98 - % - 550 - nm Output fall delay time Response peak DR1 Random noise Shot noise Note 1 - 250 - times Vsat/ bit - 1000 - times RFTN Light shielding -300 +300 +900 mV bit Light shielding, bit clamp mode - 2.0 - mV line Reset feed-through noise Vsat/DSNU DR2 Dynamic range Light shielding, line clamp mode - 8.0 - mV shot VOUT = 500 mV, bit clamp mode - 8.0 - mV Notes 1. Refer to TIMING CHART 2, 3. 2. When the fall time of 2L (t2') is the TYP. value (refer to TIMING CHART 2, 3). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. Data Sheet S14892EJ4V0DS S14892EJ4V0DS 5 PD3747 PD3747 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Pin name 1 Pin No. MIN. TYP. MAX. Unit Shift register clock pin capacitance 2 C 2 2 2L - 250 300 pF - 250 300 pF 10 - 250 300 pF 14 C 1 9 13 Shift register clock pin capacitance 1 - 250 300 pF C L 5 - 10 20 pF 18 Last stage shift register clock pin capacitance - 10 20 pF Reset gate clock pin capacitance R 4 - 10 20 pF Reset feed-through level clamp clock pin capacitance C CP CP 20 - 10 20 pF Transfer gate clock pin capacitance 6 C R C TG TG 12 - 250 300 pF Data Sheet S14892EJ4V0DS S14892EJ4V0DS Data Sheet S14892EJ4V0DS S14892EJ4V0DS Note 135 133 131 129 127 128 125 126 35 36 33 34 31 32 29 30 5 6 3 4 1 2 Invalid photocell (6 pixels) 130 Invalid photocell (6 pixels) 132 Valid photocell (7400 pixels) 134 Optical black (96 pixels) 136 Note Set the R and CP to low level during this period. VOUT2 VOUT1 CP (Line clamp mode) 137 138 CP (Bit clamp mode) 7531 7532 R 7533 7534 2L 7535 7536 2 7537 7538 1 7539 7540 TG 7541 7542 TIMING CHART 1 Note PD3747 PD3747 7 PD3747 PD3747 TIMING CHART 2 (Bit clamp mode) t1 t1' 1 2 2L t2 t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 R t6 90% 10% t10 t8 t7 t9 t11 90% CP 10% + td RFTN VOUT1, 2 RFTN - VOS 10% Symbol t1, t2 MIN. TYP. MAX. Unit 0 50 - ns t1', t2' 5 - ns 10 125 - ns t4, t5 0 5 - ns t6 0 125 - ns t7 5 125 - ns t8, t9 0 5 - ns t10 t3 125 - ns t11 8 0 t3 0 250 - ns Data Sheet S14892EJ4V0DS S14892EJ4V0DS PD3747 PD3747 TIMING CHART 3 (Line clamp mode) t1 t1' 1 2 2L t2 t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 R CP t12 90% 10% "L" + td RFTN VOUT1, 2 RFTN - VOS 10% Symbol t1, t2 MIN. TYP. MAX. Unit 0 50 - ns t1', t2' 0 5 - ns t3 10 125 - ns t4, t5 0 5 - ns t12 5 250 - ns Data Sheet S14892EJ4V0DS S14892EJ4V0DS 9 PD3747 PD3747 TIMING CHART 4 (Bit clamp mode, Line clamp mode) t14 t15 t13 90% TG 10% t16 1 90% 2, 2L t4 t3 t5 t17 t6 90% R 10% t8 t7 t9 t10 t11 90% CP 10% Note Note Set the R and CP to low level during this period. Symbol MIN. TYP. MAX. Unit t3 10 125 - ns t4, t5 0 5 - ns t6 0 125 - ns t7 5 125 - ns t8, t9 0 5 - ns t10 t3 125 - ns t11 0 250 - ns t13 1000 1500 - ns t14, t15 0 50 - ns t16, t17 200 300 - ns 1, 2 cross points 1, 2L cross points 1 1 2 V or more 2 2 V or more 2 V or more 2L Remark Adjust cross points of ( 1, 2) and ( 1, 2L) with input resistance of each pin. 10 Data Sheet S14892EJ4V0DS S14892EJ4V0DS 0.5 V or more PD3747 PD3747 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = x × 100 x x: maximum of xj - x 7400 x x= j j=1 7400 xj: Output voltage of valid pixel number j VOUT Register dark DC level x x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 7400 d j ADS (mV) = j=1 7400 dj: Dark signal of valid pixel number j Data Sheet S14892EJ4V0DS S14892EJ4V0DS 11 PD3747 PD3747 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of dj - ADS j = 1 to 7400 dj: Dark signal of valid pixel number j VOUT ADS Register dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx·s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. TG ON Light OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 9. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each output. TTE (%) = (1 - Vb / average output of all the valid pixels) × 100 Vb Va-1 : The last pixel output - 1 (Odd pixel: 7537th pixel) Va : The last pixel output (Odd pixel: 7539th pixel) Vb : The spilt pixel output (Odd pixel: 7541st pixel) Va-1 12 Va Data Sheet S14892EJ4V0DS S14892EJ4V0DS PD3747 PD3747 10. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n (V2j 1 V2j) j=1 RI (%) = × 100 n 1 n Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 11. Random noise : Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). 100 (V V) i (mV) = i=1 100 2 , V= 1 100 V i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels VOUT V1 line 1 V2 line 2 . . V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12. Shot noise : shot Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. This includes the random noise. The formula is the same with that of random noise. Data Sheet S14892EJ4V0DS S14892EJ4V0DS 13 PD3747 PD3747 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 2 8 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.2 0.25 0.1 0.1 0 10 20 30 40 1 50 5 10 Storage Time (ms) Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTIC (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 Response Ratio (%) 80 60 40 20 0 400 600 800 Wavelength (nm) 14 Data Sheet S14892EJ4V0DS S14892EJ4V0DS 1000 1200 PD3747 PD3747 APPLICATION CIRCUIT EXAMPLE +5 V +5 V +12 V + + PD3747 PD3747 10 F/16 V 0.1 F B1 + 0.1 F 47 F/25 V 47 R 47 2L 1 2 3 4 5 6 7 8 2 2 9 2 1 10 11 22 VOUT2 VOUT1 VOD CP R NC 2L 2L NC NC NC NC NC NC 1 2 2 21 GND NC 1 47 20 CP 19 47 18 2L 17 16 15 14 2 13 2 2 1 12 TG GND 0.1 F 10 F/16 V B2 10 Caution TG Connect the No connection pins (NC) to GND. Remarks 1. It is recommended that pins 5 and 18 ( 2L) are separately driven a driver other than that of pins 10, 14 ( 2). 2. The inverters shown in the above application circuit example are the 74AC04 74AC04. B1, B2 EQUIVALENT CIRCUIT +12 V 47 F/25V F/25V 4.7 k 110 CCD VOUT 47 + 2SC945 2SC945 2SA1005 2SA1005 1 k Data Sheet S14892EJ4V0DS S14892EJ4V0DS 15 PD3747 PD3747 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22-PIN 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400) (Unit : mm) The 1st valid pixel 1 9.65 ± 0.3 3.2 ± 0.3 1.60±0.25 42.2 ± 0.25 48.6 ± 0.5 10.16 3 (1.95) 2 2.38 ±0.3 1.02 ± 0.15 2.54 (5.37) 4.68±0.5 0.46 ± 0.06 25.4 0~10° .05 0.25±0 4.33±0.5 Name Dimensions Refractive index Glass cap 47.5×9.25×0.7 1.5 1 1st valid pixel Center of pin 1 2 Photosensitive surface of CCD chip 3 Photosensitive surface of CCD chip Bottom of package Top of glass cap 22D-1CCD-PKG10 22D-1CCD-PKG10 16 Data Sheet S14892EJ4V0DS S14892EJ4V0DS PD3747 PD3747 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device PD3747D-A PD3747D-A : CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400) Process Partial heating method Cautions 1. Conditions Pin temperature : 380°C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S14892EJ4V0DS S14892EJ4V0DS 17 PD3747 PD3747 NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 2 GLASS CAP Don't either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended. 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M. 18 Data Sheet S14892EJ4V0DS S14892EJ4V0DS PD3747 PD3747 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S14892EJ4V0DS S14892EJ4V0DS 19 PD3747 PD3747 · The information in this document is current as of October, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1