PD17120 PD17121 PD17132 PD17133 PD17P132 PD17P133 IEU-1367A IEU-835A IC-8407 - Datasheet Archive

 

4-BIT SINGLE-CHIP MICROCONTROLLER µPD17120 µPD17121 µPD17132 µPD17133 µPD17P132 µPD17P133

 

µPD17120 PD17120 SUBSERIES 4-BIT SINGLE-CHIP MICROCONTROLLER µPD17120 PD17120 µPD17121 PD17121 µPD17132 PD17132 µPD17133 PD17133 µPD17P132 PD17P132 µPD17P133 PD17P133 © 1993 Document No. IEU-1367A IEU-1367A (O. D. No. IEU-835A IEU-835A) Date Published July 1995 P Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function. SIMPLEHOST is a trademark of NEC Corporation. MS-DOSTM and WINDOWSTM are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M7 94.11 INTRODUCTION Targeted Reader This manual is intended for the user engineers who understand functions of the µPD17120 PD17120 subseries and design their application systems using the µPD17120 PD17120 subseries Purpose The purpose of this manual is for the user to understand the hardware functions of the µPD17120 PD17120 subseries. Use The manual assumes that the reader has a general knowledge of electricity, logic circuits, microcontrollers. · To understand the functions of the µPD17120 PD17120 subseries in a general way; Read the manual from CHAPTER 1. · To look up instruction functions in detail when you know the mnemonic of an instruction; Use APPENDIX D INSTRUCTION LIST. · To look up an instruction when you do not know its mnemonic but know outlines of the function; Refer to 18.3 LIST OF THE INSTRUCTION SET for search for the mnemonic of the instruction, then see 18.5 INSTRUCTIONS for the function. · To look up electrical characteristics of the µPD17120 PD17120 subseries; Refer to DATA SHEET. Legend Data representation weight : High-order and low-order digits are indicated from Active low representation : ××× (pin or signal name is overlined) Address of memory map : Top: low, Bottom: high Note : Explanation of Note in the text Caution : Caution to which you should pay attention Remark : Supplementary explanation to the text Number representation : Binary number left to right. Decimal number . ×××× or ××××B . ×××× or ××××D Hexadecimal number . ××××H Relevant Documents The following documents are provided for the µPD17120 PD17120 subseries. The numbers listed in the table are the document numbers. Some related documents are preliminary versions. This document, however, is not indicated as "Preliminary". Part Number µPD17120 PD17120 µPD17121 PD17121 µPD17132 PD17132 µPD17133 PD17133 µPD17P132 PD17P132 µPD17P133 PD17P133 IC-8407 IC-8407 IC-8399 IC-8399 IC-8412 IC-8412 IC-8411 IC-8411 ID-8419 ID-8419 ID-8426 ID-8426 [IC-2972 IC-2972] [IC-2976 IC-2976] [IC-2973 IC-2973] [IC-2974 IC-2974] [ID-2971 ID-2971] [ID-2983 ID-2983] Document Name Data sheet User's manual This manual [IEU-1367 IEU-1367] IE-17K IE-17K CLICE Ver.1.6 EEU-929 EEU-929 [EEU-1467 EEU-1467] User's manual IE-17K-ET IE-17K-ET CLICE-ET Ver.1.6 EEU-931 EEU-931 [EEU-1466 EEU-1466] User's manual SE board EEU-847 EEU-847 [EEU-1412 EEU-1412] User's manual SIMPLEHOSTTM EEU-723 EEU-723 [EEU-1336 EEU-1336] (Introduction) User's manual EEU-724 EEU-724 [EEU-1337 EEU-1337] (Reference) AS17K AS17K (Ver.1.11) EEU-603 EEU-603 [EEU-1287 EEU-1287] User's manual Device file EEU-907 EEU-907 [EEU-1464 EEU-1464] User's manual Remark The numbers inside [ ] indicate English document number. The µPD17120 PD17120 subseries has different pin names and signal names depending on the system clock type, as shown in the table below. System Clock RC Oscillation Ceramic Oscillation µPD17120 PD17120 µPD17121 PD17121 µPD17132 PD17132 Pin/Signal Names µPD17133 PD17133 µPD17P132 PD17P132 µPD17P133 PD17P133 System Clock OSC1 XIN Oscillation Pin OSC0 XOUT System Clock Frequency fCC fX Unless otherwise specified, this manual uses XIN, XOUT, and fX for descriptions. When using the µPD17120 PD17120, 17132, and 17P132 17P132, please change the readings to OSC1, OSC0 and fCC. TABLE OF CONTENTS CHAPTER 1 GENERAL . 1.1 1.2 1.3 1.4 1 FUNCTION LIST . ORDERING INFORMATION . BLOCK DIAGRAM . PIN CONFIGURATION (Top View) . 2 3 4 6 CHAPTER 2 PIN FUNCTIONS . 9 2.1 PIN FUNCTIONS . 9 2.1.1 Pins in Normal Operation Mode . 9 2.1.2 Pins in Program Memory Write/Verify Mode . µPD17P132 PD17P132, 17P133 17P133 only . 11 PIN INPUT/OUTPUT CIRCUIT . HANDLING UNUSED PINS . CAUTIONS ON USE OF THE RESET AND INT PINS (in Normal Operation Mode only) . 12 17 CHAPTER 3 PROGRAM COUNTER (PC) . 19 2.2 2.3 2.4 3.1 3.2 PROGRAM COUNTER CONFIGURATION . PROGRAM COUNTER OPERATION . 18 19 19 3.2.1 Program Counter at Reset . 20 3.2.2 Program Counter during Execution of the Branch Instruction (BR) . 20 3.2.3 Program Counter during Execution of Subroutine Calls (CALL) . 21 3.2.4 Program Counter during Execution of Return Instructions (RET, RETSK, RETI) . 22 3.2.5 Program Counter during Table Reference (MOVT) . 22 3.2.6 Program Counter during Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT SKF) . 22 Program Counter When an Interrupt Is Received . 22 CAUTIONS ON PROGRAM COUNTER OPERATION . 22 CHAPTER 4 PROGRAM MEMORY (ROM) . 23 3.2.7 3.3 4.1 4.2 PROGRAM MEMORY CONFIGURATION . PROGRAM MEMORY USAGE . 23 24 4.2.1 Flow of the Program . 24 4.2.2 Table Reference . 27 CHAPTER 5 DATA MEMORY (RAM) . 31 5.1 DATA MEMORY CONFIGURATION . 31 5.1.1 System Register (SYSREG) . 32 5.1.2 Data Buffer (DBF) . 32 5.1.3 General Register (GR) . 32 5.1.4 Port Registers . 33 ­i­ 5.1.5 General Data Memory . 33 5.1.6 Uninstalled Data Memory . 33 STACK . 35 STACK CONFIGURATION . FUNCTIONS OF THE STACK . ADDRESS STACK REGISTER . INTERRUPT STACK REGISTER . STACK POINTER (SP) AND INTERRUPT STACK REGISTER . STACK OPERATION DURING SUBROUTINES, TABLE REFERENCES, AND INTERRUPTS . 35 35 36 36 36 6.6.1 Stack Operation during Subroutine Calls (CALL) and Returns (RET, RETSK) . 37 6.6.2 Stack Operation during Table Reference (MOVT DBF, @AR) . 38 6.6.3 Executing RETI Instruction . 39 STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS . 39 CHAPTER 7 SYSTEM REGISTER (SYSREG) . 41 CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7.1 7.2 SYSTEM REGISTER CONFIGURATION . ADDRESS REGISTER (AR) . 37 41 43 7.2.1 7.3 Address Register Configuration . 43 7.2.2 Address Register Functions . 43 45 Window Register Configuration . 45 7.3.2 7.4 7.5 WINDOW REGISTER (WR) . 7.3.1 Window Register Functions . 45 BANK REGISTER (BANK) . INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (Memory Pointer: MP) . 46 47 7.5.1 47 Data Memory Row Address Pointer (Memory Pointer: MP) . 47 7.5.3 MPE=0 and IXE=0 (No Data Memory Modification) . 50 7.5.4 MPE=1 and IXE=0 (Diagonal Indirect Data Transfer) . 52 7.5.5 7.6 Index Register (IX) . 7.5.2 MPE=0 and IXE=1 (Index Modification) . 54 GENERAL REGISTER POINTER (RP) . 59 7.6.1 7.7 General Register Pointer Configuration . 59 7.6.2 Functions of the General Register Pointer . 60 61 Program Status Word Configuration . 61 7.7.2 Functions of the Program Status Word . 62 7.7.3 Index Enable Flag (IXE) . 63 7.7.4 Zero Flag (Z) and Compare Flag (CMP) . 63 7.7.5 Carry Flag (CY) . 64 7.7.6 Binary-Coded Decimal Flag (BCD) . 64 7.7.7 7.8 PROGRAM STATUS WORD (PSWORD) . 7.7.1 Caution on Use of Arithmetic Operations on the Program Status Word . 64 CAUTIONS ON USE OF THE SYSTEM REGISTER . 65 7.8.1 Reserved Words for Use with the System Register . 65 7.8.2 Handling of System Register Addresses Fixed at 0 . 67 ­ ii ­ CHAPTER 8 GENERAL REGISTER (GR) . 8.1 8.2 69 GENERAL REGISTER CONFIGURATION. FUNCTIONS OF THE GENERAL REGISTER . 69 69 CHAPTER 9 REGISTER FILE (RF) . 71 9.1 71 Configuration of the Register File . 71 9.1.2 9.2 REGISTER FILE CONFIGURATION . 9.1.1 Relationship between the Register File and Data Memory . 71 FUNCTIONS OF THE REGISTER FILE . 72 9.2.1 Functions of the Register File . 72 9.2.2 Control Register Functions . 72 9.2.3 Register File Manipulation Instructions . 73 CONTROL REGISTER . CAUTIONS ON USING THE REGISTER FILE . 75 75 9.4.1 Concerning Operation of the Control Register (Read-Only and Unused Registers) . 75 9.4.2 Register File Symbol Definitions and Reserved Words . 76 CHAPTER 10 DATA BUFFER (DBF). 79 10.1 DATA BUFFER CONFIGURATION . 10.2 FUNCTIONS OF THE DATA BUFFER. 79 80 9.3 9.4 10.2.1 Data Buffer and Peripheral Hardware . 81 10.2.2 Data Transfer with Peripheral Hardware . 82 10.2.3 Table Reference . 83 CHAPTER 11 ARITHMETIC AND LOGIC UNIT . 85 11.1 ALU BLOCK CONFIGURATION . 11.2 FUNCTIONS OF THE ALU BLOCK . 85 85 11.2.1 Functions of the ALU . 85 11.2.2 Functions of Temporary Registers A and B . 90 11.2.3 Functions of the Status Flip-flop. 90 11.2.4 Performing Operations in 4-Bit Binary . 91 11.2.5 Performing Operations in BCD . 91 11.2.6 Performing Operations in the ALU Block . 93 11.3 ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD) . 94 11.3.1 Addition and Subtraction When CMP=0 and BCD=0 . 95 11.3.2 Addition and Subtraction When CMP=1 and BCD=0 . 95 11.3.3 Addition and Subtraction When CMP=0 and BCD=1 . 95 11.3.4 Addition and Subtraction When CMP=1 and BCD=1 . 96 11.3.5 Cautions on Use of Arithmetic Operations . 96 11.4 LOGICAL OPERATIONS . 11.5 BIT JUDGEMENT . 96 97 11.5.1 TRUE (1) Bit Judgement . 98 11.5.2 FALSE (0) Bit Judgement . 98 ­ iii ­ 11.6 COMPARISON JUDGEMENT . 99 11.6.1 "Equal to" Judgement . 100 11.6.2 "Not Equal to" Judgement . 100 11.6.3 "Greater Than or Equal to" Judgement . 101 11.6.4 "Less Than" Judgement . 101 11.7 ROTATIONS . 102 11.7.1 Rotation to the Right . 102 11.7.2 Rotation to the Left . 103 CHAPTER 12 PORTS . 105 PORT 0A (P0A0, P0A1, P0A2, P0A3) . 105 PORT 0B (P0B0, P0B1, P0B2, P0B3) . 106 PORT 0C (P0C0, P0C1, P0C2, P0C3) . in the case of the µPD17120 PD17120 and 17121 . 107 PORT 0C (P0C0/Cin0, P0C1/Cin1, P0C2/Cin2, P0C3/Cin3) in the case of the µPD17132 PD17132, 17133, 17P132 17P132, and 17P133 17P133 . 108 12.5 PORT 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TMOUT) . 109 12.6 PORT 0E (P0E0, P0E1/Vref) . Vref, µPD17132 PD17132, 17133, 17P132 17P132, and 17P133 17P133 only . 111 12.1 12.2 12.3 12.4 Cautions when Operating Port Registers . 112 12.7 PORT CONTROL REGISTER . 12.6.1 113 12.7.1 Input/Output Switching by Group I/O . 113 12.7.2 Input/Output Switching by Bit I/O . 114 CHAPTER 13 PERIPHERAL HARDWARE . 117 13.1 8-BIT TIMER COUNTER (TM) . 117 13.1.1 8-Bit Timer Counter Configuration . 117 13.1.2 8-bit Timer Counter Control Register . 119 13.1.3 Operation of 8-bit Timer Counters . 120 13.1.4 Selecting Count Pulse . 120 13.1.5 Setting a Count Value in Modulo Register and Calculation Method . 121 13.1.6 Margin of Error of Interval Time . 124 13.1.7 Reading Count Register Values . 126 13.1.8 Timer Output . 129 13.1.9 Timer Resolution and Maximum Setting Time . 130 13.2 COMPARATOR (mPD17132, 17133, 17P132 17P132, AND 17P133 17P133 ONLY) . 131 13.2.1 Configuration of Comparator. 131 13.2.2 Functions of Comparator. 132 13.3 SERIAL INTERFACE (SIO) . 135 13.3.1 Functions of the Serial Interface . 13.3.2 3-wire Serial Interface Operation Modes . 137 13.3.3 Setting Values in the Shift Register . 141 13.3.4 Reading Values from the Shift Register . 142 13.3.5 Program Example of Serial Interface . 143 ­ iv ­ 135 CHAPTER 14 INTERRUPT FUNCTIONS . 145 14.1 INTERRUPT SOURCES AND VECTOR ADDRESS. 14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT . 146 147 14.2.1 Interrupt Request Flag (IRQ×××) and the Interrupt Enable Flag (IP×××) . 147 14.2.2 EI/DI Instruction . 147 14.3 INTERRUPT SEQUENCE . 152 14.3.1 Acceptance of Interrupts . 152 14.3.2 Return from the Interrupt Routine . 154 14.3.3 Interrupt Acceptance Timing. 155 14.4 PROGRAM EXAMPLE OF INTERRUPT . 158 CHAPTER 15 STANDBY FUNCTIONS . 161 15.1 OUTLINE OF STANDBY FUNCTION . 15.2 HALT MODE . 161 163 15.2.1 HALT Mode Setting . 163 15.2.2 Start Address after HALT Mode is Canceled . 163 15.2.3 HALT Setting Condition . 165 15.3 STOP MODE . 167 15.3.1 STOP Mode Setting . 167 15.3.2 Start Address after STOP Mode Cancellation . 167 15.3.3 STOP Setting Condition . 169 CHAPTER 16 RESET . 171 16.1 RESET FUNCTIONS . 16.2 RESETTING . 16.3 POWER-ON/POWER-DOWN RESET FUNCTION . 171 172 173 16.3.1 Conditions Required to Enable the Power-On Reset Function . 173 16.3.2 Description and Operation of the Power-On Reset Function . 174 16.3.3 Condition Required for Use of the Power-Down Reset Function . 176 16.3.4 Description and Operation of the Power-Down Reset Function . 176 CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING . 179 17.1 DIFFERENCES BETWEEN MASK ROM VERSION AND ONE-TIME PROM VERSION . 17.2 OPERATING MODE IN PROGRAM MEMORY WRITING/VERIFYING. 17.3 WRITING PROCEDURE OF PROGRAM MEMORY . 17.4 READING PROCEDURE OF PROGRAM MEMORY . 179 180 181 182 CHAPTER 18 INSTRUCTION SET . 185 18.1 18.2 18.3 18.4 OVERVIEW OF THE INSTRUCTION SET . LEGEND . LIST OF THE INSTRUCTION SET . ASSEMBLER (AS17K AS17K) MACRO INSTRUCTIONS . ­v­ 185 186 187 188 18.5 INSTRUCTIONS. 189 18.5.1 Addition Instructions . 189 18.5.2 Subtraction Instructions . 202 18.5.3 Logical Operation Instructions . 211 18.5.4 Judgment Instruction . 216 18.5.5 Comparison Instructions . 218 18.5.6 Rotation Instructions . 221 18.5.7 Transfer Instructions . 222 18.5.8 Branch Instructions . 239 18.5.9 Subroutine Instructions . 241 18.5.10 Interrupt Instructions . 247 18.5.11 Other Instructions . 249 CHAPTER 19 ASSEMBLER RESERVED WORDS . 251 19.1 MASK OPTION PSEUDO INSTRUCTIONS. 251 19.1.1 OPTION and ENDOP Pseudo Instructions . 251 19.1.2 Mask Option Definition Pseudo Instructions . 252 19.2 RESERVED SYMBOLS . 254 19.2.1 List of Reserved Symbols (µPD17120 PD17120, 17121) . 254 19.2.2 List of Reserved Symbols (µPD17132 PD17132, 17133, 17P132 17P132, 17P133 17P133) . 260 APPENDIX A DEVELOPMENT TOOLS . 267 APPENDIX B ORDERING MASK ROM . 269 APPENDIX C CAUTIONS TO TAKE IN SYSTEM CLOCK OSCILLATION CIRCUIT CONFIGURATIONS . 271 APPENDIX D INSTRUCTION LIST . 273 APPENDIX E REVISION HISTORY . 275 ­ vi ­ LIST OF FIGURES (1/2) Figure No. Title Page 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 Program Counter . Value of the Program Counter after an Instruction Is Executed . Value in the Program Counter after Reset . Value in the Program Counter during Execution of a Direct Branch Instruction . Value in the Program Counter during Execution of an Indirect Branch Instruction . Value in the Program Counter during Execution of a Direct Subroutine Call . Value in the Program Counter during Execution of an Indirect Subroutine Call . Value in the Program Counter during Execution of a Return Instruction . 19 20 20 20 21 21 21 22 4-1 4-2 4-3 Program Memory Map for the µPD17120 PD17120 Subseries . Direct Subroutine Call (CALL addr) . Table Reference (MOVT DBF, @AR) . 23 26 27 5-1 5-2 5-3 5-4 5-5 Configuration of Data Memory . System Register Configuration . Data Buffer Configuration . General Register (GR) Configuration . Port Register Configuration . 31 32 32 33 33 6-1 Stack Configuration . 35 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 Allocation of System Register in Data Memory . System Register Configuration . Address Register Configuration . Address Register Used as a Peripheral Register . Window Register Configuration . Bank Register Configuration . Index Register and Memory Pointer Configuration . Data Memory Address Modification by Index Register and Memory Pointer . Example of Operation When MPE=0 and IXE=0 . Example of Operation When MPE=1 and IXE=0 . Example of Operation When MPE=0 and IXE=1 . Example of Operation When MPE=0 and IXE=1 . Example of Operation When MPE=0 and IXE=1 (Array Processing) . General Register Pointer Configuration . General Register Configuration . Program Status Word Configuration . Outline of Functions of the Program Status Word . 41 42 43 44 45 46 48 48 51 53 55 57 58 59 60 61 62 8-1 General Register Configuration . 70 9-1 9-2 9-3 Register File Configuration . Relationship Between the Register File and Data Memory . Accessing the Register File Using the PEEK and POKE Instructions . 71 72 74 10-1 10-2 10-3 Allocation of the Data Buffer . Data Buffer Configuration . Relationship Between the Data Buffer and Peripheral Hardware . 79 80 80 11-1 Configuration of the ALU . 86 12-1 12-2 12-3 Changes in port register due to execution of the CLR1 P0E1 instruction . Input/Output Switching by Group I/O . Bit I/O Port Control Register . 112 113 114 ­ vii ­ LIST OF FIGURES (2/2) Figure No. 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 Title Page 13-14 13-15 13-16 13-17 Configuration of the 8-bit Timer Counter . Timer Mode Register . Setting the Count Value in a Modulo Register . Error in Zero-Clearing the Count Registe during Counting . Error in Starting Counting from the Count Halt State . Reading 8-Bit Counter Count Values . Timer Output Control Mode Register . Configuration of Comparator . Comparator Input Channel Selection Register . Reference Voltage Selection Register . Comparator Operation Control Register . Block Diagram of the Serial Interface . Timing of 8-Bit Transmission and Reception Mode (Simultaneous Transmission Reception) . Timing of the 8-Bit Reception Mode . Serial Interface Control Register . Setting a Value in the Shift Register . Reading a Value from the Shift Register . 137 138 139 141 142 14-1 14-2 14-3 14-4 Interrupt Control Register . Interrupt Handling Procedure . Return from Interrupt Handling . Interrupt Acceptance Timing Chart (when INTE=1 and IP×××=1) . 148 153 154 155 15-1 15-2 Cancellation of HALT Mode . Cancellation of STOP Mode . 164 168 16-1 16-2 16-3 16-4 16-5 Reset Block Configuration . Resetting . Example of the Power-On Reset Operation . Example of the Power-Down Reset Operation . Example of Reset Operation during the Period from Power-Down Reset to Power Recovery . 172 172 175 177 178 17-1 17-2 19-1 19-2 Procedure of program Memory Writing . Procedure of Program Memory Reading . Configuration of Control Register (µPD17120 PD17120, 17121) . Configuration of Control Register (µPD17132 PD17132, 17133, 17P132 17P132, 17P133 17P133) . 182 183 258 264 C-1 C-2 Externally Installed System Clock Oscillation Circuit . Unsatisfactory Oscillation Circuit Examples . 271 272 ­ viii ­ 118 119 122 124 125 127 129 131 133 133 134 136 LIST OF TABLES (1/1) Table No. Title Page 2-1 Handling Unused Pins . 17 4-1 Vector Address for the µPD17120 PD17120 Subseries . 25 6-1 6-2 6-3 6-4 6-5 Operation of the Stack Pointer . Operation of the Stack Pointer during Execution . Stack Operation during Table Reference . Stack Operation during Interrupt Receipt and Return . Stack Operation during the PUSH and POP Instructions . 37 38 38 39 39 7-1 7-2 Address-modified Instruction Statements . Zero Flag (Z) and Compare Flag (CMP) . 49 63 10-1 Peripheral Hardware . 81 11-1 11-2 11-3 11-4 11-5 11-6 11-7 List of ALU Instructions . Results of Arithmetic Operations Performed in 4-Bit Binary and BCD . Types of Arithmetic Operations . Logical Operations . Table of True Values for Logical Operations . Bit Judgement Instructions . Comparison Judgement Instructions . 88 92 94 97 97 97 99 12-1 12-2 12-3 12-4 12-5 12-6 12-7 Writing into and Reading from the Port Register (0.70H) . Writing into and Reading from the Port Register (0.71H) . Writing/reading to/from Port Register (0.72H) (µPD17120 PD17120, 17121) . Writing into and Reading from the Port Register (0.72H) and Pin Function Selection . Register File Contents and Pin Functions . Contents Read from the Port Register (0.73H) . Writing into and Reading from the Port Registers (0.6FH.0, 0.6FH.1) . 105 106 107 108 110 110 111 13-1 13-2 13-3 Timer Resolution and Maximum Setting Time . List of Serial Clock . Serial Interface's Operation Mode . 130 135 137 14-1 14-2 Interrupt Source Types . Interrupt Request Flag and Interrupt Enable Flag . 146 147 15-1 15-2 15-3 15-4 15-5 States during Standby Mode . HALT Mode Cancellation Condition . Start Address After HALT Mode Cancellation . STOP Mode Cancellation Condition . Start Address After STOP Mode Cancellation . 162 163 163 167 167 16-1 State of Each Hardware Unit When Reset . 171 17-1 17-2 17-3 Pins Used for Writing/Verifying Program Memory . Differences Between Mask ROM Version and One-Time PROM Version . Operating Mode Setting . 179 180 180 19-1 Mask Option Definition Pseudo Instructions . 252 ­ ix ­ [MEMO] ­x­ CHAPTER 1 GENERAL The µPD17120 PD17120, 17121, 17132 and 17133 are 4-bit single-chip microcontrollers employing the 17K architecture and containing 8-bit timer (1 channel), 3-wire serial interface, and power-on/power-down reset circuit. The µPD17P132 PD17P132 and 17P133 17P133 are the one-time PROM version of the µPD17132 PD17132 and 17133, respectively, and are suitable for program evaluation at system development and for small-scale production. The following are features of the µPD17120 PD17120 subseries. · Comparator input (µPD17132 PD17132, 17133, 17P132 17P132, 17P133 17P133 only) . Comparison function with external reference voltage (Vref) . Can be used as 4-bit A/D converter by using 15 types of internal reference voltage (1/16 to 15/16 VDD) depending on the software · 3-wire serial interface: 1 channel · Power-on/power-down reset circuit (reducing external circuits) · µPD17P132 PD17P132 and 17P133 17P133 can operate in the same way as mask ROM version . VDD = 2.7 to 5.5 V These features of the µPD17120 PD17120 subseries are suitable for use as a controller or a sub-microcomputer device in the following application fields; · Electric fan · Hot plate · Audio equipment · Mouse · Printer · Plain paper copier 1 CHAPTER 1 GENERAL 1.1 FUNCTION LIST Item µPD17120 PD17120 µPD17132 PD17132 µPD17P132 PD17P132 µPD17121 PD17121 µPD17133 PD17133 µPD17P133 PD17P133 Product Name Masked ROM ROM Capacity One-time PROM Masked ROM One-time PROM 1.5K bytes 2K bytes 1.5K bytes 2K bytes (768 × 16 bits) (1024 × 16 bits) (768 × 16 bits) (1024 × 16 bits) 64 × 4 bits 111 × 4 bits 64 × 4 bits 111 × 4 bits RAM Capacity Stack 5 address stacks; 1 interrupt stack Input/output port count 19 ports · 18 input/output ports · 1 sense input (INT pinNote) Comparator 4-channel None (Supply voltage) 4-channel None (VDD = 2.7 to 5.5 V) Timer 1-channel (8-bit timer) Serial Interface (VDD = 2.7 to 5.5 V) 1-channel (3-wire) Detection of the rising edge · 1 external interrupt (INT): Interrupt Detection of the trailing edge Selectable Detection of both rising and trailing edges · 2 internal interrupts System clock Instruction Execution Time Standby Function Timer (TM) · Serial interface (SIO) RC oscillation Ceramic oscillation 8 µs (when fCC = 2 MHz) 2 µs (when fX = 8 MHz) HALT, STOP Power-on/Power-down Reset Circuit · Incorporated Incorporated (Can be used on an applied circuit Operating Supply Voltage (Can be used on an applied circuit of VDD=5 V± 10%) of VDD=5 V± 10%; fX = 400 kHz to 4 MHz) · 2.7 to 5.5 V · 4.5 to 5.5 V (When using the power-on power/down reset function) · 24-pin plastic shrink DIP (300 mil) Package · 24-pin plastic SOP (375 mil) One-time PROM Product µPD17P132 PD17P132 ­ µPD17P133 PD17P133 ­ Note When not using the external interrupt function, the INT pin can be used as an input-only pin (sense input). As a sense input, the pin status is read not by the port register but by the control register's INT flag. Caution Despite a high level of functional compatibility with the masked ROM product, the PROM product is different in terms of the internal ROM circuit and some electric features. When switching from a PROM to a masked ROM product, be sure to sufficiently evaluate the application of the masked ROM product based on its sample. 2 CHAPTER 1 GENERAL 1.2 ORDERING INFORMATION Part Number Package Internal ROM µPD17120CS- PD17120CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µPD17120GT- PD17120GT-××× 24-pin plastic SOP (375 mil) Mask ROM µPD17121CS- PD17121CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µPD17121GT- PD17121GT-××× 24-pin plastic SOP (375 mil) Mask ROM µPD17132CS- PD17132CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µPD17132GT- PD17132GT-××× 24-pin plastic SOP (375 mil) Mask ROM µPD17133CS- PD17133CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µPD17133GT- PD17133GT-××× 24-pin plastic SOP (375 mil) Mask ROM µPD17P132CS PD17P132CS 24-pin plastic shrink DIP (300 mil) One-time PROM µPD17P132GT PD17P132GT 24-pin plastic SOP (375 mil) One-time PROM µPD17P133CS PD17P133CS 24-pin plastic shrink DIP (300 mil) One-time PROM µPD17P133GT PD17P133GT 24-pin plastic SOP (375 mil) One-time PROM Remark ×××: ROM code number 3 CHAPTER 1 GENERAL 1.3 BLOCK DIAGRAM · Block diagram of the µPD17120 PD17120 and 17121 VDD Power On/ Power-Down Reset XIN CPU CLK CLK STOP XOUT RF P0A (CMOS) RAM 64 × 4 bits SYSTEM REG. P0B0 P0B1 P0B2 P0B3 System Clock Generator f X /2N P0A0 P0A1 P0A2 P0A3 Clock Divider P0B (CMOS) Interrupt Controller IRQTM ALU Timer P0C0 P0C1 P0C2 P0C3 P0C (CMOS) P0E0 P0E1 P0E (N-ch) INT IRQTM IRQSIO f X /2N Instruction Decoder ROM 768 × 16 bits P0D0 /SCK P0D1/SO P0D2/SI P0D3 /TMOUT P0D (N-ch) IRQSIO Program Counter Serial I/O RESET GND Remark Stack 5 × 10 bits TM The terms CMOS and N-ch in parentheses indicate the output form of the port. CMOS: CMOS push-pull output N-ch: N-channel open-drain output (Each pin can contain pull-up resistor as specified using a mask option.) 4 CHAPTER 1 GENERAL · Block diagram of µPD17132 PD17132, 17133, 17P132 17P132, and 17P133 17P133 VDD Power On/ Power-Down Reset XIN (CLK)Note Clock Divider System Clock Generator f X /2N CPU CLK CLK STOP XOUT RF P0A0 P0A1 P0A2 P0A3 P0A (CMOS) RAM 111 × 4 bits SYSTEM REG. P0B0 P0B1 P0B2 P0B3 P0B (CMOS) Interrupt Controller Timer P0C (CMOS) f X /2N Instruction Decoder Comparator P0E0 P0E1/Vref IRQTM IRQSIO IRQTM ALU P0C0/Cin0 P0C1/Cin1 P0C2/Cin2 P0C3/Cin3 INT (VPP)Note ROM 1024 × 16 bits P0D0 /SCK P0D1/SO P0D2/SI P0D3 /TMOUT P0D (N-ch) IRQSIO P0E (N-ch) Program Counter Serial Interface RESET GND Stack 5 × 10 bits Remark TM The terms CMOS and N-ch in parentheses indicate the output form of the port. CMOS: N-ch: CMOS push-pull output N-channel open-drain output (Each pin can contain pull-up resistor as specified using a mask option.) Note The devices in parentheses are effective only in the case of program memory write/verify mode of the µPD17P132 PD17P132 and µPD17P133 PD17P133. 5 CHAPTER 1 GENERAL 1.4 PIN CONFIGURATION (Top View) (1) Normal operating mode 24-pin plastic shrink DIP 24-pin plastic SOP 24 VDD XIN 2 23 P0E1/VrefNote 1 XOUT 3 22 P0E0 RESET 4 21 P0D3 / TMOUT P0A0 5 20 P0D2/SI P0A1 6 19 P0D1/SO P0A2 7 18 P0D0 /SCK P0A3 8 17 INT P0B0 9 16 P0C3/Cin3 Note 2 P0B1 10 15 P0C2/Cin2 Note 2 P0B2 11 14 P0C1/Cin1 Note 2 P0B3 Notes 1 12 13 P0C0 /Cin0 Note 2 µ PD17120CS- PD17120CS-×××, µ PD17120GT- PD17120GT-××× µ PD17121CS- PD17121CS-×××, µ PD17121GT- PD17121GT-××× µ PD17132CS- PD17132CS-×××, µ PD17132GT- PD17132GT-××× µ PD17133CS- PD17133CS-×××, µ PD17133GT- PD17133GT-××× µ PD17P132CS PD17P132CS, µ PD17P132GT PD17P132GT µ PD17P133CS PD17P133CS, µ PD17P133GT PD17P133GT GND 1. There is no Vref pin for the µPD17120 PD17120 and 17121. 2. Pins Cin0 to Cin3 do not exist in the µPD17120 PD17120 and 17121. 6 CHAPTER 1 GENERAL (2) Program memory write/verify mode 1 24 VDD CLK 2 23 Open 3 22 (L) 4 21 MD0 5 20 MD1 6 MD2 7 MD3 8 D0 µ PD17P132CS PD17P132CS µ PD17P132GT PD17P132GT µ PD17P133CS PD17P133CS µ PD17P133GT PD17P133GT GND 19 18 17 VPP 9 16 D7 D1 10 15 D6 D2 11 14 D5 D3 12 13 (L) D4 Caution ( ) represents processing of the pins which are not used in program memory write/verify mode. L : Connect to GND via pull-down resistor one by one. Open : This pin should not be connected. (3) Pin name Cin0 to Cin3 : Comparator input CLK : Clock input for address verification D0 to D7 : Data input/output GND : Ground INT : External interrupt input MD0 to MD3 : Operating mode selection P0A0 to P0A3 : Port 0A P0B0 to P0B3 : Port 0B P0C0 to P0C3 : Port 0C P0D0 to P0D3 : Port 0D P0E0 to P0E3 : Port 0E RESET : Reset input SCK : Serial clock input/output SI : Serial data input SO : Serial data output TMOUT : Timer output VDD : Power supply VPP : Programming voltage supply Vref : External reference voltage XIN, XOUT : System clock oscillation 7 [MEMO] 8 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS 2.1.1 Pins in Normal Operation Mode Symbol 1 GND 2 XIN 3 XOUT Output ­ ­ ­ ­ Grounded on/Reset ­ Function At Power- Format Pin No. Input CMOS Input µPD17121 PD17121, 17133, 17P133 17P133 · XIN, XOUT . Pins for system clock resonator oscillation . Connected to ceramic resonator 2 OSC1 µPD17120 PD17120, 17132, 17P132 17P132 3 OSC0 · OSC0, OSC1 . 4 RESET Pins for system clock oscillation . Resistor is connected between OSC0 and OSC1 System reset input Pull-up resistor can be incorporated by mask 5 P0A0 optionNote Port 0A | | . 8 P0A3 . 9 P0B0 | | . 4-bit I/O port 12 P0B3 . Input/output can be set by 4-bit unit 13 P0C0/Cin0 | | 16 P0C3/Cin3 4-bit I/O port Input/output can be set by each bit Port 0B Port 0C and analog voltage input of comparator · P0C0 to P0C3 . CMOS Input Push-pull CMOS Input Push-pull (P0C) ­ Input 4-bit I/O port . Push-pull Input/output can be set by each bit · Cin0 to Cin3 (µPD17132 PD17132, 17133, 17P132 17P132, 17P133 17P133 only) . 17 INT Analog input of comparator External interrupt request signal input and sense input Note The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option. 9 CHAPTER 2 PIN FUNCTIONS 18 Symbol P0D0/SCK Function Port 0D, output of timer, serial data input, serial data output, serial clock input/output Output At Power- Format Pin No. on/Reset N-ch Input Open drain (P0D) N-ch Input open drain (P0E) ­ ­ · P0D0 to P0D3 . 4-bit I/O port . Input/output can be set per bit . Pull-up resistor can be incorporated by each bit by mask optionNote · SCK . 19 P0D1/SO . 20 P0D2/SI Serial data output · SI . 21 Serial clock input/output · SO Serial data input P0D3/TMOUT · TMOUT . 22 P0E0 23 P0E1/Vref Output of timer Port 0E and reference voltage input of comparator · P0E0, P0E1 . 2-bit I/O port . Input/output can be set by each bit . Pull-up resistor can be incorporated per bit by mask optionNote · Vref (µPD17132 PD17132,17133, 17P132 17P132, 17P133 17P133 only) . 24 VDD External reference voltage input of comparator Positive power supply Note The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option. 10 CHAPTER 2 PIN FUNCTIONS 2.1.2 Pins in Program Memory Write/Verify Mode . µPD17P132 PD17P132, 17P133 17P133 only Pin No. Symbol 1 GND Grounded 2 CLK Clock input for address updating in program memory writing/verifying Input 5 MD0 | | Input for selecting operation mode in program memory writing/verifying Input 8 MD3 9 D0 | | 12 VPP I/O ­ D7 17 Function 8-bit data input/output in program memory writing/verifying Input/Output Pin for applying programming voltage in program memory ­ writing/verifying Apply +12.5 V 24 VDD Positive power supply ­ Apply +6 V in program memory writing/verifying. 11 CHAPTER 2 PIN FUNCTIONS 2.2 PIN INPUT/OUTPUT CIRCUIT Below are simplified diagrams of the input/output circuits for each pin of the µPD17120 PD17120 subseries. (1) P0A0-P0A3, P0B0-P0B3 VDD Data Output latch P-ch N-ch Output disable Selector Input buffer 12 CHAPTER 2 PIN FUNCTIONS (2) P0C0/Cin0-P0C3/Cin3Note VDD Data Output latch P-ch N-ch Output disable Input disable Selector Input buffer Analog (comparator) input Note Pins Cin0 to Cin3 are not included in the µPD17120 PD17120 and 17121. 13 CHAPTER 2 PIN FUNCTIONS (3) P0D0-P0D3 VDD Data Output latch Mask option Note N-ch Output disable Selector Input buffer Note The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option, and are always open. (4) P0E0 VDD Data Output latch Mask option Note N-ch Output disable Input buffer Note The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option, and are always open. 14 CHAPTER 2 PIN FUNCTIONS (5) P0E1/VrefNote1 VDD Data Output latch Mask option Note 2 Output disable Vref enable N-ch Selector Input buffer Vref Notes 1. The µPD17120 PD17120 and 17121 have no Vref pin function. 2. The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option, and are always open. (6) INT Input buffer 15 CHAPTER 2 PIN FUNCTIONS (7) RESET VDD Mask option Note Input buffer Note The µPD17P132 PD17P132 and 17P133 17P133 have no pull-up resistor by mask option, and are always open. 16 CHAPTER 2 PIN FUNCTIONS 2.3 HANDLING UNUSED PINS In normal operation mode, it is recommended to process the unused pins as follows: Table 2-1. Handling Unused Pins Recommended Measures Pin Name Inside Microcontroller P0A, P0B, P0C ­ Does not incorporate a pull-up Input mode P0D, P0E Outside Microcontroller Each pin is connected to VDD or GND through the resistor.Note1 resistor by the mask option Incorporates a pull-up resistor Open Port by the mask option. P0A, P0BP0C ­ (CMOS port) Outputs low level without Output mode incorporating pull-up resistor by P0D and P0E (N-ch open drain port) Open the mask option. Outputs high level with a pull-up resistor incorporated by the mask option. External Interrupt (INT)Note2 RESETNote3 when using only the built-in power-ON/power-DOWN reset ­ Directly connected to GND Does not incorporate a pull-up resistor by the mask option Directly connected to VDD Incorporates a pull-up resistor by the mask option. Notes 1. When externally pulling up (connecting to VDD through a resistor) or pulling down (connecting to the GND through a resistor), make sure to pay attention to the port's driving ability and current consumption. When pulling up or pulling down at a high resistance value, be careful to ensure that no noise is caused in the relevant pin. Although it depends on the applied circuit as well, it is usual to choose several tens of k as the resistance value for pull-up or pull-down. 2. The INT pin is for the test mode setting function as well; connect it directly to the GND when unused. 3. If the applied circuit requires a high level of reliability, be sure to design it so that the RESET signal is input externally. Also, since the RESET pin is for the test mode setting function as well, connect it directly to the VDD when unused. Caution The output levels of the input/output mode and pins are recommended to be fixed by being set repeatedly in their respective loops in the program. Remark The µPD17P132 PD17P132 and 17P133 17P133 do not contain pull-up resistors by the mask option. 17 CHAPTER 2 PIN FUNCTIONS 2.4 CAUTIONS ON USE OF THE RESET AND INT PINS (in Normal Operation Mode only) In addition to the function described in 2.1 PIN FUNCTIONS, the RESET pin and the INT pin have the function (for IC testing only) of setting test mode for testing the internal operation of the µPD17120 PD17120 subseries. If a voltage exceeding the VDD is applied to either of these pins, test mode is set. Therefore, adding a noise exceeding VDD even in normal operation may result in placing the pin in test mode, thus impeding normal operation. For example, if the RESET or INT pin wires are laid out too long, wiring noise is added to these pins, thus causing the above problem. Therefore, make sure that the wires are laid down in such a manner that such inter-wire noises are suppressed as much as possible. If noise is still a problem, take noise countermeasures based on external parts as shown in the illustrations below. · Connecting a Diode of Small VF between VDDs · Connecting a Capacitor between VDDs VDD Diode whose VF is small VDD RESET, INT 18 VDD VDD RESET, INT CHAPTER 3 PROGRAM COUNTER (PC) The program counter is used to specify an address in program memory. 3.1 PROGRAM COUNTER CONFIGURATION Figure 3-1 shows the configuration of the program counter. The program counters are 10-bit binary counters. This program counter is incremented whenever an instruction is executed. Figure 3-1. Program Counter MSB PC9 LSB PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC 3.2 PROGRAM COUNTER OPERATION Normally, the program counter is automatically incremented each time a command is executed. The memory address at which the next instruction to be executed is stored is assigned to the program counter under the following conditions: At reset; when a branch, subroutine call, return, or table referencing instruction is executed; or when an interrupt is received. Sections 3.2.1 to 3.2.7 explain program counter operating during execution of each instruction. 19 CHAPTER 3 PROGRAM COUNTER (PC) Figure 3-2. Value of the Program Counter after an Instruction Is Executed Program Counter Bit Instruction Program Counter Value PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 During reset 0 BR addr 0 0 0 0 0 0 0 0 0 Value set by addr CALL addr BR @AR CALL @AR Value in the address register (AR) (MOVT DBF, @AR) RET Value in the address stack register location pointed to the RETSK stack pointer (return address) RETI During interrupt Each interrupted vector address 3.2.1 Program Counter at Reset By setting the RESET terminals to low, the program counter is set to 000H. Figure 3-3. Value in the Program Counter after Reset MSB 0 LSB 0 0 0 0 0 0 0 0 0 All bits are set to 0 3.2.2 Program Counter during Execution of the Branch Instruction (BR) There are two ways to specify branching using the branch instruction. One is to specify the branch address in the operand using the direct branch instruction (BR addr). The other is to branch to the address specified by the address register using the indirect branch instruction (BR @AR). The address specified by a direct branch instruction is placed in the program counter. Figure 3-4. Value in the Program Counter during Execution of a Direct Branch Instruction MSB PC9 LSB PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Address specified by addr An indirect branch instruction causes the address in the address counter to be placed in the program counter. 20 CHAPTER 3 PROGRAM COUNTER (PC) Figure 3-5. Value in the Program Counter during Execution of an Indirect Branch Instruction MSB LSB PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 3.2.3 Program Counter during Execution of Subroutine Calls (CALL) There are two ways to specify branching using subroutine calls. One is to specify the branch address in the operand using the direct subroutine call (CALL addr). The other is to branch to the address specified by the address register using the indirect subroutine call (CALL @AR). A direct subroutine call causes the value in the program counter to be saved in the stack and then the address specified in the operand to be placed in the program counter. Direct subroutine calls can specify any address in program memory. Figure 3-6. Value in the Program Counter during Execution of a Direct Subroutine Call MSB PC9 LSB PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Address specified by addr An indirect subroutine call causes the value in the program counter to be saved in the stack and then the value in the address register to be placed in the program counter. Figure 3-7. Value in the Program Counter during Execution of an Indirect Subroutine Call Address stack register n (n = 0 to 4) MSB LSB PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 21 CHAPTER 3 PROGRAM COUNTER (PC) 3.2.4 Program Counter during Execution of Return Instructions (RET, RETSK, RETI) During execution of a return instruction (RET, RETSK, RETI), the program counter is restored to the value saved in the address stack register. Figure 3-8. Value in the Program Counter during Execution of a Return Instruction Address stack register n (n = 0 to 4) MSB PC9 LSB PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 3.2.5 Program Counter during Table Reference (MOVT) During execution of table reference (MOVT DBF, @AR), the value in the program counter is saved in the stack, the address register is set by the program counter, then the contents stored at that program memory location is read into the data buffer (DBF). After the program memory contents are read into DBF, the program counter is restored to the value saved in the address stack register. Caution One level of the address stack is temporarily used during execution of table reference. Be careful of the stack level. 3.2.6 Program Counter during Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT SKF) When skip conditions are met and a skip instruction (SKE, SKGE, SKLT, SKNE, SKT, SKF) is executed, the instruction immediately following the skip instruction is treated as a no operation instruction (NOP). Therefore, whether skip conditions are met or not, the number of instructions executed and instruction execution time remain the same. 3.2.7 Program Counter When an Interrupt Is Received When an interrupt is received, the value in the program counter is saved in the address stack. Next, the vector address for the interrupt received is placed in the program counter. 3.3 CAUTIONS ON PROGRAM COUNTER OPERATION Consisting of 10 bits, the µPD17120/17121 PD17120/17121's program counter (PC) can specify a program of up to 1024 steps. As opposed to this, the ROM size is only 768 steps (addresses 0000H-02FFH 0000H-02FFH). If the program counter's value exceeds 300H, the contents of the program are equivalent to reading FFFFH and executing the "SKF PSW, #0FH" instruction. Therefore, be careful about the following point: (1) When the instruction at the 768th step (address 02FFH 02FFH) is executed, it does not automatically happen that the program counter goes to 0000H 0000H. If the instruction up to the 768th step (address 02FFH 02FFH) is other than a branch (BR) or (RET) instruction, it will result in specifying a program counter not contained in a ROM. Be careful about this. (2) In the same manner as (1), please avoid using an instruction that will branch to after the 768th step (address 02FFH 02FFH). 22 CHAPTER 4 PROGRAM MEMORY (ROM) The program configuration of the µPD17120 PD17120 subseries is as follows. Product Name 0000H-02FFH 0000H-02FFH 2K bytes (1024 × 16 bits) µPD17121 PD17121 Program Memory Address 1.5K bytes (768 × 16 bits) µPD17120 PD17120 Program Memory Capacity 0000H-03FFH 0000H-03FFH µPD17132 PD17132 µPD17133 PD17133 µPD17P132 PD17P132 µPD17P133 PD17P133 Program memory stores the program, and the constant data table. The top of the program memory is allocated to the reset start address and the interrupted vector address. The program memory address is specified by the program counter. 4.1 PROGRAM MEMORY CONFIGURATION Figure 4-1 shows the program memory map. Branch instructions, subroutine calls, and table references can specify any address in program memory (0000H 0000H - 07FFH 07FFH). Figure 4-1. Program Memory Map for the µPD17120 PD17120 Subseries Address 16 bits 0000H 0000H Reset start address 0001H 0001H Serial interface interrupt vector 0002H 0002H Timer interrupt vector 0003H 0003H External (INT) interrupt vector Subroutine entry address for the CALL addr instruction ( µ PD17120/17121 PD17120/17121) 02FFH 02FFH ( µ PD17132/17133/17P132/17P133 PD17132/17133/17P132/17P133) Branch address for the BR addr instruction Branch address for the BR @AR instruction Subroutine entry address for the CALL @AR instruction Table reference address for the MOVT DBF, @AR instruction 03FFH 03FFH 23 CHAPTER 4 PROGRAM MEMORY (ROM) 4.2 PROGRAM MEMORY USAGE Program memory has the following two main functions: (1) Storage of the program (2) Storage of constant data The program is made up of the instructions which operate the CPU (Central Processing Unit). The CPU executes sequential processing according to the instructions stored in the program. In other words, the CPU reads each instruction in the order stored by the program in program memory and executes it. Since all instructions are 16-bit long words, each instruction is stored in a single location in program memory. Constant data, such as display output patterns, are set beforehand. The MOVT instruction is used to transfer data from program memory to the data buffer (DBF) in data memory. Reading the constant data in program memory is called table reference. Program memory is read-only (ROM: Read Only Memory) and therefore cannot be changed by any instructions. 4.2.1 Flow of the Program The program is usually stored in program memory starting from memory location 0000H 0000H and executed sequentially one memory location at a time. However, if for some reason a different kind of program is to be executed, it will be necessary to change the flow of the program. In this case, the branch instruction (BR instruction) is used. If the same section of program code is going to appear in a number of places, reproducing the code each time it needs to be used will decrease the efficiency of the program. In this case, this section of program code should be stored in only one place in memory. Then, by using the CALL instruction, this piece of code can be executed or read as many times as needed within the program. Such a piece of code is called a subroutine. As opposed to a subroutine, code used during normal operation is called the main routine. For cases completely unrelated to the flow of the program (in which a section of code is to be executed when a certain condition arises), the interrupt function is used. Whenever a condition arises that is unrelated to the flow of the program, the interrupt function can be used to branch the program to a prechosen memory location (called a vector address). Items (1) to (5) explain branching of the program using the interrupt function and CPU instructions. (1) Vector Address Table 4-1 shows the address to which the program is branched (vector address) when a reset or interrupt occurs. 24 CHAPTER 4 PROGRAM MEMORY (ROM) Table 4-1. Vector Address for the µPD17120 PD17120 Subseries Vector Address Interrupt Sources 0000H 0000H Reset 0001H 0001H Serial interface interrupt 0002H 0002H Timer interrupt 0003H 0003H External interrupt (INT pin) (2) Direct branch When executing a direct branch (BR addr), the 11-bit instruction operand is used to specify an address in program memory. (However, the most significant bit must be 0. If an address is specified outside of this range, an error will occur in the assembler.) A direct branch instruction can be used to branch to any address in program memory. (3) Indirect branch When executing an indirect branch (BR @AR), the program branches to the address specified by the value stored in the address register (AR). An indirect branch can be used to branch to any address in program memory. Also refer to 7.2 ADDRESS REGISTER (AR). (4) Direct subroutine call When using a direct subroutine call (CALL addr), the 11-bit instruction operand is used to specify a program memory address of the called subroutine. (However, the most significant bit must be 0. If an address is specified outside of this range, an error will occur in the assembler). 25 CHAPTER 4 PROGRAM MEMORY (ROM) Example Figure 4-2. Direct Subroutine Call (CALL addr) Program memory Adddress 0000H 0000H CALL SUB1 SUB1: RET 03FFH 03FFH Note Note The last address of the program memory of the µPD17120 PD17120 and µPD17121 PD17121 is 02FFH 02FFH. (5) Indirect subroutine call When using an indirect subroutine call (CALL @AR), the value in the address register (AR) should be an address of the called subroutine. This instruction can be used to call any address in program memory. Also refer to 7.2 ADDRESS REGISTER (AR). 26 CHAPTER 4 PROGRAM MEMORY (ROM) 4.2.2 Table Reference Table reference is used to reference constant data in program memory. The table reference instruction (MOVT DBF, @AF) is used to store the contents of the program memory address specified by the address register in the data buffer. Since each location in program memory contains 16 bits of information, the MOVT instruction causes 16 bits of data to be stored in the data buffer. The address register can be used to table reference any location in program memory. Caution Note that one level of the stack is temporarily used when performing table reference. Also refer to 7.2 ADDRESS REGISTER (AR) and CHAPTER 10 DATA BUFFER (DBF). Remark As an exception, execution of table reference instructions requires two instruction cycle. Figure 4-3. Table Reference (MOVT DBF, @AR) Data buffer DBF3 DBF2 DBF1 DBF0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Program memory b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 16-bit data read Address register AR3 AR2 AR1 AR0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 0 0 0 0 0 0 Constant data Table addressing 27 CHAPTER 4 PROGRAM MEMORY (ROM) (1) Constant data table Example 1 shows an example of code used to reference a constant data table. Example 1. Code used for reading the values recorded in a constant data table. The value specified by an OFFSET value is read. OFFSET MEM 0.00H ; Storing area for the offset address. MOV RPH,#0 ; Register pointer 7 is used to specify that MOV RPL,#7 SHL 1 ; operation results be stored in row address 7. ; BANK0 ROMREF: ; BANK0 ; Stores the start address of the constant data ; table in the address register (AR). MOV AR3, #.DL.TABLE SHR 12 AND 0FH MOV AR2, #.DL.TABLE SHR 8 AND 0FH MOV AR1, #.DL.TABLE SHR 4 AND 0FH MOV AR0, #.DL.TABLE AND 0FH ADD AR0, OFFSET ADDC AR1, #0 ADDC AR2, #0 ADDC AR3, #0 MOVT DBF, @AR TABLE: DW 0001H 0001H DW 0002H 0002H DW 0004H 0004H DW 0008H 0008H DW 0010H 0010H DW 0020H 0020H DW 0040H 0040H DW 0080H 0080H DW 0100H 0100H DW 0200H 0200H DW 0400H 0400H DW 0800H 0800H DW 1000H 1000H DW 2000H 2000H DW 4000H 4000H DW 8000H 8000H END 28 ; Adds the offset address. ; Executes the table reference instruction. CHAPTER 4 PROGRAM MEMORY (ROM) (2) Branch table Example 2 shows an example of code used to reference a branch table. Example 2. Code used for reading the values recorded in a branch table. The value specified by an OFFSET value is read. OFFSET MEM 0.00H ; Storing area for the offset address. MOV RPH,#0 ; Sets the register pointer to row MOV RPL,#7 SHL 1 ; address 7. ; BANK0 ROMREF: ; BANK0 ; Stores the start address of the constant data ; table in the address register (AR). MOV AR3, #.DL.TABLE SHR 12 AND 0FH MOV AR2, #.DL.TABLE SHR 8 AND 0FH MOV AR1, #.DL.TABLE SHR 4 AND 0FH MOV AR0, #.DL.TABLE AND 0FH ADD AR0, OFFSET ADDC AR1, #0 MOVT DBF, @AR PUT AR, DBF BR ; Adds the offset address. ; Executes the table reference instruction. @AR TABLE: DW 0001H 0001H DW 0002H 0002H DW 0004H 0004H DW 0008H 0008H DW 0010H 0010H DW 0020H 0020H DW 0040H 0040H DW 0080H 0080H DW 0100H 0100H DW 0200H 0200H END 29 [MEMO] 30 CHAPTER 5 DATA MEMORY (RAM) Data memory stores data such as operation and control data. Data can be read from or written to data memory with an instruction during normal operation. 5.1 DATA MEMORY CONFIGURATION Figure 5-1 shows the configuration of data memory. Data memory is controlled by the concept called banks. The µPD17120 PD17120 subseries has BANK0 only. An address is allocated to the data memory for each bank. An address consists of four bits of memory called "a nibble". The address of data memory consists of 7 bits. The three high-order bits are called "the row address", and the four low-order bits are called "the column address". For example, when the address of data memory is 1AH (0011010B 0011010B), the row address is 1H (001B), and the column address is AH (1010B 1010B). In the case of the µPD17120 PD17120 and 17121, addresses 40H to 6EH should not be used because they are non-mounted areas. Sections 5.1.1 to 5.1.6 describe functions of data memory other than its use as address space. Figure 5-1. Configuration of Data Memory BANK0 0 1 2 3 4 5 6 7 8 9 A B C D E F DBF3 DBF2 DBF1 DBF0 0 1 Example: Address 1AH of BANK0 2 3 4 5 P0E (2 bits) 6 7 P0A P0B P0C P0D 4 bits 4 bits 4 bits 4 bits Remark System register The shaded parts represent the non-mounted area in the case of the µPD17120 PD17120 and 17121. 31 CHAPTER 5 DATA MEMORY (RAM) 5.1.1 System Register (SYSREG) The system register (SYSREG) consists of the 12 nibbles allocated at addresses 74H to 7FH in data memory. The system register (SYSREG) is allocated independently of the banks. This means that each bank has the same system register at addresses 74H to 7FH. Figure 5-2 shows the configuration of the system register. Figure 5-2. System Register Configuration System Register (SYSREG) Address 74H 75H 76H 77H 78H 79H Window Bank register register (WR) 7AH (BANK) 7BH 7CH 7DH 7EH 7FH Index register Name Address register (Symbol) (AR) General Program Data memory register status word row address pointer (RP) (PSWORD) (IX) pointer (MP) 5.1.2 Data Buffer (DBF) The data buffer consists of four nibbles allocated at addresses 0CH to 0FH in BANK0 of data memory. Figure 5-3 shows the configuration of the data buffer. Figure 5-3. Data Buffer Configuration Data Buffer (DBF) Address 0CH 0DH 0EH 0FH Symbol DBF3 DBF2 DBF1 DBF0 5.1.3 General Register (GR) The general register consists of 16 nibbles specified by an arbitrary row address in a bank in data memory. This arbitrary row address in a bank is pointed to by the register pointer (RP) in the system register (SYSREG). In the case of the µPD17120 PD17120 and 17121, addresses 40H to 6EH are non-mounted areas. These areas should not be specified as a general register. Figure 5-4 shows the configuration of the general register (GR). 32 CHAPTER 5 DATA MEMORY (RAM) Figure 5-4. General Register (GR) Configuration Column address BANK0 General register Row address 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 A B C D E F Area specifiable as general register Port register Pointed to by general register pointer (RP) in system register. Note that row addresses 4 to 6 in the case of the µ PD17120 PD17120 and 17121 are uninstalled memory locations. The register pointer (RP) should therefore not specify a row address in this area. SYSREG 5.1.4 Port Registers A port register consists of five nibbles allocated at addresses 6FH to 73H in Bank0 of the data memory. As shown in Figure 5-5, the two high-order bits of address 6FH are always set to 0. Figure 5-5 shows the configuration of the port registers. Figure 5-5. Port Register Configuration Port Register 6FH 70H 71H 72H 73H P0E Symbol Address P0A P0B P0C P0D P 0 0 P P P P P P P P P P P P P P P P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E E A A A A B B B B C C C C D D D D 1 BANK0 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 5.1.5 General Data Memory General data memory is all the data memory not used by the port and system registers (SYSREG). In other words, general data memory consists of 64 nibbles (µPD17120 PD17120 and 17121) or 111 nibbles (µPD17132 PD17132, 17133, 17P132 17P132, and 17P133 17P133). 5.1.6 Uninstalled Data Memory There is no hardware installed at addresses 40H to 6EH of the µPD17120 PD17120 and 17121. Any attempt to read this area will yield unpredictable results. Writing data to this area is invalid and should therefore not be attempted. 33 [MEMO] 34 CHAPTER 6 STACK The stack is a register used to save information such as the program return address and the contents of the system register during execution of subroutine calls, interrupts and similar operations. 6.1 STACK CONFIGURATION Figure 6-1 shows the stack configuration. The stack consists of the following parts: one 3-bit binary counter stack pointer, five 10-bit address stack registers, and one 5-bit interrupt stack registers. Figure 6-1. Stack Configuration Stack Pointer (SP) Address Stack Register (ASR) b2 b1 b0 SPb2 SPb1 SPb0 b10 b9 b8 b7 b6 b5 b4 b3 0H Address stack register 2 3H Address stack register 3 4H b0 Address stack register 1 2H b1 Address stack register 0 1H b2 Address stack register 4 Interrupt Stack Register (INTSK) 0H BCDSK CMPSK CYSK ZSK IXESK 6.2 FUNCTIONS OF THE STACK The stack is used to save the return address during execution of subroutine calls and table reference instructions. When an interrupt occurs, the program return address and the program status word (PSWORD) are automatically saved in the stack. Remark All the 5 bits of PSWORD are automatically cleared to zero after being saved in the interrupt stack register. 35 CHAPTER 6 STACK 6.3 ADDRESS STACK REGISTER As shown in Figure 6-1, the address stack register consists of five consecutive 10-bit registers. A value equal to the program counter (PC)+1 (return address) is stored during execution of subroutine calls (CALL addr, CALL @AR), the first cycle of a table reference (MOVT DBF, @AR), and upon receipt of an interrupt in the address stack register. The contents of the address register (AR) is also stored when a stack push (PUSH AR) is executed. The address register holding data is pointed to by the address in the stack pointer at execution time less one (address in stack pointer (SP) ­ 1). When a subroutine return (RET, RETSK), an interrupt return (RETI), or the second cycle of a table reference (MOVT DBF, @AR) is executed, the contents of the address pointed to by the stack pointer is restored to the program counter and the stack pointer is incremented. When a stack pop (POP AR) is executed, the value in the address stack register pointed to by the stack pointer is transferred to the address to the address register and the stack pointer is incremented. If more than five subroutine calls or interrupts are executed, an internal reset signal is generated, and the address stack register initializes hardware for start at address 0000H 0000H (to prevent a software crash). 6.4 INTERRUPT STACK REGISTER As shown in Figure 6-1, the interrupt stack register consists of one 5-bit register. When an interrupt is received five bits in the system register (SYSREG) (mentioned later) that is, each flag (BCD, CMP, CY, Z, IXE) of the program status word (PSWORD), are saved. When the interrupt return (RETI) is executed, the program status word is restored from the interrupt stack register. In the interrupt stack register, every time an interrupt is received, necessary data is saved. When more than three interrupts are received, the data from the first interrupt is lost. Remark All the 5 bits of PSWORD are automatically cleared to zero after being saved in the interrupt stack register. 6.5 STACK POINTER (SP) AND INTERRUPT STACK REGISTER As shown in Figure 6-1, the stack pointer (SP) is a 3-bit binary counter used to point to addresses in the five address stack registers. The stack pointer is located at address 01H in the register file. At reset, the stack pointer is set to 5. As shown in Table 6-1, the stack pointer is decremented when subroutine calls (CALL addr, CALL @AR), the first cycle of a table reference (MOVT DBF, @AR), stack push (PUSH AR), and an interrupt are accepted. The stack pointer is incremented at the following times: subroutine returns (RET, RETSK), the second instruction cycle of a table reference (MOVT DBF, @AR), stack pop (POP AR), and an interrupt return (RETI). The interrupt stack counter as well as the stack pointer is decremented when an interrupt is accepted. The interrupt stack counter is incremented by an interrupt return (RETI) only. 36 CHAPTER 6 STACK Table 6-1. Operation of the Stack Pointer Instruction Stack Pointer Value Counter of Interrupt Stack Register ­1 Not changed ­1 ­1 +1 Not changed +1 +1 CALL addr CALL @AR MOVT DBF, @AR (1st instruction cycle) PUSH AR Interrupt receipt RET RETSK MOVT DBF, @AR (2nd instruction cycle) POP AR RETI As mentioned above, the stack pointer is a 3-bit counter and therefore can conceivably store any of the eight values from 0H to 7H. Since there are only five address stack registers, however, a stack pointer value that is greater than five will cause an internal reset signal to be generated (to prevent a software crash). Since the stack pointer is located in the register file, it can be read and written to directly by using the PEEK and POKE instructions to manipulate the register file. When this is done, the stack pointer value will change but the values in the address stack register will not be affected. 6.6 STACK OPERATION DURING SUBROUTINES, TABLE REFERENCES, AND INTERRUPTS Stack operation during execution of each command is explained in 6.6.1 to 6.6.3. 6.6.1 Stack Operation during Subroutine Calls (CALL) and Returns (RET, RETSK) Table 6-2 shows operation of the stack pointer (SP), address stack register, and the program counter (PC) during execution of subroutine calls and returns. 37 CHAPTER 6 STACK Table 6-2. Operation of the Stack Pointer during Execution Instruction CALL addr Operation Stack pointer (SP) is decremented. Program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). Value specified by the instruction operand (addr) is transferred to the program counter. RET Value in the address stack register pointed to by the stack pointer (SP) is restored RETSK to the program counter (PC). Stack pointer (SP) is incremented. When the RETSK instruction is executed, the first command after data restoration becomes a no operation instruction (NOP). 6.6.2 Stack Operation during Table Reference (MOVT DBF, @AR) Table 6-3 shows stack operation during table reference. Table 6-3. Stack Operation during Table Reference Instruction MOVT DBF, @AR Instruction Cycle First Operation Stack pointer (SP) is decremented. Program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). Value in the address register (AR) is transferred to the program counter (PC). Second Contents of the program memory (ROM) pointed to by the program counter (PC) is transferred to the data buffer (DBF). Value in the address stack register pointed to by the stack pointer (SP) is restored to the program counter (PC). Stack pointer (SP) is incremented. Remark 38 As an exception, execution of MOVT DBF and @AR instructions require two instruction cycle. CHAPTER 6 STACK 6.6.3 Executing RETI Instruction Table 6-4 shows stack operation during interrupt receipt and RETI instruction execution. Table 6-4. Stack Operation during Interrupt Receipt and Return Instruction Operation Receipt of interrupt Stack pointer (SP) is decremented. Value in the program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). Values in the PSWORD flags (BCD, CMP, CY, Z, IXE) are saved in the interrupt stack. Vector address is transferred to the program counter (PC) RETI Values in the interrupt stack register are restored to the PSWORD (BCD, CMP, CY Z, IXE). Values in the address stack register pointed to by the stack pointer (SP) is restored to the program counter (PC). Stack pointer (SP) is incremented. 6.7 STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS During execution of operations such as subroutine calls and returns, the stack pointer (SP) simply functions as a 3-bit counter which is incremented and decremented. When the value in the stack pointer is 0H and a CALL or MOVT instruction is executed or an interrupt is received, the stack pointer is decremented to 7H. The µPD17120 PD17120 subseries treats this condition as a fault and generates an internal reset signal. In order to avoid this condition, when the address stack register is being used frequently, the PUSH and POP instructions are used as necessary to save/return the address stack register. Table 6-5 shows stack operation during the PUSH and POP instructions. Table 6-5. Stack Operation during the PUSH and POP Instructions Instruction PUSH Operation Stack pointer (SP) is decremented. Value in the address register (AR) is transferred to the address stack register pointed to by the stack pointer (SP). POP Value in the address stack register pointed to by the stack pointer (SP) is transfer