PD17704A PD17P709A PD17704 PD17705 PD17707 PD17708 PD17709 PD17709A - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µ PD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION The µ PD17704A PD17704A, 17705A, 17707A, 17708A, and 17709A are 4-bit single-chip CMOS microcontrollers containing hardware for digital tuning systems. Provided with a wealth of hardware, these microcontrollers are available with many variations of ROM and RAM capacities to support various applications. Therefore, a high-performance, multi-function digital tuning system can be configured with only one chip. In addition, a one-time PROM model, µ PD17P709A PD17P709A, which can be written only once and is ideal for program evaluation and small-scale production of a µ PD17704A PD17704A, 17705A, 17707A, 17708A, or 17709A system, is also available. FEATURES µ PD17704 PD17704 Program memory (ROM) 16 KB (8192 × 16 bits) General-purpose data memory (RAM) µ PD17705 PD17705 672 × 4 bits µ PD17707 PD17707 24 KB (12288 × 16 bits) µ PD17708 PD17708 32 KB (16384 × 16 bits) 1120 × 4 bits · Instruction execution time µ PD17709 PD17709 1776 × 4 bits · Many interrupts 1.78 µ s (with f X = 4.5 MHz crystal oscillator) · PLL frequency synthesizer External: 6 sources Internal: Dual modulus prescaler (130 MHz MAX.), 6 sources · Power-on reset, CE reset, and power failure programmable divider, phase comparator, charge detector · Supply voltage: V DD = 5 V ±10% pump · Abundant peripheral hardware units General-purpose I/O ports, serial interfaces, A/D converter, D/A converter (PWM output), BEEP output, frequency counter Unless otherwise specified, the µ PD17709A PD17709A is treated as the representative model in this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15722EJ1V1DS00 U15722EJ1V1DS00 (1st edition) Date Published October 2001 N CP (K) Printed in Japan The mark shows major revised points. © 2001 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A ORDERING INFORMATION Part Number Package µ PD17704AGC- PD17704AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17705AGC- PD17705AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17707AGC- PD17707AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17708AGC- PD17708AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17709AGC- PD17709AGC-×××-3B9 80-pin plastic QFP (14 × 14) Remark ××× indicates ROM code suffix. FUNCTIONAL OUTLINE Part Number Item Program memory (ROM) µ PD17704A PD17704A µ PD17705A PD17705A µ PD17707A PD17707A 24 KB (12288 × 16 bits) 16 KB µ PD17708A PD17708A µ PD17709A PD17709A 32 KB (16384 × 16 bits) (8192 × 16 bits) General-purpose data memory (RAM) 672 × 4 bits Instruction execution time 1.78 µ s (with f X = 4.5 MHz crystal oscillator) General-purpose ports · I/O ports: 46 · Input ports: 12 · Output ports: 4 Stack levels · Address stack: 15 levels · Interrupt stack: 4 levels · DBF stack: 4 levels (can be manipulated via software) Interrupts 1120 × 4 bits 1176 × 4 bits · External: 6 sources (falling edge of CE pin, INT0 through INT4) · Internal: Timer 5 · · · · 6 sources (timers 0 through 3, serial interfaces 0 and 1) channels Basic timer (clock: 10, 20, 50, 100 Hz): 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz): 8-bit timer (clock: 1 kHz, 2 kHz, 10 kHz, 100 kHz): 8-bit timer multiplexed with PWM (clock: 440 Hz, 4.4 kHz): 1 1 2 1 channel channel channels channel A/D converter 8 bits × 6 channels (hardware mode and software mode selectable) D/A converter (PWM) 3 channels (8-bit or 9-bit resolution selectable by software) Output frequency: 4.4 kHz, 440 Hz (with 8-bit PWM selected) 2.2 kHz, 220 Hz (with 9-bit PWM selected) Serial interface 2 units (3 channels) · 3-wire serial I/O: 2 channels · 2-wire serial I/O/I 2 C bus: 1 channel PLL frequency synthesizer · Direct division mode (VCOL pin (MF mode): 0.5 to 3 MHz) · Pulse swallow mode (VCOL pin (HF mode): 10 to 40 MHz) (VCOH pin (VHF mode): 60 to 130 MHz) Reference frequency 13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 kHz) Charge pump Two error-out output pins (EO0, EO1) Phase comparator 2 Division mode Unlock status detectable by program Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Part Number Item µ PD17704A PD17704A µ PD17705A PD17705A µ PD17707A PD17707A µ PD17708A PD17708A µ PD17709A PD17709A Frequency counter · Intermediate frequency (IF) measurement P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode 0.4 to 0.5 MHz in AMIF mode P1C1/AMIFC pin: 0.4 to 0.5 MHz in AMIF mode · External gate width measurement P2A1/FCG1, P2A0/FCG0 pin BEEP output 2 pins Output frequency: 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin) 67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin) Reset · Power-on reset (on power application) · Reset by RESET pin · Watchdog timer reset Can be set only once on power application: 65536 instructions, 131072 instructions, or no-use selectable · Stack pointer overflow/underflow reset Can be set only once on power application: interrupt stack or address stack selectable · CE reset (CE pin low high level) CE reset delay timing can be set. · Power failure detection function Standby · Clock stop mode (STOP) · Halt mode (HALT) Supply voltage · PLL operation: VDD = 4.5 to 5.5 V · CPU operation: V DD = 3.5 to 5.5 V Package 80-pin plastic QFP (14 × 14) Data Sheet U15722EJ1V1DS U15722EJ1V1DS 3 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A PIN CONFIGURATION (TOP VIEW) 80-pin plastic QFP (14 × 14) µ PD17704AGC- PD17704AGC-×××-3B9 µ PD17705AGC- PD17705AGC-×××-3B9 µ PD17707AGC- PD17707AGC-×××-3B9 µ PD17708AGC- PD17708AGC-×××-3B9 P0C1 P0C0 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P2D2 P2D1 P2D0 REG GND0 XIN XOUT CE VDD0 RESET µ PD17709AGC- PD17709AGC-×××-3B9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INT2 1 60 P0C2 P1A3/INT4 2 59 P0C3 P1A2/INT3 3 58 P2C0 P1A1 4 57 P2C1 P1A0/TM0G 5 56 P2C2 P3A3 6 55 P2C3 P3A2 7 54 P3D0 P3A1 8 53 P3D1 P3A0 9 52 P3D2 P3B3 10 51 P3D3 P3B2 11 50 P3C0 P3B1 12 49 P3C1 P3B0 13 48 P3C2 P2A2 14 47 P3C3 P2A1/FCG1 15 46 P2B0 P2A0/FCG0 16 45 P2B1 P1B3 17 44 P2B2 P1B2/PWM2 18 43 P2B3 P1B1/PWM1 19 42 INT0 P1B0/PWM0 20 41 INT1 Data Sheet U15722EJ1V1DS U15722EJ1V1DS P1D0/BEEP0 P1D2 P1D1/BEEP1 P1D3 TEST EO1 EO0 GND1 VCOL VCOH VDD1 P1C0/FMIFC P1C1/AMIFC P1C2/AD4 P1C3/AD5 P0D0/AD0 P0D1/AD1 P0D2/AD2 GND2 4 P0D3/AD3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A PIN NAMES AD0 to AD5: A/D converter input P2C0 to P2C3: Port 2C AMIFC: AM frequency counter input P2D0 to P2D2: Port 2D BEEP0, BEEP1: BEEP output P3A0 to P3A3: Port 3A CE: Chip enable P3B0 to P3B3: Port 3B EO0, EO1: Error-out output P3C0 to P3C3: Port 3C FCG0, FGC1: Frequency counter gate input P3D0 to P3D3: Port 3D FMIFC: FM frequency counter input REG: CPU regulator GND0 to GND2: Ground 0 to 2 RESET: Reset input INT0 to INT4: External interrupt input SCK0, SCK1: 3-wire serial clock I/O PWM0 to PWM2: D/A converter output SCL: 2-wire serial clock I/O P0A0 to P0A3: Port 0A SDA: 2-wire serial data I/O P0B0 to P0B3: Port 0B SI0, SI1: 3-wire serial data input P0C0 to P0C3: Port 0C SO0, SO1: 3-wire serial data output P0D0 to P0D3: Port 0D TEST: Test input P1A0 to P1A3: Port 1A TM0G: Timer 0 gate input P1B0 to P1B3: Port 1B VCOH: Local oscillation high input P1C0 to P1C3: Port 1C VCOL: Local oscillation low input P1D0 to P1D3: Port 1D V DD0, V DD1: Power supply P2A0 to P2A2: Port 2A X IN, X OUT: Main clock oscillation P2B0 to P2B3: Port 2B Data Sheet U15722EJ1V1DS U15722EJ1V1DS 5 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A BLOCK DIAGRAM P0A0 to P0A3 P0B0 to P0B3 VCOH 4 4 PLL RF VCOL EO0 EO1 P0C0 to P0C3 4 P0D0 to P0D3 4 P1A0 to P1A3 4 P1B0 to P1B3 4 RAM 672 × 4 bits ( µPD17704A PD17704A, 17705A) 1120 × 4 bits ( µPD17707A PD17707A, 17708A) 1776 × 4 bits ( µ PD17709A PD17709A) P1C0 to P1C3 4 SYSREG P1D0 to P1D3 4 SO0/P0A0 SCK0/P0A1 Serial interface 0 SCL/P0A2 SDA/P0A3 SI0/P0B3 SCK1/P0B2 Ports P2A0 to P2A2 3 P2B0 to P2B3 4 P2D0 to P2D2 3 SO1/P0B1 SI1/P0B0 ALU 4 P2C0 to P2C3 Serial interface 1 BEEP BEEP0/P1D0 BEEP1/P1D1 P3A0 to P3A3 4 P3D0 to P3D3 INT1 Interrupt control 4 P3C0 to P3C3 INT0 4 P3B0 to P3B3 Instruction decoder 4 INT2 INT3/P1A2 ROM 8192 × 16 bits ( µ PD17704A PD17704A) 12288 × 16 bits ( µ PD17705A PD17705A, 17707A) 16384 × 16 bits ( µ PD17708A PD17708A, 17709A) INT4/P1A3 FCG0/P2A0 Frequency counter FCG1/P2A1 FMIFC/P1C0 AMIFC/P1C1 AD0/P0D0 AD1/P0D1 AD2/P0D2 AD3/P0D3 A/D converter 8-bit timer 0 gate counter Program counter TM0G/P1A0 AD4/P1C2 AD5/P1C3 8-bit timer 1 Stack PWM0/P1B0 PWM1/P1B1 D/A converter 8-bit timer 2 PWM2/P1B2 8-bit timer 3 CPU Peripheral OSC XIN XOUT CE Basic timer Reset RESET VDD0, VDD1 GND0 to GND2 VCPU 6 Data Sheet U15722EJ1V1DS U15722EJ1V1DS Regulator REG µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A CONTENTS 1. PIN FUNCTIONS . 1.1 Pin Function List . 1.2 Equivalent Circuits of Pins . 1.3 Connections of Unused Pins . 1.4 Cautions on Using CE, INT0 to INT4, and RESET Pins . 1.5 Cautions on Using TEST Pin . 11 11 16 21 23 23 2. PROGRAM MEMORY (ROM) . 2.1 Outline of Program Memory . 2.2 Program Memory . 2.3 Program Counter . 2.4 Flow of Program . 2.5 Cautions on Using Program Memory . 24 24 25 26 26 31 3. ADDRESS STACK (ASK) . 3.1 Outline of Address Stack . 3.2 Address Stack Register (ASR) . 3.3 Stack Pointer (SP) . 3.4 Operation of Address Stack . 3.5 Cautions on Using Address Stack . 32 32 32 34 35 36 4. DATA MEMORY (RAM) . 4.1 Outline of Data Memory . 4.2 Configuration and Function of Data Memory . 4.3 Data Memory Addressing . 4.4 Cautions on Using Data Memory . 37 37 40 44 45 5. SYSTEM REGISTERS (SYSREG) . 5.1 Outline of System Registers . 5.2 System Register List . 5.3 Address Register (AR) . 5.4 Window Register (WR) . 5.5 Bank Register (BANK) . 5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) . 5.7 General Register Pointer (RP) . 5.8 Program Status Word (PSWORD) . 46 46 47 48 50 51 52 54 56 6. GENERAL REGISTER (GR) . 6.1 Outline of General Register . 6.2 General Register . 6.3 Generating Address of General Register by Each Instruction . 6.4 Cautions on Using General Register . 58 58 58 59 59 Data Sheet U15722EJ1V1DS U15722EJ1V1DS 7 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 7. ALU (Arithmetic Logic Unit) BLOCK . 7.1 Outline of ALU Block . 7.2 Configuration and Function of Each Block . 7.3 ALU Processing Instruction List . 7.4 Cautions on Using ALU . 60 60 61 61 65 8. REGISTER FILE (RF) . 8.1 Outline of Register File . 8.2 Configuration and Function of Register File . 8.3 Control Registers . 8.4 Port I/O Selection Registers . 8.5 Cautions on Using Register File . 66 66 67 68 80 86 9. DATA BUFFER (DBF) . 9.1 Outline of Data Buffer . 9.2 Data Buffer . 9.3 Relationship Between Peripheral Hardware and Data Buffer . 9.4 Cautions on Using Data Buffer . 87 87 88 89 92 10. DATA BUFFER STACK . 10.1 Outline of Data Buffer Stack . 10.2 Data Buffer Stack Register . 10.3 Data Buffer Stack Pointer . 10.4 Operation of Data Buffer Stack . 10.5 Using Data Buffer Stack . 10.6 Cautions on Using Data Buffer Stack . 93 93 93 95 96 97 97 11. GENERAL-PURPOSE PORTS . 11.1 Outline of General-Purpose Port . 11.2 General-Purpose I/O Ports (P0A, P0B, P0C, P1D, P2A, P2B, P2C, P2D, P3A, P3B, P3C, P3D) . 11.3 General-Purpose Input Port (P0D, P1A, P1C) . 11.4 General-Purpose Output Port (P1B) . 98 98 101 115 118 12. INTERRUPTS . 12.1 Outline of Interrupt Block . 12.2 Interrupt Control Block . 12.3 Interrupt Stack Register . 12.4 Stack Pointer, Address Stack Registers, and Program Counter . 12.5 Interrupt Enable Flip-Flop (INTE) . 12.6 Acknowledging Interrupt . 12.7 Operations After Interrupt Has Been Acknowledged . 12.8 Returning from Interrupt Routine . 12.9 External Interrupts (CE and INT0 to INT4 Pins) . 12.10 Internal Interrupts . 119 119 121 135 139 139 140 145 145 146 149 13. TIMERS . 150 13.1 Outline of Timers . 150 8 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 13.2 13.3 13.4 13.5 13.6 Basic Timer 0 . Timer 0 . Timer 1 . Timer 2 . Timer 3 . 152 165 174 181 188 14. A/D CONVERTER . 14.1 Outline of A/D Converter . 14.2 Input Selection Block . 14.3 Compare Voltage Generation and Compare Blocks . 14.4 Comparison Timing Chart . 14.5 Using A/D Converter . 14.6 Cautions on Using A/D Converter . 14.7 Status After Reset . 195 195 196 198 201 202 203 203 15. D/A CONVERTER (PWM MODE) . 15.1 Outline of D/A Converter . 15.2 PWM Clock Selection Register . 15.3 PWM Output Selection Block . 15.4 Duty Setting Block . 15.5 Clock Generation Block . 15.6 D/A Converter Output Wave . 15.7 Example of Using D/A Converter . 15.8 Status After Reset . 204 204 205 206 209 213 213 216 217 16. SERIAL INTERFACES . 16.1 Outline of Serial Interfaces . 16.2 Serial Interface 0 . 16.3 Serial Interface 1 . 218 218 219 247 17. PLL FREQUENCY SYNTHESIZER . 17.1 Outline of PLL Frequency Synthesizer . 17.2 Input Selection Block and Programmable Divider . 17.3 Reference Frequency Generator . 17.4 Phase Comparator (-DET), Charge Pump, and Unlock FF . 17.5 PLL Disabled Status . 17.6 Using PLL Frequency Synthesizer . 17.7 Status After Reset . 257 257 258 262 264 268 269 273 18. FREQUENCY COUNTER . 18.1 Outline of Frequency Counter . 18.2 I/O Selection Block and Gate Time Control Block . 18.3 Start/Stop Control Block and IF Counter . 18.4 Using IF Counter . 18.5 Using External Gate Counter . 18.6 Status After Reset . 274 274 275 278 285 287 288 Data Sheet U15722EJ1V1DS U15722EJ1V1DS 9 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 19. BEEP . 19.1 Outline of BEEP . 19.2 I/O Selection Block and Output Selection Block . 19.3 Clock Selection Block and Clock Generation Block . 19.4 Output Waveform of BEEP . 19.5 Status After Reset . 289 289 290 292 293 293 20. STANDBY . 20.1 Outline of Standby Function . 20.2 Halt Function . 20.3 Clock Stop Function . 20.4 Device Operation in Halt and Clock Stop Status . 20.5 Cautions on Processing of Each Pin in Halt and Clock Stop Status . 20.6 Device Operation Control Function of CE Pin . 294 294 295 301 303 303 305 21. RESET . 21.1 Outline of Reset . 21.2 CE Reset . 21.3 Power-on Reset . 21.4 Relationship Between CE Reset and Power-on Reset . 21.5 Reset by RESET Pin . 21.6 WDT&SP Reset . 21.7 Power Failure Detection . 308 308 309 315 318 322 323 329 22. INSTRUCTION SET . 22.1 Outline of Instruction Set . 22.2 Legend . 22.3 Instruction List . 22.4 Assembler (RA17K RA17K) Embedded Macro Instruction . 334 334 335 336 338 23. RESERVED SYMBOLS . 23.1 Data Buffer (DBF) . 23.2 System Registers (SYSREG) . 23.3 Port Registers . 23.4 Register File (Control Registers) . 23.5 Peripheral Hardware Registers . 23.6 Others . 339 339 339 340 342 347 347 24. ELECTRICAL CHARACTERISTICS . 348 25. PACKAGE DRAWING . 351 26. RECOMMENDED SOLDERING CONDITIONS . 352 APPENDIX A. CAUTIONS ON CONNECTING CRYSTAL RESONATOR . 353 APPENDIX B. DEVELOPMENT TOOLS . 354 10 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 1. PIN FUNCTIONS 1.1 Pin Function List Pin No. Symbol Function Output Form 1 41 42 INT2 INT1 INT0 Edge-detectable vectored interrupt input pins. Rising or falling edge can be specified. ­ 2 3 4 5 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G Port 1A multiplexed with external interrupt request signal input and event signal input pins. · P1A3 to P1A0 · 4-bit input port · INT4, INT3 · Edge-detectable vectored interrupt · TM0G · Input for gate of 8-bit timer 0 ­ After reset Power-on reset Input (P1A3 to P1A0) 6 | 9 P3A3 | P3A0 WDT&SP reset Input (P1A3 to P1A0) With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 10 P3B3 4-bit I/O port. CMOS | 13 | P3B0 Input or output can be specified in 4-bit units. push-pull After reset Power-on reset Input 14 15 16 P2A2 P2A1/FCG1 P2A0/FCG0 WDT&SP reset Input With clock stopped CE reset Retained Retained Port 2A multiplexed with external gate counter input pins. · P2A2 to P2A0 · 3-bit I/O port · Input or output can be specified in 1-bit units. · FCG1, FCG0 · Input for external gate counter After reset Power-on reset WDT&SP reset Input (P2A2 to P2A0) Input (P2A2 to P2A0) CMOS push-pull With clock stopped CE reset Retained (P2A2 to P2A0) Data Sheet U15722EJ1V1DS U15722EJ1V1DS Retained (P2A2 to P2A0) 11 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol 17 18 | 20 P1B3 P1B2/PWM2 | P1B0/PWM0 Function Output Form Port 1B multiplexed with D/A converter output pins. · P1B3 to P1B0 · 4-bit output port · PWM2 to P2M0 · 8- or 9-bit D/A converter output After reset Power-on reset WDT&SP reset Outputs low level Outputs low level (P1B3 to P1B0) N-ch open-drain (12 V) With clock stopped CE reset (P1B3 to P1B0) Retained Retained (P1B3 to P1B0) 21 33 75 GND2 GND1 GND0 Ground ­ 22 | 25 P0D3/AD3 | P0D0/AD0 Port 0D multiplexed with A/D converter input pins · P0D3 to P0D0 · 4-bit input port · Pull-down resistors can be connected in 1-bit units. · AD3 to AD0 · Analog input of A/D converter with 8-bit resolution ­ After reset Power-on reset Input with pull-down resistor (P0D3 to P0D0) 26 27 28 29 P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC WDT&SP reset Input with pull-down resistor (P0D3 to P0D0) With clock stopped CE reset Retained Retained Port 1C multiplexed with A/D converter input and IF counter input pins. · P1C3 to P1C0 · 4-bit input port · AD5, AD4 · Analog input to A/D converter with 8-bit resolution · FMIFC, AMIFC · Input to frequency counter After reset Power-on reset Input (P1C3 to P1C0) 12 WDT&SP reset Input (P1C3 to P1C0) With clock stopped CE reset · P1C3/AD5, P1C2/AD4 retained · P1C1/AMIFC, P1C0/FMIFC input (P1C1, P1C0) Data Sheet U15722EJ1V1DS U15722EJ1V1DS · P1C3/AD5, P1C2/AD4 retained · P1C1/AMIFC, P1C0/FMIFC input (P1C1, P1C0) ­ µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol Function Output Form 30 79 V DD 1 V DD 0 Power supply. Supply the same voltage to these · With CPU and peripheral function operating: · With CPU operating: · With clock stopped: pins. 4.5 to 5.5 V 3.5 to 5.5 V 2.2 to 5.5 V 31 32 VCOH VCOL PLL local oscillation (VCO) frequency input. · VCOH · Active with VHF mode selected by program; otherwise, pulled down. · VCOL · Active with HF or MW mode selected by program; otherwise, pulled down. ­ ­ Because the input of these pins goes into an AC amplifier, cut the DC component of the input signal with a capacitor. 34 35 EO0 EO1 Output from charge pump of PLL frequency synthesizer. Outputs the divided frequency of local oscillation and the result of comparison of the phase difference of the reference frequency. After reset CMOS 3-state With clock stopped Power-on reset WDT&SP reset CE reset High-impedance output High-impedance output High-impendance output 36 TEST Test input pin. Be sure to connect this pin to GND. 37 38 39 40 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 High-impedance output ­ Port 1D and BEEP output. · P1D3 to P1D0 · 4-bit I/O port · Input or output can be specified in 1-bit units. · BEEP1, BEEP0 CMOS push-pull · BEEP output After reset Power-on reset WDT&SP reset With clock stopped CE reset Input 43 | 46 P2B3 | P2B0 Input Retained Retained (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) 4-bit I/O port. Input or output can be specified in 1-bit units. After reset Power-on reset Input 47 | 50 P3C3 | P3C0 WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Data Sheet U15722EJ1V1DS U15722EJ1V1DS Retained 13 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Pin No. 51 | 54 Symbol P3D3 | P3D0 Function 4-bit I/O port. Input or output can be specified in 4-bit units. Input P2C3 | P2C0 65 66 67 68 69 70 P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 WDT&SP reset Input CE reset Retained WDT&SP reset Input Retained Retained Ports P0A and P0B are multiplexed with I/O of serial interface. · P0A3 to P0A0 · 4-bit I/O port · Input or output can be specified in 1-bit units. · P0B3 to P0B0 · 4-bit I/O port · Input or output can be specified in 1-bit units. · SDA, SCL · Serial data and serial clock I/O of serial interface 0 in 2-wire serial I/O or I 2 C bus mode · SCK0, SO0, SI0 · Serial clock I/O, serial data output, and serial data input of serial interface 0 in 3-wire serial I/O mode · SCK1, SO1, SI1 · Serial clock I/O, serial data output, serial data input of serial interface 1 in 3-wire serial I/O mode N-ch open-drain CMOS push-pull With clock stopped WDT&SP reset CE reset Input P0A3 to P0A0, P0B3 to P0B0 Input P0A3 to P0A0, P0B3 to P0B0 Retained P0A3 to P0A0, P0B3 to P0B0 Retained P0A3 to P0A0, P0B3 to P0B0 3-bit I/O port. Input or output can be specified in 1-bit units. After reset Power-on reset Input 14 CMOS push-pull CE reset Power-on reset P2D2 | P2D0 Retained With clock stopped After reset 71 | 73 CMOS push-pull With clock stopped After reset Input P0A3/DSA P0A2/SCL Retained 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 63 64 Retained After reset Input P0C3 | P0C0 Input CE reset 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 59 | 62 WDT&SP reset CMOS push-pull With clock stopped After reset Power-on reset 55 | 58 Output Form WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Data Sheet U15722EJ1V1DS U15722EJ1V1DS Retained µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol Function Output Form 74 REG CPU regulator. Connect this pin to GND via 0.1 µ F capacitor. ­ 76 77 X OUT X IN Ground pins of crystal resonator. ­ 78 CE Device operation selection, CE reset, and interrupt signal input pin. · Device operation selection When CE is high, the PLL frequency synthesizer can operate. When CE is low, the PLL frequency synthesizer is automatically disabled internally. · CE reset When CE goes high, the device is reset at the rising edge of the internal basic timer setting pulse. This pin also has a reset timing delay function. · Interrupt ­ A vectored interrupt occurs at the falling edge of this pin. 80 RESET Reset input ­ Data Sheet U15722EJ1V1DS U15722EJ1V1DS 15 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 1.2 Equivalent Circuits of Pins (1) P0A (P0A1/SCK0, P0A0/SO0) P0B (P0B3/SI0, P0B2/SCK1, P0B1/SO1, P0B0/SI1) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1/BEEP1, P1D0/BEEP0) P2A (P2A2, P2A1/FCG1, P2A0/FCG0) P2B (P2B3, P2B2, P2B1, P2B0) (I/O) P2C (P2C3, P2C2, P2C1, P2C0) P2D (P2D2, P2D1, P2D0) P3A (P3A3, P3A2, P3A1, P3A0) P3B (P3B3, P3B2, P3B1, P3B0) P3C (P3C3, P3C2, P3C1, P3C0) P3D (P3D3, P3D2, P3D1, P3D0) VDD CKSTOPNote VDD Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. 16 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A (2) P0A (P0A3/SDA, P0A2/SCL) (I/O) VDD CKSTOPNote Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) P1B (P1B3, P1B2/PWM2, P1B1/PWM1, P1B0/PWM0) (output) (4) P0D (P0D3/AD3, P0D2/AD2, P0D1/AD1, P0D0/AD0) (input) A/D converter VDD CKSTOPNote P0DPLD flag High on-resistance Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 17 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A (5) P1A (P1A1) (input) VDD CKSTOPNote Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (6) P1C (P1C3/AD5, P1C2/AD4) (input) VDD A/D converter CKSTOPNote Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (7) P1C (P1C1/AMIFC, P1C0/FMIFC) (input) VDD General-purpose port CKSTOPNote VDD High on-resistance VDD Frequency counter Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. 18 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A (8) CE RESET INT0, INT1, INT2 (Schmitt-triggered input) P1A (P1A3/INT4, P1A2/INT3, P1A0/TM0G) VDD (9) X OUT (output), X IN (input) VDD High on-resistance VDD XIN Internal clock High onresistance XOUT (10) EO1, EO0 (output) VDD DWN UP Data Sheet U15722EJ1V1DS U15722EJ1V1DS 19 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A (11) VCOH, VCOL (input) VDD High on-resistance VDD High onresistance 20 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 1.3 Connections of Unused Pins It is recommended to connect unused pins as follows. Table 1-1. Connections of Unused Pins (1/2) Pin Name Port pin P0D3/AD3 to P0D0/AD0 I/O Mode Recommended Connection Independently connect to GND via a resistorNote 1 . Input P1C3/AD5 P1C2/AD4 P1C1/AMIFC Note 2 Set to port mode and individually connect to V DD or GND P1C0/FMIFC Note 2 via a resistor Note 1 . P1A3/INT4 Independently connect to GND via a resistor Note 1 . P1A2/INT3 P1A1 P1A0/TM0G P1B3 N-ch open-drain P1B2/PWM2 to P1B0/PWM0 output P0A3/SDA I/O Note 3 P0A2/SCL Set to low-level output by software and leave open. Set to general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P0C3 to P0C0 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 P2A2 P2A1/FCG1 P2A0/FCG0 P2B3 to P2B0 P2C3 to P2C0 P2D2 to P2D0 Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 k, although it depends on the application circuit. 2. Do not set these pins as AMIFC and FMIFC pins; otherwise, the current consumption will increase. 3. The I/O ports are set in the general-purpose I/O port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 21 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Table 1-1. Connections of Unused Pins (2/2) Pin Name Port pin P3A3 to P3A0 I/O Mode I/O Note 2 Recommended Connection Set in general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P3B3 to P3B0 P3C3 to P3C0 P3D3 to P3D0 CE Input Connect to V DD via a resistor Note 1. EO1 Output Leave open INT0 to INT2 Input Independently connect to GND via a resistorNote 1 . RESET Non-port pins Input Connect to V DD via a resistor Note 1. EO0 TEST VCOH ­ Input Directly connect to GND. Disable PLL via software and leave open. VCOL Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 k, although it depends on the application circuit. 2. The I/O ports are set in the general-purpose input port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. 22 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 1.4 Cautions on Using CE, INT0 to INT4, and RESET Pins The CE, INT0 to INT4, and RESET pins have a function to set a test mode in which the internal operations of the µ PD17709A PD17709A are tested (IC test), in addition to the functions listed in 1.1 Pin Function List. When a voltage exceeding V DD is applied to any of these pins, the device is set in the test mode. If a noise exceeding V DD is superimposed during normal operation, therefore, the test mode is set by mistake, affecting the normal operation. Especially if the wiring length of pins is too long, noise is superimposed on these pins. In consequence, the above problem occurs. Therefore, keep the wiring length as short as possible to prevent noise from being superimposed. If superimposition of noise is unavoidable, connect an external component as illustrated below to suppress the noise. · Connect a diode with a low V F · Connect a capacitor between the pin and between the pin and V DD . V DD. VDD Diode with low VF VDD VDD VDD CE, INT0 to INT4, RESET CE, INT0 to INT4, RESET 1.5 Cautions on Using TEST Pin When V DD is applied to the TEST pin, the device is set in the test mode. Therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the GND pin. If the wiring length between the TEST pin and GND pin is too long, or if external noise is superimposed on the TEST pin, generating a potential difference between the TEST pin and GND pin, your program may not run normally. GND TEST Short Data Sheet U15722EJ1V1DS U15722EJ1V1DS 23 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 2. PROGRAM MEMORY (ROM) 2.1 Outline of Program Memory Figure 2-1 outlines the program memory. As shown in this figure, the addresses of the program memory are specified by the program counter. The program memory has the following two major functions. · To store programs · To store constant data Figure 2-1. Outline of Program Memory Address specification Program memory . Program counter . . Instruction . Constant data 24 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 2.2 Program Memory Figure 2-2 shows the configuration of the program memory. As shown in this figure, the µ PD17704A PD17704A has 16 KB (8192 × 16 bits) of program memory, the µ PD17705A PD17705A and 17707A have 24 KB (12288 × 16 bits), and the µ PD17708A PD17708A and 17709A have 32 KB (16384 × 16 bits). Therefore, the program memory addresses of the µ PD17704A PD17704A are 0000H 0000H to 1FFFH, those of the µ PD17705A PD17705A, 17707A are 0000H 0000H to 2FFFH, and those of the µ PD17708A PD17708A and 17709A are 0000H 0000H to 3FFFH. Because all instructions are one-word instructions, one instruction can be stored in one address of the program memory. The contents of the program memory are read to the data buffer as constant data by using a table reference instruction. Figure 2-2. Configuration of Program Memory Address 0 0 0 0 H Reset start address 0 0 0 1 H Serial interface 1 interrupt vector 0 0 0 2 H Serial interface 0 interrupt vector 0 0 0 3 H Timer 3 interrupt vector Page 0 0 0 0 4 H Timer 2 interrupt vector 0 0 0 5 H Timer 1 interrupt vector CALL addr instruction subroutine entry address 0 0 0 6 H Timer 0 interrupt vector BR @AR instruction branch address CALL @AR instruction subroutine entry address 0 0 0 7 H INT4 pin interrupt vector 0 0 0 8 H INT3 pin interrupt vector 0 0 0 9 H INT2 pin interrupt vector 0 0 0 A H INT1 pin interrupt vector 0 0 0 B H INT0 pin interrupt vector MOVT DBF, @AR instruction table reference address Segment 0 BR addr instruction branch address 0 0 0 C H Falling edge interrupt vector of CE pin 0 7 FFH Page 1 0 FFFH Page 2 1 7 FFH Page 3 1 FFFH 2000H 2000H ( µ PD17704A PD17704A) Page 0 CALL addr instruction subroutine entry address Page 1 2 FFFH ( µ PD17705A PD17705A, 17707A) Segment 1 BR addr (system instruction segment) branch address Page 2 Page 3 3 FFFH ( µ PD17708A PD17708A, 17709A) 16 bits Data Sheet U15722EJ1V1DS U15722EJ1V1DS 25 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 2.3 Program Counter 2.3.1 Configuration of program counter Figure 2-3 shows the configuration of the program counter. As shown in this figure, the program counter consists of a 13-bit binary counter and a 1-bit segment register (SGR). Bits 11 and 12 of the program counter indicate a page. The program counter specifies an address of the program memory. Figure 2-3. Configuration of Program Counter SGRNote PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Page PC Note This bit is fixed to 0 in the µ PD17704A PD17704A. 2.3.2 Segment register (SGR) The segment register specifies a segment of the program memory. Table 2-1 shows the relationship between the segment register and program memory. The segment register is set only when the SYSCAL entry instruction is executed. Remark The segment register is not available in the µ PD17704A PD17704A. Table 2-1. Relationship Between Segment Register and Program Memory Value of Segment Register Segment of Program Memory 0 Segment 0 1 Segment 1 2.4 Flow of Program The flow of the program is controlled by the program counter, which specifies an address of the program memory. The program flow when each instruction is executed is described below. Figure 2-5 shows the value that is set to the program counter when each instruction is executed. Table 2-2 shows the vector address when an interrupt is acknowledged. 2.4.1 Branch instruction (1) Direct branch ("BR addr") The branch destination address of the direct branch instruction is in the same segment of the program memory. In other words, a branch exceeding a segment cannot be executed. (2) Indirect branch ("BR @AR") The branch destination addresses of the indirect branch instruction are all the addresses of the program memory, i.e., addresses 0000H 0000H to 1FFFH for the µ PD17704A PD17704A, addresses 0000H 0000H to 2FFFH for the µ PD17705A PD17705A, 17707A, and 0000H 0000H to 3FFFH for the µ PD17708A PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR). 26 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 2.4.2 Subroutine (1) Direct subroutine call ("CALL addr") The first address of a subroutine that can be called by the direct subroutine instruction is in page 0 of each segment (addresses 0000H 0000H to 07FFH 07FFH). (2) Indirect subroutine call (CALL @AR) The first addresses of a subroutine that can be called by the indirect subroutine call instruction are all the addresses of the program memory, i.e., addresses 0000H 0000H to 1FFFH for the µ PD17704A PD17704A, addresses 0000H 0000H to 2FFFH for the µ PD17705A PD17705A, 17707A, and 0000H 0000H to 3FFFH for the µ PD17708A PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR). 2.4.3 Table reference The addresses that can be referenced by the table reference instruction ("MOVT DBF, @AR") are all the addresses of the program memory, i.e., addresses 0000H 0000H to 1FFFH for the µ PD17704A PD17704A, addresses 0000H 0000H to 2FFFH for the µ PD17705A PD17705A, 17707A, and 0000H 0000H to 3FFFH for the µ PD17708A PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR) and 9.2.2 Table reference instruction (MOVT, DBF, @AR). 2.4.4 System call The first address of a subroutine that can be called by the system call instruction ("SYSCAL entry") is the first 16 steps of each block (blocks 0 to 7) in page 0 of segment 1 (system segment). Remark The system call instruction is not available in the µ PD17704A PD17704A. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 27 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 2-4. Outline of System Call Instruction Segment 1 (system segment) Segment 0 00000H 00000H Block 0 of segment 1 02000H 02000H 02000H 02000H Block 0 0 2 0FFH 02100H 02100H 0 2 0 0FH Block 1 0 2 1FFH 02200H 02200H Block 2 Page 0 (16 bits × 2K steps) 0 2 2FFH Area where entry address of system segment can be specified . . . . 02700H 02700H Block 7 0 0 7FFH 00800H 00800H 0 2 7FFH 02800H 02800H Page 1 0 0FFFH 01000H 01000H Page 1 0 2FFFH 03000H 03000H Page 2 0 1 7FFH 01800H 01800H Page 2 0 3 7FFH 03800H 03800H Page 3 0 1FFFH 0 3FFFH (16 bits × 8K steps) 28 Page 3 (16 bits × 8K steps) Data Sheet U15722EJ1V1DS U15722EJ1V1DS Entry address of SYSCAL instruction µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 2-5. Value of Program Counter Upon Execution of Instruction Program counter Instruction Contents of program counter (PC) SGR b12 Page 0 BR addr b11 1 0 0 0 0 b6 b5 b4 b3 b2 b1 b0 1 Retained Operand of instruction (addr) Page 3 CALL addr b7 0 1 b8 1 1 Page 2 0 b9 0 Retained Page 1 0 b10 Operand of instruction (addr) SYSCAL entry 0 entryH 0 0 0 entryL BR @AR CALL @AR Contents of address register MOVT DBF, @AR RET RETSK Contents of address stack register (ASR) (return address) specified by stack pointer (SP) RETI Other instructions Increment 0 (including skip instruction) Retained Vector address of each interrupt When interrupt is acknowledged Power-on reset, watchdog timer reset, 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET pin, CE reset entryH: Higher 3 bits of entry entryL: Lower 4 bits of entry Remark The segment register and system call instruction are not available in the µ PD17704A PD17704A. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 29 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Table 2-2. Interrupt Vector Address Order Internal/External Interrupt Source Vector Address 1 Falling edge of CE pin 00CH 2 External INT0 pin 00BH 3 External INT1 pin 00AH 4 External INT2 pin 009H 5 External INT3 pin 008H 6 External INT4 pin 007H 7 Internal Timer 0 006H 8 Internal Timer 1 005H 9 Internal Timer 2 004H 10 Internal Timer 3 003H 11 Internal Serial interface 0 002H 12 30 External Internal Serial interface 1 001H Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 2.5 Cautions on Using Program Memory 2.5.1 Last address in each segment The segment register is not connected to the binary counter. Therefore, address 0000H 0000H of segment 0 is specified next to address 1FFFH, which is the last address of segment 0. To specify between segments, a dedicated instruction such as an indirect branch, indirect subroutine call, or system call instruction is used. Remark The segment register and system call instruction are not available in the µ PD17704A PD17704A. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 31 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 3. ADDRESS STACK (ASK) 3.1 Outline of Address Stack Figure 3-1 outlines the address stack. The address stack consists of a stack pointer and address stack registers. The address of an address stack register is specified by the stack pointer. The address stack saves a return address when a subroutine call instruction is executed or when an interrupt is acknowledged. The address stack is also used when the table reference instruction is executed. Figure 3-1. Outline of Address Stack Stack pointer Address stack register Address specification Return address 3.2 Address Stack Register (ASR) Figure 3-2 shows the configuration of the address stack register. The address stack register consists of sixteen 16-bit registers ASR0 to ASR15 ASR15. Actually, however, it consists of fifteen 16-bit registers (ASR0 to ASR14 ASR14) because no register is allocated to ASR15 ASR15. The address stack saves a return address when a subroutine is called, when an interrupt is acknowledged, and when the table reference instruction is executed. 32 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 3-2. Configuration of Address Stack Register Address stack register (ASR) Stack pointer (SP) Bit b3 b2 Address b1 SP3 SP2 SP1 SP0 Bit b15 b14 b13 b12 b11 b10 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0H ASR0 1H ASR1 2H ASR2 3H ASR3 4H ASR4 5H ASR5 6H ASR6 7H ASR7 8H ASR8 9H ASR9 AH ASR10 ASR10 BH ASR11 ASR11 CH ASR12 ASR12 DH ASR13 ASR13 EH ASR14 ASR14 FH ASR15 ASR15 (Undefined) Data Sheet U15722EJ1V1DS U15722EJ1V1DS Cannot be used 33 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 3.3 Stack Pointer (SP) 3.3.1 Configuration and function of stack pointer Figure 3-3 shows the configuration and functions of the stack pointer. The stack pointer consists of a 4-bit binary counter. It specifies the address of an address stack register. A value can be directly read from or written to the stack pointer by using a register manipulation instruction. Figure 3-3. Configuration and Function of Stack Pointer Name Flag symbol Address Read/write 01H R/W b3 b2 b1 b0 Stack pointer ( ( ( ( (SP) S S S S P P P P 3 2 1 0 ( ( ( ( Specifies address of address stack register (ASR) 0 0 0 Address 0 (ASR0) 0 0 0 1 Address 1 (ASR1) 0 0 1 0 Address 2 (ASR2) 0 0 1 1 Address 3 (ASR3) 0 1 0 0 Address 4 (ASR4) 0 1 0 1 Address 5 (ASR5) 0 1 1 0 Address 6 (ASR6) 0 1 1 1 Address 7 (ASR7) 1 0 0 0 Address 8 (ASR8) 1 0 0 1 Address 9 (ASR9) 1 0 1 0 Address 10 (ASR10 ASR10) 1 0 1 1 Address 11 (ASR11 ASR11) 1 1 0 0 Address 12 (ASR12 ASR12) 1 1 0 1 Address 13 (ASR13 ASR13) 1 1 1 0 Address 14 (ASR14 ASR14) 1 After reset 0 1 1 1 Setting prohibited Power-on reset 1 1 1 1 WDT&SP reset 1 1 1 1 CE reset 1 1 1 1 Clock stop Retained Power-on reset: Reset by RESET pin up on power application WDT&SP reset: Reset by watchdog timer and stack pointer CE reset: Clock stop: 34 CE reset Upon execution of clock stop instruction Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 3.4 Operation of Address Stack 3.4.1 Subroutine call instruction ("CALL addr", "CALL @AR") and return instruction ("RET", "RETSK") When a subroutine call instruction is executed, the value of the stack pointer is decremented by one, and the return address is stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 Table reference instruction ("MOVT DBF, @AR") When the table reference instruction is executed, the value of the stack pointer is incremented by one, and the return address is stored in the address stack register specified by the stack pointer. Next, the contents of the program memory specified by the address register are read to the data buffer, the contents of the address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.3 When interrupt is acknowledged and on execution of return instruction ("RETI") When an interrupt is acknowledged, the value of the stack pointer is decremented by one, and the return address is stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.4 Address stack manipulation instruction ("PUSH AR", "POP AR") When the "PUSH" instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to the address stack register specified by the stack pointer. When the "POP" instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. 3.4.5 System call instruction ("SYSCAL entry") and return instruction ("RET", "RETSK") When the "SYSCAL entry" instruction is executed, the value of the stack pointer is decremented by one, and the return address and the value of the segment register are stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter and segment register, and the value of the stack pointer is incremented by one. Remark The segment register and system call instruction are not available in the µ PD17704A PD17704A. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 35 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 3.5 Cautions on Using Address Stack 3.5.1 Nesting level and operation on overflow The value of address stack register (ASR15 ASR15) is undefined when the value of the stack pointer is 0FH. Accordingly, if a subroutine call or system call exceeding 15 levels or an interrupt is used without manipulating the stack, execution returns to an undefined address. 3.5.2 Reset on detection of overflow or underflow of address stack Whether the device is reset on detection of overflow or underflow of the address stack can be specified by program. After reset, the program is started from address 0, and some control registers are initialized. This reset function is valid after power-on reset or reset by the RESET pin. For details, refer to 21. RESET. 36 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 4. DATA MEMORY (RAM) 4.1 Outline of Data Memory Figure 4-1 outlines the data memory. As shown in the figure, system registers, a data buffer, port registers, and port I/O selection registers are located on the data memory. The data memory stores data, transfers data with the peripheral hardware or ports, and controls the CPU. Figure 4-1. Outline of Data Memory (1/3) (a) µ PD17709A PD17709A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C 0 D E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 . . . BANK14 BANK14 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 37 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-1. Outline of Data Memory (2/3) (b) µ PD17707A PD17707A, 17708A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C D 0 E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 . . . BANK9 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Cautions 1. The µ PD17707A PD17707A and 17708A do not have BANKs 10 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15 BANK15. 38 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-1. Outline of Data Memory (3/3) (c) µ PD17704A PD17704A, 17705A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C 0 D E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 BANK5 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Cautions 1. The µ PD17704A PD17704A and 17705A do not have BANKs 6 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15 BANK15. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 39 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 4.2 Configuration and Function of Data Memory Figure 4-2 shows the configuration of the data memory. As shown in this figure, the data memory is divided into several banks with each bank made up of a total of 128 nibbles with 7H row addresses and 0FH column addresses. The data memory can be divided into five functional blocks. Each block is described in 4.2.1 through 4.2.5 below. The contents of the data memory can be operated on, compared, judged, and transferred in 4-bit units with a single data memory manipulation instruction. Table 4-1 lists the data memory manipulation instructions. 4.2.1 System registers (SYSREG) The system registers are allocated to addresses 74H to 7FH. Because the system registers are allocated to all banks, the same system registers exist at addresses 74H to 7FH of any bank. For details, refer to 5. SYSTEM REGISTER (SYSREG). 4.2.2 Data buffer (DBF) The data buffer is allocated to addresses 0CH to 0FH of BANK 0. For details, refer to 9. DATA BUFFER (DBF). 4.2.3 Port registers The port registers are allocated to addresses 70H to 73H of BANKs 0 to 3. For details, refer to 11. GENERAL-PURPOSE PORTS. 4.2.4 Port I/O selection registers Port I/O selection registers are allocated to addresses 60H to 6FH of BANK15 BANK15. For details, refer to 8.4 Port I/O Selection Register. 4.2.5 General-purpose data memory The general-purpose data memory is allocated to the addresses of the data memory excluding those of the system registers, port registers, and port I/O selection registers. (a) µ PD17709A PD17709A The general-purpose data memory of the µ PD17709A PD17709A consists of a total of 1776 nibbles of the 112 nibbles each of BANKs 0 to 15 (BANK15 BANK15 only has 96 nibbles). (b) µ PD17707A PD17707A, 17708A The general-purpose data memory of the µPD17707A PD17707A and 17708A consists of a total of 1120 nibbles of the 112 nibbles each of BANKs 0 to 9. (c) µ PD17704A PD17704A, 17705A The general-purpose data memory of the µ PD17704A PD17704A and 17705A consists of a total of 672 nibbles of the 112 nibbles each of BANKs 0 to 5. 40 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (1/3) (a) µ PD17709A PD17709A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Data buffer Row address 1 Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 . 6 7 Port register BANK14 BANK14 BANK15 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4 to BANK14 BANK14 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 Row address 0 1 2 3 4 5 6 7 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F 2 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 41 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (2/3) (b) µ PD17707A PD17707A, 17708A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 0 Data buffer 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 . 6 7 Port register BANK9 BANK15 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4 to BANK9 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Nothing is allocated 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Cautions 1. The µ PD17707A PD17707A and 17708A do not have BANKs 10 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15 BANK15. 42 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (3/3) (c) µ PD17704A PD17704A, 17705A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 0 Data buffer 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 . 6 7 Port register BANK5 BANK15 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4, BANK5 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Nothing is allocated 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Cautions 1. The µ PD17704A PD17704A and 17705A do not have BANKs 6 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15 BANK15. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 43 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A Table 4-1. Data Memory Manipulation Instructions Function Operation Instruction Add ADD ADDC Subtract SUB SUBC Logic AND OR XOR Compare SKE SKGE SKLT SKNE Transfer MOV LD ST Judge SKT SKF 4.3 Data Memory Addressing Figure 4-3 shows address specification of the data memory. An address of the data memory is specified by a bank, row address, and column address. A row address and a column address are directly specified by a data memory manipulation instruction. However, a bank is specified by the contents of a bank register. For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Address Specification of Data Memory Bank b3 b2 b1 Row address b0 b2 b1 b0 Column address b3 b2 Data memory address Bank register 44 Data Sheet U15722EJ1V1DS U15722EJ1V1DS Instruction operand b1 b0 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 4.4 Cautions on Using Data Memory 4.4.1 After power-on reset The contents of the general-purpose data memory are undefined after power-on reset. Initialize the data memory as necessary. 4.4.2 Cautions on data memory not provided If a data memory manipulation instruction that reads the data memory is executed to a data memory address that is not provided, undefined data is read. Nothing is changed even if data is written to such an address. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 45 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5. SYSTEM REGISTERS (SYSREG) 5.1 Outline of System Registers Figure 5-1 shows the location of the system registers on the data memory and their outline. As shown in the figure, the system registers are allocated to addresses 74H to 7FH of all the banks of the data memory. Therefore, identical system registers exist at addresses 74H to 7FH of any bank. Because the system registers are located on the data memory, they can be manipulated by all data memory manipulation instructions. Seven types of system registers are available classified by function. Figure 5-1. Location and Outline of System Registers on Data Memory Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Data memory 3 4 5 6 BANK0 7 BANK1 BANK2 . . BANK14 BANK14 BANK15 BANK15 System register Remark The µPD17704A PD17704A and 17705A do not have BANK 6 to 14. The µPD17707A PD17707A and 17708A do not have BANK 10 to 14. Address Name 74H 75H 76H 77H 78H 79H 7AH 7BH 7DH 7EH 7FH Address register Window Bank (AR) register register (IX) (WR) (BANK) Data memory row word address pointer (MP) Function (PSWORD) General register Program pointer (RP) status Transfers Specifies Modifies address of data memory Specifies Controls data with bank of address of operation register data general register file 46 Controls program memory address Index register 7CH memory Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.2 System Register List Figure 5-2 shows the configurations of the system registers. Figure 5-2. Configuration of System Registers Address 74H 75H 76H 77H 78H Name 79H 7AH 7BH 7CH 7DH 7EH 7FH System registers Address register Window Bank Index register (AR) register register (WR) General register Program (BANK) Data memory row (IX) pointer (RP) status word (PSWORD) address pointer (MP) Symbol Data AR2 AR1 AR0 WR IXH BANK IXM MPH Bit AR3 IXL RPH RPL PSW MPL b3 b 2 b1 b 0 b 3 b2 b 1 b0 b 3 b2 b 1 b0 b 3 b2 b 1 b0 b3 b2 b 1 b 0 b3 b 2 b1 b 0 b3 b 2 b1 b 0 b 3 b2 b 1 b0 b3 b2 b 1 b 0 b3 b2 b1 b0 b3 b 2 b1 b 0 b 3 b 2 b1 b 0 M (RP) P 0 E Data Sheet U15722EJ1V1DS U15722EJ1V1DS B C C Z I (IX) (MP) CMY X D P E 47 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.3 Address Register (AR) 5.3.1 Configuration of address register Figure 5-3 shows the configuration of the address register. As shown in the figure, the address register consists of 16 bits at system register addresses 74H to 77H (AR3 to AR0). Figure 5-3. Configuration of Address Register Address 74H 75H Name 76H 77H Address register (AR) Symbol AR3 Data b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 AR0 b0 b3 b2 b1 b0 b3 AR1 Bit AR2 M L S S B B After reset Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 Retained Retained Retained Retained Clock stop Power-on reset: WDT&SP reset: Reset by watchdog timer and stack pointer CE reset: CE reset Clock stop: 48 Reset by RESET pin on power application On execution of clock stop instruction Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.3.2 Function of address register The address register specifies a program memory address when the table reference instruction ("MOVT DBF, @AR"), stack manipulation instruction ("PUSH AR", "POP AR"), indirect branch instruction ("BR @AR"), or indirect subroutine call instruction ("CALL @AR") is executed. A dedicated instruction ("INC AR") is available that can increment the contents of the address instruction by one. The following paragraphs (1) through (5) describe the operation of the address register when the respective instructions are executed. (1) Table reference instruction ("MOVT DBF, @AR") When the table reference instruction is executed, the constant data (16 bits) of a program memory address specified by the contents of the address register are read to the data buffer. The constant data that can be specified by the address register is stored to address 0000H 0000H to 1FFFH in the case of µ PD17704A PD17704A, address 0000H 0000H to 2FFFH in the case of the µ PD17705A PD17705A and 17707A, and address 0000H 0000H to 3FFFH in the case of the µ PD17708A PD17708A and 17709A. (2) Stack manipulation instruction ("PUSH AR", "POP AR") When the "PUSH AR" instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register (AR) are transferred to an address stack register specified by the stack pointer whose value has been decremented by one. When the "POP AR" instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. (3) Indirect branch instruction ("BR @AR") When this instruction is executed, the program branches to a program memory address specified by the contents of the address register. The branch address that can be specified by the address register is 0000H 0000H to 1FFFH in the case of µ PD17704A PD17704A, 0000H 0000H to 2FFFH in the case of the µ PD17705A PD17705A and 17707A, and 0000H 0000H to 3FFFH in the case of the µ PD17705A PD17705A and 17708A and 17709A. (4) Indirect subroutine call instruction ("CALL @AR") The subroutine at a program memory address specified by the contents of the address register can be called. The first address of the subroutine that can be specified by the address register is 0000H 0000H to 1FFFH in the case of the µ PD17704A PD17704A, 0000H 0000H to 2FFFH in the case of the µ PD17705A PD17705A and 17707A, and 0000H 0000H to 3FFFH in the case of the µ PD17708A PD17708A and 17709A. (5) Address register increment instruction ("INC AR") This instruction increments the contents of the address register by one. 5.3.3 Address register and data buffer The address register can transfer data as part of the peripheral hardware via the data buffer. For details, refer to 9. DATA BUFFER (DBF). Data Sheet U15722EJ1V1DS U15722EJ1V1DS 49 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.3.4 Cautions on using address register Because the address register is configured in 16 bits, it can specify an address up to FFFFH. However, the program memory exists at addresses 0000H 0000H to 1FFFH in the case of µ PD17704A PD17704A, 0000H 0000H to 2FFFH in the case of the µ PD17705A PD17705A and 17707A and 0000H 0000H to 3FFFH in the case of the µ PD17708A PD17708A and 17709A. Therefore, the maximum value that can be set to the address register of the µ PD17704 PD17704 is address 1FFFH. In the case of the µ PD17705A PD17705A and 17707A, it is address 2FFFH. In the case of the µ PD17708A PD17708A and 17709A, it is address 3FFFH. 5.4 Window Register (WR) 5.4.1 Configuration of window register Figure 5-4 shows the configuration of the window register. As shown in the figure, the window register consists of 4 bits at system register address 78H (WR). Figure 5-4. Configuration of Window Register Address 78H Name Window register (WR) Symbol WR Data b2 b1 b0 b3 Bit M L S S B B After reset Power-on reset Undefined WDT&SP reset Retained CE reset Clock stop 5.4.2 Function of window register The window register is used to transfer data with the register file (RF) to be described later. Data transfer between the window register and register file is manipulated by using dedicated instructions "PEEK WR, rf" and "POKE, rf WR" (rf: address of register file). The following paragraphs (1) and (2) describe the operation of the window register when these instructions are executed. For further information, also refer to 8. REGISTER FILE (RF). (1) "PEEK WR, rf" instruction When this instruction is executed, the contents of the register file addressed by "rf" are transferred to the window register. (2) "POKE rf, WR" instruction When this instruction is executed, the contents of the window register are transferred to the register file addressed by "rf". 50 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.5 Bank Register (BANK) 5.5.1 Configuration of bank register Figure 5-5 shows the configuration of the bank register. As shown in the figure, the bank register consists of 4 bits at system register address 79H (BANK). Figure 5-5. Configuration of Bank Register Address 79H Name Bank register (BANK) Symbol BANK b0 Data b1 Bit b2 b3 M L S S B B After reset Power-on reset 0 WDT&SP reset 0 CE reset 0 Clock stop Retained 5.5.2 Function of bank register The bank register specifies a bank of the data memory. Table 5-1 shows the relationships between the value of the bank register and a bank of the data memory that is specified. Because the bank register is one of the system registers, its contents can be rewritten regardless of the bank currently specified. When manipulating a bank register, therefore, the status of the bank at that time is irrelevant. Table 5-1. Data Memory Bank Specification Bank Register Bank of Data (BANK) Memory b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 Bank Register Bank of Data (BANK) Memory b3 b2 b1 b0 BANK0 1 0 0 0 BANK8Note 1 BANK1 1 0 0 1 BANK9Note 1 0 BANK2 1 0 1 0 BANK10Note 0 1 1 BANK3 1 0 1 1 BANK11Note 0 1 0 0 BANK4 1 1 0 0 BANK12Note 0 1 0 1 BANK5 1 1 0 1 BANK13Note 0 1 1 0 BANK6Note 1 1 1 0 BANK14Note 1 Note 1 1 1 1 BANK15 BANK15 0 1 1 BANK7 Note Do not set BANKs 6 to 14 in the µ PD17704A PD17704A and 17705A, and BANKs 10 to 14 in the µ PD17707A PD17707A and 17708A because these banks are not provided. Caution The area to which the data memory is allocated varies depending on the model. For details, refer to Figure 4-2 Configuration of Data Memory. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 51 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) 5.6.1 Configuration of index register and data memory row address pointer Figure 5-6 shows the configuration of the index register and data memory row address pointer. As shown in the figure, the index register consists of an index register (IX) made up of 11 bits (the lower 3 bits (IXH) at system register address 7AH, 7BH, and 7CH (IXM, IXL) and an index enable flag (IXE) at the least significant bit position of 7FH (PSW). The data memory row address pointer (memory pointer) consists of a data memory row address pointer (MP) that is made up of 7 bits of the lower 3 bits at 7AH (MPH) and 7BH (MPL), and a data memory row address pointer enable flag (memory pointer enable flag: MPE) at the most significant bit position of 7AH (MPH). In other words, the higher 7 bits of the index register are shared with the data memory row address pointer. Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer Address 7BH 7AH 7EH 7CH Index register (IX) Name Program status word (PSWORD) Memory pointer (MP) IXH MPH b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Data PSW IXL IXM Symbol Bit 7FH M M L I P S S X E B B E IX M L S S B B After reset MP Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 Retained Retained Retained R Clock stop R: Retained 52 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.6.2 Functions of index register and data memory row address pointer The index register and data memory row address pointer modify the addresses of the data memory. The following paragraphs (1) and (2) describe their functions. A dedicated instruction ("INC IX") that increments the value of the index register by one is available. For details of address modification, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. (1) Index register (IX) When a data memory manipulation instruction is executed, the data memory address is modified by the contents of the index register. This modification, however, is valid only when the IXE flag is set to 1. To modify the address, the bank, row address, and column address of the data memory are ORed with the contents of the index register, and the instruction is executed to a data memory address (called real address) specified by the result of this OR operation. All data memory manipulation instructions are subject to address modification by the index register. The following instructions, however, are not subject to address modification by the index register. INC AR RORC r INX IX CALL addr MOVT DBF, @AR CALL @AR PUSH AR RET POP AR RETSK PEEK WR,rf RETI POKE rf,WR EI GET DBF,p DI PUT p, DBF STOP s BR addr HALT h BR @AR NOP (2) Data memory row address pointer (MP) When the general register indirect transfer instruction ("MOV @r,m" or "MOV m,@r") is executed, the indirect transfer destination address is modified. This modification, however, is valid only when the MPE flag is set to 1. To modify the address, the bank and row address at the indirect transfer destination are replaced by the contents of the data memory row address pointer. Instructions other than the general register indirect transfer instruction are not subject to address modification. (3) Index register increment instruction ("INC IX") This instruction increments the contents of the index register by one. Because the index register is configured of 10 bits, its contents are incremented to 000H if the "INC IX" instruction is executed when the contents of the index register are 3FFH. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 53 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.7 General Register Pointer (RP) 5.7.1 Configuration of General Register Pointer Figure 5-7 shows the configuration of the general register pointer. As shown in the figure, the general register pointer consists of 7 bits including 4 bits at system register address 7DH (RPH) and the higher 3 bits at address 7EH (RPL). Figure 5-7. Configuration of General Register Pointer 7DH Address Name 7EH General register pointer (RP) RPH Symbol b1 b0 b3 b1 b2 b0 L B S S C B B D After reset M Data b2 b3 Bit RPL Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 Retained Retained Clock stop 54 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.7.2 Function of general register pointer The general register pointer specifies a general register on the data memory. Figure 5-8 shows the addresses of the general registers specified by the general register pointer. As shown in the figure, a bank is specified by the higher 4 bits (RPH: address 7DH) of the general register pointer, and a row address is specified by the lower 3 bits (RPL: address 7EH). Because the valid number of bits of the general register pointer is 7, all the row addresses (0H to 7FH) of all the banks can be specified as general registers. For details of the operation of the general register, refer to 6. GENERAL REGISTER (GR). Figure 5-8. Address of General Register Specified by General Register Pointer General register pointer (RP) b3 b2 M S B L S B B C D b0 b0 b1 b1 b3 b2 RPL RPH Specifies row address of each bank Specifies bank Bank Row address 0 0 0 0 0 0 0H 0 0 0 0 0 0 1 1H 0 0 0 0 0 1 0 0 0 0 0 0 1 1 3H 1 1 1 1 1 0 0 4H 1 1 1 1 1 0 1 1 1 1 1 1 1 0 6H 1 Remark 0 1 1 1 1 1 1 7H BANK0 BANK15 BANK15 2H 5H The µ PD17704A PD17704A and 17705A do not have BANKs 6 to 14. The µ PD17707A PD17707A and 17708A do not have BANKs 10 to 14. Caution The area to which the data memory is allocated varies depending on the model. For details, refer to Figure 4-2 Configuration of Data Memory. 5.7.3 Cautions on using general register pointer The least significant bit at address 7EH (RPL) of the general register pointer is allocated as the BCD flag of the program status word. When rewriting RPL, therefore, pay attention to the value of the BCD flag. Data Sheet U15722EJ1V1DS U15722EJ1V1DS 55 µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.8 Program Status Word (PSWORD) 5.8.1 Configuration of program status word Figure 5-9 shows the configuration of the program status word. As shown in the figure, the program status word consists of a total of 5 bits including the least significant bit at system register address 7EH (RPL) and 4 bits at address 7FH (PSW). Each bit of the program status word has its own function. The 5 bits of the program status word are BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Figure 5-9. Configuration of Program Status Word 7EH Address Name 7FH Program status word (PSWORD) RPL Symbol Bit b3 b2 b1 PSW b1 b0 C C Z I M Y D After reset b2 C P X E Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 Retained Retained Clock stop 56 b3 B Data b0 Data Sheet U15722EJ1V1DS U15722EJ1V1DS µPD17704A PD17704A, 17705A, 17707A, 17708A, 17709A 5.8.2 Function of program status word The program status word is a register that sets the conditions under which the ALU (Arithmetic Logic Unit) executes an operation or data transfer, or indicates the result of an operation. Table 5-2 outlines the function of each flag of the program status word. For details, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. Table 5-2. Outline of Function of Each Flag of Program Status Word (RP) Program Status Word (PSWORD) RPL b1 b0 b3 b2 b1 b0 B C C Z I C M Y D b3 b2 PSW P X E Flag Name Function Index enable flag Modifies address of data memory when data memory (IXE) manipulation instruction is executed. 0: Does not modify 1: Mod