PD17215 PD17P218 PD172 IEU-1317 PD17217 PD17218 PD17216 U12042EJ3V0DS00 AS17K - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD17215, 17216, 17217, 17218 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD17215 PD17215, 17216, 17217, 17218 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER DESCRIPTION µPD17215 PD17215, 17216, 17217, 17218 (hereafter called µPD17215 PD17215 subseries) are 4-bit single-chip microcontrollers for small general-purpose infrared remote control transmitters. It employs a 17K architecture of general-purpose register type devices for the CPU, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. Moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. In addition, a one-time PROM model, µPD17P218 PD17P218, to which data can be written only once, is also available. It is convenient either for evaluating the µPD17215 PD17215 subseries programs or small-scale production of application systems. Detailed functions are described in the follwing manual. Be sure to read this manual when designing your system. µPD172 PD172×× Subseries User's Manual: IEU-1317 IEU-1317 FEATURES · Infrared remote controller carrier generator circuit (REM output) · 17K architecture: General-purpose register system · Program memory (ROM), Data memory (RAM) µPD17215 PD17215 µPD17217 PD17217 µPD17218 PD17218 4 K bytes 8 K bytes 12 K bytes 16 K bytes (2048 × 16) Program memory (ROM) µPD17216 PD17216 (4096 × 16) (6144 × 16) (8192 × 16) 111 × 4 bits Data memory (RAM) · 8-bit timer : 223 × 4 bits 1 channel · Basic internal timer / Watchdog timer: 1 channel (WDOUT output) · Instruction execution time (can be changed in two steps) at fX 4 MHz : 4 µs (high-speed mode)/8 µs (ordinary mode) at fX 8 MHz : 2 µs (high-speed mode)/4 µs (ordinary mode) · External interrupt pin (INT) : 1 · I/O pins : 20 · Supply voltage : VDD = 2.2 to 5.5 V (at fX = 4 MHz (high-speed mode) VDD = 2.0 to 5.5 V (at fX = 4 MHz (ordinary mode) · Low-voltage detector circuit (mask opation) Unless otherwise specified, the µPD17215 PD17215 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Document No. U12042EJ3V0DS00 U12042EJ3V0DS00 (3rd edition) (Previous No. IC­3249) Date Published January 1997 N Printed in Japan The mark shows major revised points. © 1993 µPD17215 PD17215, 17216, 17217, 17218 APPLICATION Preset remote controllers, toys, portable systems, etc. ORDERING INFORMATION Part Number Package µPD17215CT-xxx 28-pin plastic shrink DIP (400 mil) µPD17215GT-xxx 28-pin plastic SOP (375 mil) µPD17216CT-xxx 28-pin plastic shrink DIP (400 mil) µPD17216GT-xxx 28-pin plastic SOP (375 mil) µPD17217CT-xxx 28-pin plastic shrink DIP (400 mil) µPD17217GT-xxx 28-pin plastic SOP (375 mil) µPD17218CT-xxx 28-pin plastic shrink DIP (400 mil) µPD17218GT-xxx 28-pin plastic SOP (375 mil) Remark: xxx is ROM code number. 2 µPD17215 PD17215, 17216, 17217, 17218 PIN CONFIGURATION (TOP VIEW) · 28-pin plastic SOP (375 mil) µPD17215GT-xxx, 17216GT-xxx, 17217GT-xxx, 17218GT-xxx · 28-pin plastic shrink DIP (400 mil) µPD17215CT-xxx, 17216CT-xxx, 17217CT-xxx, 17218CT-xxx P0D 2 1 28 P0D 1 P0D 3 2 27 P0D 0 INT 3 26 P0C 3 P0E 0 4 25 P0C 2 P0E 1 5 24 P0C 1 P0E 2 6 23 P0C 0 P0E 3 7 22 P0B 3 REM 8 21 P0B 2 V DD 9 20 P0B 1 X OUT 10 19 P0B 0 X IN 11 18 P0A 3 GND 12 17 P0A 2 RESET 13 16 P0A 1 WDOUT 14 15 P0A 0 GND : Ground INT : External interrupt request signal input P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input port (CMOS input) P0C0-P0C3 : Output port (N-ch open-drain output) P0D0-P0D3 : Output port (N-ch open-drain output) P0E0-P0E3 : I/O port (CMOS push-pull output) REM : Remote controller output (CMOS push-pull output) RESET : Reset input VDD : Power supply WDOUT : Hang-up/low voltage detection output (N-ch open-drain output) XIN, XOUT : Oscillator connection 3 µPD17215 PD17215, 17216, 17217, 17218 BLOCK DIAGRAM P0A 0 P0A 1 P0A 2 P0A Remote Control Divider RF REM P0A 3 ROM µ PD17215 PD17215, 17216 : 111 × 4 bits µ PD17217 PD17217, 17218 : 223 × 4 bits P0B 0 P0B 1 P0B 2 P0B 3 8-bit Timer SYSTEM REG. P0B Interrupt Controller INT ALU P0C 0 P0C 1 P0C 2 P0C 3 P0D 0 P0D 1 P0D 2 P0D 3 P0C ROM µ PD17215 PD17215 : 2048 µ PD17216 PD17216 : 4096 µ PD17217 PD17217 : 6144 µ PD17218 PD17218 : 8192 × × × × 16 bits 16 bits 16 bits 16 bits Instruction Decoder RESET P0D WDOUT Program Counter P0E 0 P0E 1 P0E 2 P0E 3 Power Supply Circuit P0E Stack (5 levels) V DD GND CPU Clock X IN Basic Interval/ Watchdog Timer OSC X OUT 4 µPD17215 PD17215, 17216, 17217, 17218 CONTENTS 1. 9 Notes on Using INT and RESET Pins . 9 MEMORY SPACE . 10 Program Counter (PC) . 10 2.2 Program Memory (ROM) . 10 2.3 Stack . 12 2.4 Data Memory (RAM) . 14 2.5 Register File (RF) . 21 PORTS . 24 3.1 Port 0A (P0A0-P0A3) . 24 3.2 Port 0B (P0B0-P0B3) . 24 3.3 Port 0C (P0C0-P0C3) . 24 3.4 Port 0D (P0D0-P0D3) . 24 3.5 Port 0E (P0E0-P0E3) . 24 3.6 INT Pin . 25 3.7 Switching Bit I/O . 26 3.8 Specifying Pull-up Sesistor Connection . 27 CLOCK GENERATOR CIRCUIT . 28 4.1 Instruction Execution Time (CPU Clock) Selection . 28 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT . 29 5.1 Configuration of 8-bit Timer (with modulo function) . 29 5.2 Function of 8-bit Timer (with modulo function) . 31 5.3 Carrier Generator Circuit for Remote Controller . 32 BASIC INTERVAL TIMER/WATCHDOG TIMER . 36 6.1 Source Clock for Basic Interval Timer . 36 6.2 Controlling Basic Interval Timer . 36 6.3 7. 8 Processing of Unused Pins . 2.1 6. Input/Output Circuits . 1.4 5. 7 1.3 4. Pin Function List . 1.2 3. 7 1.1 2. PIN FUNCTIONS . Operation Timing for Watchdog Timer . 38 INTERRUPT FUNCTIONS . 39 7.1 Interrupt Sources . 39 7.2 Hardware of Interrupt Control Circuit . 40 7.3 Interrupt Sequence . 44 5 µPD17215 PD17215, 17216, 17217, 17218 8. STANDBY FUNCTIONS . 46 8.1 HALT Mode . 46 8.2 HALT Instruction Execution Conditions . 47 8.3 STOP Mode . 47 8.4 STOP Instruction Execution Conditions . 49 8.5 Releasing Standby Mode . 49 RESET . 50 9.1 Reset by Reset Signal Input . 50 9.2 Reset by Watchdog Timer (Connect RESET and WDOUT pins) . 50 9.3 Reset by Stack Pointer (Connect RESET and WDOUT pins) . 51 10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) . 51 11. ASSEMBLER RESERVED WORDS . 52 9. 11.1 Mask Option Directives . 52 11.2 Reserved Symbols . 53 12. INSTRUCTION SET . 58 12.1 Instruction Set Outline . 58 12.2 Legend . 59 12.3 List of Instruction Sets . 60 12.4 Assembler (AS17K AS17K) Built-In Macro Instruction . 62 13. ELECTRICAL SPECIFICATIONS . 63 14. CHARACTERISTIC WAVEFORMS (REFERENCE VALUE) . 70 15. APPLICATION CIRCUIT EXAMPLE . 16. PACKAGE DRAWINGS . 74 17. RECOMMENDED SOLDERING CONDITIONS . 76 APPENDIX A. DIFFERENCES AMONG µPD17215 PD17215, 17216, 17217, 17218 AND µPD17P218 PD17P218 . 77 APPENDIX B. FUNCTIONAL COMPARISON OF µPD17215 PD17215 SUBSERIES RELATED PRODUCTS . 78 APPENDIX C. DEVELOPMENT TOOLS . 6 73 79 µPD17215 PD17215, 17216, 17217, 17218 PIN FUNCTIONS 1.1 Pin Function List No. Symbol Function 15 P0A0 4-bit CMOS input port with pull-up resistor. 16 P0A1 Can be used for key return input of key matrix. When at least 17 P0A2 one of these pins goes low, standby function is released. 18 P0A3 19 P0B0 20 P0B1 21 P0B2 22 P0B3 23 P0C0 24 P0C1 25 P0C2 26 P0C3 27 P0D0 4-bit N-ch open-drain output port. 28 P0D1 Can be used for key source output of key matrix. 1 P0D2 Output Form On Reset - Input - Input 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low,standby function is released. 4-bit N-ch open-drain output port. N-ch Low- Open- level drain Can be used for key source output of key matrix. output N-ch Low- Open- level drain output 2 P0D3 4 P0E0 Can be set in inputset in input or output mode in 1-bit units. CMOS 5 P0E1 In output mode, this port functions as a highcurrent CMOS output push- 6 P0E2 port. In input mode, function as CMOS input and can bespecified pull 7 P0E3 to connect pull-up resistor by program. 8 REM 4-bit input/output port. Input Outputs transfer signal for infrared remotecontroller. CMOS Low-level Active-high output. pusl-pll output - Input Power supply - - Ground - - External interrupt request signal input - Input System reset input. CPU can be reset when low-level signal is input to this pin. While low-level signal is input, oscillator circuit is 13 RESET 9 VDD 12 GND 3 INT stopped. Can be connected to pull-upresistor by mask option. Output detecting hang-up and drop in supply voltage.This pin outputs at low level either when an overflow occurs in the 14 WDOUT N-ch watchdog timer, when an overflow/underflow occurs in the stack, Open- or when the supply voltage drops below a specified level (mask drain option). Connect this pin to the RESET pin. 11 XIN 10 XOUT Connects ceramic oscillator for system clock oscillation - 1. Highimpedance Low-level output at low voltage detection (Oscillation stops) 7 µPD17215 PD17215, 17216, 17217, 17218 1.2 Input/Output Circuits The equivalent input/output circuit for each µPD17215 PD17215 pin is shown below. (1) P0A, P0B (4) RESET V DD V DD Mask option Input buffer (2) P0C, P0D Output latch data Input buffer Schmitt trigger input with hysteresis characN-ch teristics (5) (3) INT P0E V DD Input buffer data Pull-up register P-ch Schmitt trigger input with hysteresis V DD data Output latch P-ch N-ch output disable characteristics (6) REM V DD data Selector P-ch Input buffer N-ch output disable (7) WDOUT data 8 N-ch µPD17215 PD17215, 17216, 17217, 17218 1.3 Processing of Unused Pins Process the unused pins as follows: Table 1-1 Processing of Unused Pins Pin Recommended Connection P0A0-P0A3 Connect to VDD P0B0-P0B3 Connect to VDD P0C0-P0C3 Connect to GND P0E0-P0E3 Input : Connect to VDD or GND Output : Open REM Open INT Connect to GND WDOUT 1.4 Connect to GND P0D0-P0D3 Connect to GND Notes on Using INT and RESET Pins In addition to the functions shown in 1.1 PIN FUNCTIONS, the INT and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD17215 PD17215 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the µPD17215 PD17215 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the INT or RESET pin is too long, noise superimposed on the wiring line of the pin main cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. · Connect diode with low VF between VDD · Connect capacitor between VDD and INT/RESET pin and INT/RESET pin V DD Diode with low V F V DD V DD INT, RESET V DD INT, RESET If the test mode is set by the INT pin, low level is output from the WDOUT pin. In this case, connect the WDOUT and RESET pin. 9 µPD17215 PD17215, 17216, 17217, 17218 2. 2.1 MEMORY SPACE Program Counter (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter is a 11/12/13-bit binary counter as shown in Fig. 2-1. Its contents are initialized to address 0000H 0000H at reset. Fig. 2-1 Configuration of Program Counter Page MSB LSB PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC (µPD17215 PD17215) PC (µPD17216 PD17216) PC (µPD17217 PD17217, 17218) 2.2 Program Memory (ROM) The configuration of the program memory is as follows: Part Number Capacity Address µPD17215 PD17215 2048 x 16 bits 0000H-07FFH 0000H-07FFH µPD17216 PD17216 4096 x 16 bits 0000H-0FFFH 0000H-0FFFH µPD17217 PD17217 6144 x 16 bits 0000H-17FFH 0000H-17FFH µPD17218 PD17218 8192 x 16 bits 0000H-1FFFH 0000H-1FFFH The program memory stores a program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Fig. 2-2 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H 0000H to 07FFH 07FFH. 10 µPD17215 PD17215, 17216, 17217, 17218 Fig. 2-2 Program Memory Map Address 16 bits 0000H 0000H Reset start address 0001H 0001H Basic interval timer interrupt vector 0002H 0002H External input (INT) interrupt vector 0003H 0003H 8-bit timer interrupt vtor Branch addresses for BR addr instruction Subroutine entry Page 0 addresses for CALL addr instruction Branch addresses for BR @AR instruction ( µPD17215 PD17215) 07FFH 07FFH 0FFFH ( µPD17216 PD17216) 17FFH 17FFH ( µPD17217 PD17217) 1FFFH ( µPD17218 PD17218) Page 1 Page 2 Page 3 Subroutine entry addresses for CALL @AR instruction Table reference addresses for MOVT DBR, @AR instruction 11 µPD17215 PD17215, 17216, 17217, 17218 2.3 Stack A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 Stack configuration Fig. 2-3 shows the stack configurarion. A stack consists of a stack pointer (a 4-bit binary counter, the upper 1-bit fixed to 0), five 11-bit (µPD17215 PD17215)/12-bit (µPD17216 PD17216)/13-bit (µPD17217 PD17217, 17218) address stack registers, and three 5-bit (µPD17215 PD17215, 17216)/6-bit (µPD17217 PD17217, 17218) interrupt stack registers. Fig. 2-3 Stack Configuration Stack pointer (SP) b3 0 b2 b1 Address stack registers (ASR) b0 SPb2 SPb1 SPb0 b 12 b 11 b 10 b9 b8 b7 b6 b5 b4 Address stack register 3 4H Address stack register 4 5H Undefined 6H Undefined 7H b0 Address stack register 2 3H b1 Address stack register 1 2H b2 Address stack register 0 1H WDOUT pin goes low when the contents of the stack pinter are 6H-7H. 0H b3 Undefined µ PD17215 PD17215 µPD17216 PD17216 µ PD17217 PD17217, 17218 Interrupt stack registers (INTSK) b5 b4 b3 b2 b1 b0 0H BANKSK0 BCDSK0 CMPSK0 CYSK0 ZSK0 IXESK0 1H BANKSK1 BCDSK1 CMPSK1 CYSK1 ZSK1 IXESK1 2H BANKSK2 BCDSK2 CMPSK2 CYSK2 ZSK2 IXESK2 µ PD17215 PD17215, 17216 µ PD17217 PD17217, 17218 12 µPD17215 PD17215, 17216, 17217, 17218 2.3.2 Function of stack The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. The WDOUT pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is accepted. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur. 2.3.3 Stack Pointer (SP) and Interrupt Stack Pointer Table 2-1 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H-07 0H-07. Because there are only five stack registers available, however, the WDOUT pin goes low if the value of SP is 6 or greater. Table 2-1 Operations of Stack Pointer Instruction Value of Stack Pointer (SP) Counter of Interrupt Stack Register ­1 0 ­1 ­1 +1 0 +1 +1 CALL addr CALL @AR MOVT DBF, @AR (1st Instruction Cycle) PUSH AR When Interrupt Is Accepted RET RETSK MOVT DBF, @AR (2nd Instruction Cycle) POP AR RET1 13 µPD17215 PD17215, 17216, 17217, 17218 2.4 Data Memory (RAM) Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 2.4.1 Memory configuration Figure 2-4 shows the configuration of the data memory (RAM). The data memory consists of two "banks": BANK0 and BANK1. In each bank, every 4 bits of data is assigned an address. The higher 3 bits of the address indicate a "row address" and the lower 4 bits of the address indicate a "column address". For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= a "nibble"). In addition, the data memory is divided into following six functional blocks: (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other nibbles, each bank has a system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory. The reset value is 0320H 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles long) of any bank of data memory. The row address of the general register is pointed by the general pointer (RP) in the system register (SYSREG). (4) Port register A port data register is resident on addresses 6FH, and 70H to 73H (5 nibbles) of BANK0 of data memory. No data can be written to the addresses 70H to 73H of BANK1 (the values of addresses 70H to 73H of BANK0 are read in this case). µPD17215 PD17215 and 17216 are not provided with BANK1. 14 µPD17215 PD17215, 17216, 17217, 17218 (5) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. This memory area has a total of 223 nibbles (111 nibbles in BANK0 and 112 nibbles in BANK1). µPD17215 PD17215 and 17216 are not provided with BANK1. Fig. 2-4 Configuration of Data Memory BANK 0 Column address 0 1 2 3 4 5 6 7 8 9 A B Row address 0 C D E F Data buffer (DBF) 1 Example: Address 1AH in BANK 0 2 3 4 5 P0E 6 7 P0A P0B P0C P0D System register (SYSREG) 1 Column address 2 3 4 5 6 BANK 1 7 8 9 A B C D E F Row address 0 System register (SYSREG) Caution: No data can be written to the addresses 70H to 73H of BANK1 (the value of P0A to P0D are read in this case). 15 µPD17215 PD17215, 17216, 17217, 17218 2.4.2 System registers (SYSREG) The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers: Address registers (AR0-AR3)* Window register (WR) Bank register (BANK)* Memory pointer enable flag (MPE) Memory pointers (MPH, MPL) Index registers (IXH, IXM, IXL) General register pointers (RPH, RPL) Program status word (PSWORD) *: The address register (AR3) and the bank register (BANK) are fixed to 0 in the µPD17215 PD17215 and 17216. Fig. 2-5 Configuration of System Register Address 74H 75H 76H 77H 79H Window Bank register register (WR) (BANK) Address register (AR) Name 78H 7AH 7BH Index register (IX) Bit AR 3 AR 2 AR 1 AR 0 WR BANK IXH IXM 7DH 7EH General register pointer (RP) Data memory row address pointer (MP) MPH Symbol 7CH 7FH Program status word (PSWORD) MPL IXL RPH RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 (WR) Data 0 0 0 (AR) ( µ PD17217 PD17217, 17218) 0 0 0 0 0 0 0 0 0 Initial Value At Reset (AR) ( µ PD17216 PD17216) (AR) ( µ PD17215 PD17215) (BANK) M 0 0 0 P 0 0 0 * * E (MP) (RP) 0 0 0 * BCC I CMY Z X DP E * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *: This bit is fixed to 0 in the µPD17215 PD17215 and 17216. 16 (IX) µPD17215 PD17215, 17216, 17217, 17218 2.4.3 General register (GR) A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-6 shows the configuration of the general register. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. The row address is selected by the general register pointer (RP) of the system register. The RP having four significant bits in the µPD17217 PD17217 and 17218 can point to any row address in the range of 0H to 7H of each bank (BANK0 and BANK1). In the µPD17215 PD17215 and 17216, 3 bits are available in the RP. These bits can point to any row address in the range of 0H to 7H of BANK0. (2) Functions of the general register The general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. Similarly, the general register can be accessed by a Data Memory Manipulation instruction as it is a part of the data memory. Fig. 2-6 Configuration of General Registers General register pointer (RP) RPH BANK0 RPL b 3 b 2 b 1 b 0 b3 b 2 b 1 b 0 F i x e d F i x e d F i x e d 0 0 0 0 0 1 0 0 1 0 t o t o t o 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 Column address 1 A s s i g n e d t o 2 Example: General registers when RP = 0000010B 0000010B General registers (16 nibbles) 3 4 5 Port register 6 7 Port register BANK1 System registers RP General register settable range 0 B C 1 D 2 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 f 3 l a 4 g 5 1 1 1 0 6 1 1 1 1 7 Same system registers exist System registers 17 µPD17215 PD17215, 17216, 17217, 17218 2.4.4 Data buffer (DBF) The data buffer on the addresses 0CH to 0FH of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the Data Buffer The data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). Figure 2-7 shows the relationship between the data buffer and peripheral hardware. Fig. 2-7 Data Buffer and Peripheral Hardware Data buffer (DBF) Peripheral address Peripheral hardware Constant data 18 8-bit timer (TMC, TMM) Carrier generator for remote controller (NRZLTMM, NRZHTMM) 40H Program memory (ROM) 05H, 06H 03H, 04H Internal bus Address register (AR) µPD17215 PD17215, 17216, 17217, 17218 Table 2-2 Relations between Hardware Peripherals and Data Buffer Peripheral Register Transferring Data with Data Buffer Hardware Peripherals Name Symbol Peripheral Address Data Buffer PUT/GET 8-bit counter TMC 05H DBF0, DBF1 GET only 8-bit modulo register TMM 06H DBF0, DBF1 PUT only 8-Bit Timer NRZ low level period setting modulo register Remote Controller Carrier Generator NRZ high level period setting modulo register Address Register Address register PUT GET NRZLTMM 03H NRZHTMM AR DBF0, DBF1 04H DBF0, DBF1 40H DBF0-DBF3 PUT (clear bit 3 of DBF1 to 0) GET (bits 3 of DBF1 is always 0) PUT (bits 0 to 3 of AR3 and bit 3 of 1 AR2 are any)* GET (bits 0 to 3 of AR3 and bit 3 of 2 AR2 are always 0)* *1: In the µPD17216 PD17216: bits 0 to 3 of AR3 are any, in the µPD17217 PD17217, 17218: bits 1 to 3 of AR3 are any 2: In the µPD17216 PD17216: bits 0 to 3 of AR3 are always 0, in the µPD17217 PD17217, 17218: bits 1 to 3 of AR3 are always 0 (2) Table reference A MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF,@AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF). Data buffer DBF 3 DBF 2 DBF 1 DBF 0 Program memory (ROM) MOVT DBF, @ AR 16 bits b15 b0 19 µPD17215 PD17215, 17216, 17217, 17218 (3) Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows: · When device operates Nothing changes even if data is written to the read-only register. If the unused address is read, an undefined value is read. Nothing changes even if data is written to that address. · Using assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. · If an in-circuit emulator (IE-17K IE-17K or IE-17K-ET IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur. 20 µPD17215 PD17215, 17216, 17217, 17218 2.5 Register File (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of AS17K AS17K, SETn, CLRn, and INITFLG. 2.5.1 Configuration of register file Fig. 2-8 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H-3FH 00H-3FH regardless of the bank, the addresses 00H-3FH 00H-3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH 00H-3FH of the control registers and 40H-7FH 40H-7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H-BFH 80H-BFH on the IE-17K IE-17K to facilitate debugging. Fig. 2-8 Register File Access with PEEK or POKE Instructions 0 1 2 3 4 5 Column address 6 7 8 9 A B C D E F 0 1 2 Data memory 3 4 5 POKE M063, WR 6 7 Row address System register 0 1 PEEK WR, SP 2 POKE LCDMD, WR 3 Control register Register file 21 µPD17215 PD17215, 17216, 17217, 17218 2.5.2 Control registers The control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00H-3FH 00H-3FH of the register file. Of these, however, only 14 nibbles are actually used. The remaining 50 nibbles are unused registers that are inhibited from being read or written. When the "PEEK WR, rf" instruction is executed, the contents of the register file addressed by "rf" are read to the window register. When the "POKE rf, WR" instruction is executed, the contents of the window register are written to the register file addressed by "rf". When using the assembler (AS17K AS17K), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Fig. 11-1 Register File List. SETn : Sets flag to "1" CLRn : Sets flag to "0" SKTn : Skips if all flags are "1" SKFn : Skips if all flags are "0" NOTn : Complements flag INITFLG: Initializes flag 2.5.3 Notes on using register files When using the register files, bear in mind the points described below. For details, refer to µPD172xx subseries User's Manual (IEU-1317 IEU-1317). (1) When manipulating control registers (read-only and unused registers) When manipulating the write-only (W), the read-only (R) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: · When device operates Nothing changes even if data is written to the read-only register. If the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. · Using assembler An error occurs if instruction is excecuted to read data to the write-only register. An error occurs if an instruction is executed to write data to the read-only register. An error also occurs if an instruction is executed to read or write the unused address. · When an in-circuit emulator (IE-17K IE-17K or IE-17K-ET IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if the write-only register is read, and an error does not occur. Nothing changes even if data is written to the read-only register, and an error does not occur. An undefined value is read if the unused address is read; nothing changes even if data is written to this address. An error does not occur. 22 µPD17215 PD17215, 17216, 17217, 17218 (2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand "rf" of the "PEEK WR, rf" or "POKE rf, WR" instruction if the 17K Series Assembler (AS17K AS17K) is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as the addresses 80H-BFH 80H-BFH of BANK0. The portion of the register file overlapping the data memory (40H-7FH 40H-7FH), however, can be defined as symbols as is. 23 µPD17215 PD17215, 17216, 17217, 17218 3. 3.1 PORTS Port 0A (P0A0-P0A3) This is a 4-bit input port. Data is read through port register P0A (address 70H). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.2 Port 0B (P0B0-P0B3) This is a 4-bit input port. Data is read through port register P0B (address 71H). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.3 Port 0C (P0C0-P0C3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0C (address 72H). This port is an N-ch open-drain output port, and can be used as the key source of a key matrix. In the standby mode, this port outputs low-level signals. 3.4 Port 0D (P0D0-P0D3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0D (address 73H). This port is an N-ch open-drain output port, and can be used as the key source for a key matrix. In the standby mode, this port outputs low-level signals. 3.5 Port 0E (P0E0-P0E3) This is a 4-bit I/O port which can be set in either the input or output mode in 1-bit units by the P0EBIO (address 27H) of the register file. To read the input data or to set the output data, use the P0E register (address 6F). When data is read in the output mode, the contents of the output latch are read. Connection of a pull-up resistor can be specified in 1-bit units by the P0EBPU (address 17H) of the register file. (When the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) On reset, this port functions as an input port. 24 µPD17215 PD17215, 17216, 17217, 17218 3.6 INT Pin This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the IRQ flag (RF: address 3EH, bit 0) is set. The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to the pin, the INT flag is set to "1"; when the low level is input, the flag is reset to "0" (refer to 7.2.1 INT). Fig. 3-1 Relations between Port Register and Each Pin Contents to Be Read Bank Address Port Bit Output Form Input Mode Contents to Be Written Output Mode Input Mode Output Mode On Reset b 3 P0A 3 b 2 P0A 2 70H Port 0A b 1 P0A 1 b 0 P0A 0 Input only Input mode (w/pull-up resistor) Pin status b 3 P0B 3 b 2 P0B 2 71H Port 0B b 1 P0B 1 b 0 P0B 0 b 3 P0C 3 b 2 P0C 2 0 72H Port 0C b 1 P0C 1 b 0 P0C 0 b 3 P0D 3 N-ch open-drain (Output only) Output mode (Low level output) b 2 P0D 2 73H Output latch Port 0D Output latch b 1 P0D 1 b 0 P0D 0 b 3 P0E 3 b 2 P0E 2 6FH Port 0E b 1 P0E 1 COMS push-pull Pin status Output latch Input mode (w/pull-up resistor) b 0 P0E 0 25 µPD17215 PD17215, 17216, 17217, 17218 3.7 Switching Bit I/O The I/O which can be set in the input or output mode in bit units is called a bit I/O. P0E is a bit I/O port, which can be set in the input or output mode in bit units by the register file shown below. When the mode is changed from input to output, the P0E output latch contents are output to the port lines, as soon as the mode has been changed. 3 2 1 0 Address: On reset: R/W: P0EBIO3 P0EBIO2 P0EBIO1 P0EBIO0 RF : 27H 0H R/W P0EBIO0 Sets P0E0 Input/Output Mode 0 Sets P0E0 in input mode 1 Sets P0E0 in output mode P0EBIO1 Sets P0E1 Input/Output Mode 0 Sets P0E1 in input mode 1 Sets P0E1 in output mode P0EBIO2 Sets P0E2 Input/Output Mode 0 Sets P0E2 in input mode 1 Sets P0E2 in output mode P0EBIO3 Sets P0E3 Input/Output Mode 0 1 26 Sets P0E3 in input mode Sets P0E3 in output mode µPD17215 PD17215, 17216, 17217, 17218 3.8 Specifying Pull-up Resistor Connection Whether or not a pull-up resistor is connected to port P0E can be specified by the following registers of the register file in 1-bit units when the port is in the input mode*. 3 2 1 0 P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0 Address: On reset: R/W: RF : 17H 0H R/W P0EBPU0 Connects Pull-Up Resistor to P0E 0 0 Not connected 1 Connected P0EBPU1 Connects Pull-Up Resistor to P0E 1 0 Not connected 1 Connected P0EBPU2 Connects Pull-Up Resistor to P0E 2 0 Not connected 1 Connected P0EBPU3 Connects Pull-Up Resistor to P0E 3 0 1 *: Not connected Connected To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register. 27 µPD17215 PD17215, 17216, 17217, 17218 4. 4.1 CLOCK GENERATOR CIRCUIT Instruction Execution Time (CPU Clock) Selection The µPD17215 PD17215 is equipped with a clock oscillator circuit that supplies clocks to the CPU and hardware peri-pherals. Instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by using the POKE instruction. Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed. When using the high-speed mode, pay attention to the supply voltage. (Refer to 13. ELECTRICAL SPECIFICATIONS.) At reset, the ordinary mode is set. 3 2 1 0 Address: On reset: R/W: 0 0 0 SYSCK RF : 02H 0H R/W SYSCK Selects Instruction Execution Time 0 Ordinary mode 32/f X (8 µ s) 1 High-speed mode 16/f X (4 µ s) Figures in ( ): indicate figures when system clock f X= 4 MHz. 28 µPD17215 PD17215, 17216, 17217, 17218 5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT The µPD17215 PD17215 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 Configuration of 8-bit Timer (with modulo function) Figure 5-1 shows the configuration of the 8-bit timer. As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H, bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1) and TMCK0 (address 33H, bit 0) of the register file. The value of the 8-bit counter is read by using the GET instruction through DBF (data buffer). No value can be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value of the modulo register cannot be read. When the value of the counter coincides with that of the modulo register, an interrupt flag (IRQTM: address 3FH, bit 0) of the register file is set. TMC 7 6 5 4 3 1 Address On reset R/W Peripheral register: 05H 2 00H R Address On reset R/W Peripheral register: 06H FFH W 0 8-bit counter TMM 7 6 5 4 3 2 8-bit modulo register Caution: 1 0 Do note clear TMM to 0 (IRQTM is not set). 29 µPD17215 PD17215, 17216, 17217, 17218 Fig. 5-1 Configuration of 8-bit Timer and Remote Controller Carrier Generator Circuit Data buffer Internal bus 8-bit timer RF : 33H TMEN TMRES TMCK1 TMCK0 8-bit modulo register TMM f X/32 f X /64 f X /256 R Selector IRQTM Comparator Q S 8-bit counter TMC Remote controller carrier generator circuit f X /2 SW 7-bit counter RF : 11H Comparator NRZBF bit 7 × RF : 12H 7-bit modulo register NRZLTMM NRZ 7-bit counter Comparator bit 7 0 7-bit modulo register NRZHTMM fixed Remark: 30 TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers. REM µPD17215 PD17215, 17216, 17217, 17218 5.2 Function of 8-bit Timer (with modulo function) 3 2 TMEN 1 TMRES 0 TMCK1 Address TMCK0 On reset RF : 33H TMCK1 8H *1 TMCK0 R/W R/W *2 8-Bit Timer Clock Source Selection 0 0 Count clock: fX/32 (Measurement time range: 8 µ s to 2.048 ms) 0 1 Count clock: fX/64 (Measurement time range: 16 µ s to 4.096 ms) 1 0 Count clock : fX/256 (Measurement time range: 64 µ s to 16.384 ms) 1 1 Remote control carrier generation circuit output Value indicated by parentheses is for when ( ): f SYS (system clock) = f X = 4MHz TMRES 8-Bit Timer Reset Flag 0 Data read out is always "0" 1 Resets 8-bit counter and IRQTM TMEN 8-Bit Timer Count Enable Flag 0 Stops 8-bit timer count operation 1 Enable 8-bit timer count operation (falling edge) *1: When the STOP mode is released, bit 3 must be set. 2: Bit 2 is a write-only bit. NRZLTMM 7 6 5 × 4 3 2 Address On reset R/W Peripheral register: 03H 1 Undefined R/W 0 7-bit modulo register Bit 7 Output Control of REM Pin 0 When NRZ = 1, carrier output to REM pin 1 When NRZ = 1, high-level output to REM pin NRZHTMM 7 0 6 5 4 3 2 1 Address On reset R/W Peripheral register: 04H Undefined R/W 0 7-bit modulo register Bit 7 Fixed to 0 31 µPD17215 PD17215, 17216, 17217, 17218 5.3 Carrier Generator Circuit for Remote Controller µPD17215 PD17215 is provided with a carrier generator circuit for the remote controller. The remote controller carrier generator circuit consists of a 7-bit counter, NRZ high-level period setting modulo register (NRZHTMM), and NRZ low-level period setting modulo register (NRZLTMM). The high-level and low-level periods are set in the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency. The system clock (fx) is divided by two and is input to the 7-bit counter. Therefore, when a 4-MHz oscillator is used, 2 MHz (0.5 µs) is input to the counter as the clock; when a 32-kHz oscillator (fXT) is used, 16 kHz is input. The NRZ high-level output period setting modulo register is called NRZHTMM, and the NRZ low-level period setting modulo register is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents for these register are read by the GET instruction. Bit 7 of NRZLTMM specifies whether the carrier or high level is output to the REM pin. To output the carrier, be sure to clear bit 7 to 0. 5.3.1 Remote controller signal output control The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF for the register file and timer 0. While the NRZ content is "1", the clock generated by the remote controller carrier generator circuit is output to the REM pin; while the NRZ content is "0", the REM pin outputs a low level. The NRZBF content is automatically transferred to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes in synchronization with the timer 0 counting operation. If the interrupt signal is generated from timer 0 with the REM pin at the high level, NRZ being "1", and the carrier clock at the high level, the REM pin output is not in accordance with the updated content of NRZ, until the carrier clock goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). When the content of NRZ is "0", the remote controller carrier generator circuit stops. However, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the NRZ content becomes "0". An actual example showing a remote controller signal output to the REM pin is presented below. When bit 7 of NRZLTMM is 0 (carrier output) NRZ REM MAX. 500 ns (delay)* (f x = 4 MHz) REM pin does not go low until carrier goes low even if NRZ becomes 0 *: Value when (TMCK1, TMCK0) (1, 1). When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock. 32 µPD17215 PD17215, 17216, 17217, 17218 When bit 7 of NRZLTMM is 0 (carrier not output) NRZ REM 3 2 1 0 Address On reset R/W 0 0 0 NRZ RF : 12H 0H R/W NRZ NRZ Data 0 Outputs low level to REM pin 1 Outputs a carrier to REM pin or high level output 3 2 1 0 Address On reset R/W 0 0 0 NRZBF RF : 11H 0H R/W NRZBF 0 1 NRZ Data Output Next NRZ buffer bit. Transfered to NRZ by interrupt signal for 8-bit timer. Setting carrier frequency and duty factor Where the system clock frequency is fX and carrier frequency is fC: l (division ratio) = fX/(2 × fC) l is divided into m:n and is set in the modulo registers as follows: High-level period set value = {l × m/(m + n)} - 1 Low-level period set value = {l × n/(m + n)} - 1 Example: Where fc = 38 kHz, duty factor (high-level period) = 1/3, and fx = 4 MHz, l = 4 MHz/(2 x 38 kHz) = 52.6 m:n = 1:2 From the above, the value of the modulo register is: High-level period · · 17 = · 34 Low-level period = · Therefore, the carrier frequency is 37.74 kHz. 33 µPD17215 PD17215, 17216, 17217, 17218 Table 5-1 Carrier Frequency List (fx = 4 MHz) Set value tH (µs) tL (µs) 1/fC (µs) fC (kHz) Duty 00H 0.5 0.5 1.0 1000 1/2 02H 1.0 1.5 2.5 400 2/5 04H 04H 2.5 2.5 5.0 200 1/2 09H 09H 5.0 5.0 10.0 100 1/2 0FH 10H 8.0 8.0 16.5 60.6 1/2 0FH 21H 8.0 17.0 25.0 40.0 1/3 11H 21H 9.0 17.0 26.0 38.5 1/3 11H 22H 9.0 17.5 26.5 37.7 1/3 NRZHTMM NRZLTMM 00H 01H 19H 35H 13.0 27.0 40.0 25.0 1/3 3FH 3FH 32.0 32.0 64.0 15.6 1/2 7FH 7FH 64.0 64.0 120.0 7.8 1/2 tH REM (fC) 1/fC 34 tL µPD17215 PD17215, 17216, 17217, 17218 5.3.2 Countermeasures against noise during transmission (carrier output) When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several of equivalent resistance (r) exists in the power source as shown in Fig. 5-2. This resistance increases to 10 to 20 if the supply voltage drops to 2 V. While the carrier is output from the REM pin (while the infrared LED lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures: Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. Locate the oscillator as close as possible to the microcontroller and shield it with GND lines (as indicated by the shaded portion in the figure below). Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. To improve the reliability in case of program hang-up, use the watchdog timer (connect the WDOUT and RESET pins). Fig. 5-2 Example of Countermeasures against Noise 0.5 ­ 1 A Infrared LED REM VDD Microcomputer r + Batteries RESET ­ WDOUT VSS Remarks 1: The INT and RESET pins are multiplexed with test pins (refer to 1.4 NOTES ON USING OF INT AND RESET PINS). 2: In this figure, the RESET pin is connected to a pull-up resistor by mask option. 35 µPD17215 PD17215, 17216, 17217, 17218 6. BASIC INTERVAL TIMER/WATCHDOG TIMER The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 Source Clock for Basic Interval Timer The system clock (fx) is divided, to generate the source clock for the basic interval timer. The input clock frequency for the basic interval timer is fx/27. When the CPU is set in the STOP mode, the basic interval timer also stops. 6.2 Controlling Basic Interval Timer The basic interval timer is controlled by the bits on the register file. That is, the basic interval timer is reset by BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the watchdog timer is reset by WDTRES. Selector B Fig. 6-1 Basic Interval Timer Configuration fX /2 18 fX /2 20 System clock f X 1/2 7 divider 1/2 11 divider 1/2 divider 1/2 divider 1/2 divider WDOUT BTMRES 36 WDTRES BTMCK IRQBTM µPD17215 PD17215, 17216, 17217, 17218 3 2 1 0 Address On reset R/W WDTRES BTMCK BTMRES 0 RF : 03H 0H R/W* BTMRES Basic Interval Timer Reset 0 Data read out is always "0" 1 Writing "1" resets basic interval timer BTMCK Basic Interval Timer Mode Selection 0 Generates interrupt signal IRQBTM every f X /2 20 1 Generates interrupt signal IRQBTM every f X /2 18 WDTRES Watchdog Timer Reset 0 1 *: Data read out is always "0" Writing "1" resets watchdog timer (f X /2 21 counter) Bits 1 and 3 are write-only bits. 37 µPD17215 PD17215, 17216, 17217, 17218 6.3 Operation Timing for Watchdog Timer The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed time*, it judges that "the program has hung up", and the µPD17215 PD17215 is reset. It is therefore necessary to reset through programming the watchdog timer with in a fixed time. The watchdog timer can be reset by setting WDTRES to 1. *: Fixed time: approx. 340 ms (at 4 MHz) Coutions 1: The watchdog timer cannot be reset in the shaded range in Fig. 6-2. Therefore, set WDTRES before both the fx/221 and fx/220 signals go high. 2: Refer to 9. RESET for the WDOUT pin function. Fig. 6-2 Watchdog Timer Operation Timing f X /218 f X /219 f X /220 f X /221 INTBTM (f X/2 20 ) INTBTM (f X/2 18 ) WDOUT WDOUT output goes low if WDTRES is not set Watchdog timer reset signal WDTRES Setting WDTRES at this timing is invalid 38 µPD17215 PD17215, 17216, 17217, 17218 7. 7.1 INTERRUPT FUNCTIONS Interrupt Sources µPD17217 PD17217 is provided with three interrupt sources. When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1. Table 7-1 Vector Address Priority Interrupt Source Ext/Int Vector Address 1 8-bit timer Internal 0003H 0003H 2 INT pin rising and falling edges External 0002H 0002H 3 Basic interval timer Internal 0001H 0001H When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is accepted, the interrupt is disabled. To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions. Caution: In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing the saved contents be returned to thier original location. 39 µPD17215 PD17215, 17216, 17217, 17218 7.2 Hardware of Interrupt Control Circuit This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 7-2 Interrupt Request Flags and Interrupt Enable Flag Interrupt Request Flag Signal Setting Interrupt Request Flag Interrupt Enable Flag IRQTM IPTM IRQ Set when edge of INT pin input signal is detected IP IRQBTM 40 Reset by 8-bit timer. Reset by basic interval timer. IPBTM µPD17215 PD17215, 17216, 17217, 17218 7.2.1 INT This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to "1"; when a low level is input, the flag is reset to "0". 3 2 1 0 Address On reset R/W 0 0 0 INT RF : 0FH Undefined R INT INT Pin Level Detection 0 1 7.2.2 INT pin : Low level INT pin : High level IEG This pin selects the interrupt edge to be detected on the INT pin. When this flag is "0", the interrupt is detected at the rising edge; when it is "1", the interrupt is detected at the falling edge. 3 2 1 0 Address On reset R/W 0 0 0 IEG RF : 1FH 0H R/W IEG INT Pin Interrupt Detection Edge Selection 0 Rising edge of INT pin 1 Falling edge of INT pin 41 µPD17215 PD17215, 17216, 17217, 17218 7.2.3 Interrupt enable flag This flag enables each interrupt source. When this flag is "1", the corresponding interrupt is enabled; when it is "0", the interrupt is disabled. 3 2 1 0 Address On reset R/W 0 IPBTM IP IPTM RF : 2FH 0H R/W IPTM 8-Bit Timer Interrupt Enable Flag 0 Disables interrupt acceptance by 8-bit timer 1 Enables interrupt acceptance by 8-bit timer IP INT Pin Interrupt Enable Flag 0 Disables interrupt acceptance by INT pin input 1 Enables interrupt acceptance by INT pin input IPBTM Basic Interval Timer Interrupt Enable Flag 0 1 42 Disables interrupt acceptance by basic interval timer Enables interrupt acceptance by basic interval timer µPD17215 PD17215, 17216, 17217, 17218 7.2.4 IRQ This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to "1". When the interrupt has been accepted, the interrupt request flag is reset to "0". The interrupt request flag can be read or written by the program. Therefore, when it is set to "1", an interrupt can be generated by the software. By writing "0" to the flag, the interrupt pending status can be canceled. 3 2 1 0 Address On reset R/W 0 0 0 IRQBTM RF : 3DH 0H R/W IRQBTM Basic Interval Timer Interrupt Request Flag 0 Interrupt request has not been made. 1 Basic interval timer interrupt request has been made. 3 2 1 0 Address On reset R/W 0 0 0 IRQ RF : 3EH 0H R/W IRQ INT Pin Interrupt Request Flag 0 Interrupt request has not been made. 1 Interrupt request has been made at rising edge or falling edge of INT input. 3 2 1 0 Address On reset R/W 0 0 0 IRQTM RF : 3FH 1H* R/W IRQTM 8-Bit Timer Interrupt Request Flag 0 Interrupt request has not been made. 1 8-bit timer interrupt request has been made. *: 1H is also set after releasing STOP mode. 43 µPD17215 PD17215, 17216, 17217, 17218 7.3 Interrupt Sequence If IRQxxx flag is set to "1" when IPxxx flag is "1", interrupt processing is started after the instruction cycle of the instruction executed when IRQxxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If IPxxx flag is "0", the interrupt processing is not performed even if IRQxxx flag is set, until IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 Operations when interrupt is accepted When an interrupt has been accepted, the CPU performs processing in the following sequence: Clears IRQ××× corresponding to INTE flag and accepted interrupt Decrements value of stack pointer by 1 (SP-1) Saves contents of program counter to stack addressed by stack pointer Loads vector address to program counter Save contents of PSWORD to interrupt stack register One instruction cycle is required to perform the above processing. 44 µPD17215 PD17215, 17216, 17217, 17218 7.3.2 Returning from interrupt processing routine To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle. Loads contents of stack addressed by stack pointer to program counter Loads contents of interrupt stack register to PSWORD Increments value of stack pointer by 1 To enable an interrupt after the processing of an interrupt has been finished, the EI instruction must be executed immediately before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, the interrupt is not accepted between the EI and RETI instructions. 45 µPD17215 PD17215, 17216, 17217, 17218 8. STANDBY FUNCTIONS µPD17215 PD17215 is provided with HALT and STOP modes as standby functions. By using the standby function, current dissipation can be reduced. In the HALT mode, the program is not executed, but the system clock fx is not stopped. This mode is maintained, until the HALT mode release condition is satisfied. In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until the STOP mode release condition is satisfied. The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP instruction has been executed. 8.1 HALT Mode In this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current dissipation. Use the HALT instruction to set the HALT mode. The HALT mode releasing condition can be specified by the operand for the HALT instruction, as shown in Table 8-1. After the HALT mode has been released, the operation is performed as shown in Table 8-1 and Figure 8-2. Caution: Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the HALT 8H instruction; otherwise, the HALT mode may not be set. Table 8-1 HALT Mode Releasing Conditions Operand Value Releasing Conditions 0010B 0010B (02H) When interrupt request (IRQTM) occurs for 8-bit timer 1000B 1000B (08H) When interrupt request (IRQTM, IRQWTM, or IRQ), whose interrupt enable flag (IPTM, IPBTM, or IP) is set, occurs When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Other Than Above Inhibited Table 8-2 Operations After HALT Mode Release (1/2) (a) HALT 08H HALT Mode Released by: Interrupt Status Interrupt Enable Flag Low-Level Input of P0A0-P0A3, P0B0-P0B3 Don't care Don't care Operations after HALT Mode Release Instruction next to HALT is executed Disabled Standby mode is not released Enabled Instruction next to HALT is executed Disabled Standby mode is not released Enabled Branches to interrupt vector address DI When Release Condition Is Satisfied by Interrupt EI 46 µPD17215 PD17215, 17216, 17217, 17218 Table 8-2 Operations After HALT Mode Release (2/2) (b) HALT 02H HALT Mode Released by: Interrupt Status Interrupt Enable Flag Operations after HALT Mode Release Disabled DI Enabled 8-Bit Timer Disabled Instructions are executed from the instruction next to the HALT instruction. EI Enabled 8.2 Branches to interrupt vector address HALT Instruction Execution Conditions The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to prevent the program from hangup. If the conditions in Table 8-3 are not satisfied, the HALT instruction is treated as an NOP instruction. Table 8-3 HALT Instruction Execution Conditions Operand Value Execution Conditions 0010B 0010B (02H) When all interrupt request flags (IRQTM) of 8-bit timer are reset 1000B 1000B (08H) When interrupt request flag is reset, corresponding to interrupt whose interrupt enable flag (IPTM, IPBTM, or IP) is set When high level is input to all P0A0-P0A3 and P0B0-P0B3 pins Other Than Above 8.3 Inhibited STOP Mode In the STOP mode, the system clock (fx) oscillation is stopped and the program execution is stopped to minimize current dissipation. To set the STOP mode, use the STOP instruction. The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4. After the STOP mode has released, the operation is performed as follows: Resets IRQTM. Starts the basic interval timer and watchdog timer (does not reset). Resets and starts the 8-bit timer. Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter coincides with the value of the modulo register (IRQTM is set). 47 µPD17215 PD17215, 17216, 17217, 17218 The µPD17215 PD17215 oscillator circuit is stopped, when the STOP instruction has been executed (i.e., in the STOP mode). Oscillation is not resumed, until the STOP mode is released. After the STOP mode has been released, the HALT mode is set. Set the time required to release the HALT mode by using the timer with modulo function. The time that elapses, after the STOP mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table. 8-Bit Modulo Register Set Value (TMM) Time Required to Set Operation Mode after STOP Mode Release At 4 MHz 40H FFH Remark: Caution: 4.160 ms (64 µs × 65) 16.384 ms (64 µs × 256) Set the 8-bit modulo timer before executing STOP instruction. Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction; otherwise, the STOP mode may not be set. Table 8-4 STOP Mode Releasing Conditions Operand Value 1000B 1000B (08H) Others 48 Releasing Conditions When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Inhibited µPD17215 PD17215, 17216, 17217, 17218 8.4 STOP Instruction Execution Conditions The STOP instruction can be executed, only under special conditions, as shown in Table 8-5, to prevent the program from hangup. If the conditions in Table 8-5 are not satisfied, the STOP instruction is treated as an NOP instruction. Table 8-5 STOP Instruction Execution Conditions Operand Value 1000B 1000B (08H) Others 8.5 Execution Conditions High level input for all P0A0-P0A3 and P0B0-P0B3 pins Inhibited Releasing Standby Mode Operations for releasing the STOP and HALT modes will be as shown in Fig. 8-1. Fig. 8-1 Operations After Standby Mode Release (a) Releasing STOP mode by interrupt Wait (time set by TMM) STOP instruction Stanby release signal Operation mode Clock (b) STOP mode Oscillation Oscillation stops HALT mode Operation mode Oscillation Releasing HALT mode by interrupt HALT instruction Stanby release signal Operation mode Clock Remark: Operation mode HALT mode Oscillation The dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted. 49 µPD17215 PD17215, 17216, 17217, 17218 9. RESET 9.1 Reset by Reset Signal Input When a low-level signal more than 50 µs is input to the RESET pin, µPD17215 PD17215 is reset. When the system is reset, the oscillator circuit remains in the HALT mode and then enters an operation mode, like when the STOP mode has been released. The wait time, after the reset signal has been removed, is 16.384 ms (fx = 4 MHz). On power application, input the reset signal at least once because the internal circuitry operations are not stable. When µPD17215 PD17215 is reset, the following initialization takes place: (1) Program counter is reset to 0. (2) Flags in the register file are initialized to their default values (for the default values, refer to Fig. 11-1 Register Files). (3) The default value (0320H 0320H) is written to the data buffer (DBF). (4) The hardware peripherals are initialized. (5) The system clock (fx) stops oscillation. When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 MHz) later. Fig. 9-1 Reset Operation by RESET Input Wait (about 16 ms at 4 MHz) Starts from address 0H RESET Operation mode or standby mode HALT mode Operation mode Oscillation stops 9.2 Reset by Watchdog Timer (Connect RESET and WDOUT pins) When the watchdog timer operates during program execution, a low level is output to the WDOUT pin, and the program counter is reset to 0. If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. Program so that the watchdog timer is reset at intervals of within 340 ms (at fx = 4 MHz) (set the WDTRES flag). 50 µPD17215 PD17215, 17216, 17217, 17218 9.3 Reset by Stack Pointer (Connect RESET and WDOUT pins) When the value of the stack pointer reaches 6H or 7H during program execution, a low level is output to the WDOUT pin, and the program counter is reset to 0. If the nesting level of the interrupt or subroutine call exceeds 5 (stack over flow), or if the return instruction is executed without correspondence between CALL and return (RET) instructions established, then regardless of a stack level of 0 (stack underflow), the program can be restarted from address 0H. Table 9-1 Status of Each Hardware After Reset Hardware Program Counter (PC) RESET Input During Standby Mode RESET Input During Operation Input/output Input Input 0 0 General-purpose data memory (Except DBF, port register) Retains previous status Undefined DBF 0320H 0320H 0320H 0320H System register (SYSREG) 0 0 WR Data Memory (RAM) 0000H 0000H Output latch Port 0000H 0000H Retains previous status Undefined Control Register 8-bit Timer Refer to Fig. 11-1 Register Files 00H 00H Modulo register (TMM) Remote Controller Carrier Generator Counter (TMC) FFH FFH NRZ high level period setting modulo register (NRZHTMM) Retains previous status Undefined 00H 00H NRZ low level period setting modulo register (NRZLTMM) Basic Interval Timer/Watchdog Timer Counter 10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) The low-voltage detector circuit outputs a low level from the WDOUT pin for initialization (reset) to prevent program hangup that may take place when the batteries are replaced, if the circuit detects a low voltage. A drop in the supply voltage is detected if the status of TA = -10 to +85°C, VDD = 0.8 to 2.2 V lasts for 1 ms or longer. Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. Although the voltage at which the the reset function is effected ranges from 0.8 to 2.2 V, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 8 to 32 µs. Note that some oscillators stop oscillating before the reset function is effected. The low-voltage detector circuit can be set arbitrarily by the mask option. 51 µPD17215 PD17215, 17216, 17217, 17218 Caution: Connect a diode and a capacitor to the RESET pin as shown below to stabilize the operation. Microcomputer VDD RESET WDOUT Remark: In this figure, the RESET pin is connected to a pull-up resistor by the mask option. 11. ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives When developing the µ PD17215 PD17215 program, mask options must be specified by using mask option directives in the program. The RESET pin for µ PD17215 PD17215 requires a mask option to be specified. 11.1.1 OPTION and ENDOP directives That portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block. This block is described in the following format: Description: Symbol [Label: ] 11.1.2 Mnemonic Operand OPTION : : : ENDOP Comment [;Comment] Mask option definition directives Table 19-1 lists the directives that can be used in the mask option definition block. Here is an example of mask option definition: Description format: Symbol field Mnemonic field Operand field Comment field OPTION OPTRES PULLUP ; RESET pin has pull-up resistors. OPTPOC USEPOC ; Internal low-voltage detector circuit ENDOP 52 µPD17215 PD17215, 17216, 17217, 17218 Table 11-1 Mask Option Definition Directives Name Directive Operands 1st Operand 2nd Operand 3rd Operand 4th Operand Mask option of RESET RESET OPTRES 1 PULLUP (w/pull-up resistor) OPEN (w/o pull-up resistor) USEPOC (low-voltage detector circuit provided) POC OPTPOC 1 NOUSEPOC (low-voltage detector circuit not provided) 11.2 Reserved Symbols The symbols defined by the µ PD17215 PD17215 device file are listed in Table 11-2. The defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 Register file The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK and POKE instructions through the window register (WR). Fig. 11-1 shows the register file. 11.2.2 Registers and ports on data memory The names of the registers assigned at addresses 00H through 7FH on the data memory and the names of ports assigned to address 70H and those that follow, and system register names are defined. Fig. 11-2 shows the data memory configuration. 11.2.3 Peripheral hardware The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 11-3 shows the peripheral hardware. 53 µPD17215 PD17215, 17216, 17217, 17218 Table 11-2 Reserved Symbols (1/2) Symbol Name Attribute Value R/W Description DBF3 0.0CH R/W Bits 15-12 of data buffer DBF2 MEM 0.0DH R/W Bits 11-8 of data buffer DBF1 MEM 0.0EH R/W Bits 7-4 of data buffer DBF0 MEM 0.0FH R/W Bits 3-0 of data buffer AR3 MEM 0.74H R Bits 15-12 of address register AR2 MEM 0.75H R/W Bits 11-8 of address register AR1 MEM 0.76H R/W Bits 7-4 of address register AR0 MEM 0.77H R/W Bits 3-0 of address register WR MEM 0.78H R/W Window register BANK MEM 0.79H R Bank register IXH MEM 0.7AH R Bits 11-8 of index register MPH MEM 0.7AH R Bits 7-4 of memory pointer MPE FLG 0.7AH.3 R/W Memory pointer enable flag IXM MEM 0.7BH R/W Bits 7-4 of index register MPL MEM 0.7BH R/W Bits 3-0 of memory pointer IXL MEM 0.7CH R/W Bits 3-0 of index register RPH MEM 0.7DH R Bits 7-4 of register pointer RPL MEM 0.7EH R/W Bits 3-0 of register pointer PSW MEM 0.7FH R/W Program status word BCD FLG 0.7EH.0 R/W BCD flag CMP FLG 0.7FH.3 R/W Compare flag CY FLG 0.7FH.2 R/W Carry flag Z FLG 0.7FH.1 R/W Zero flag IXE FLG 0.7FH.0 R/W Index register enable flag P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B P0C0 FLG 0.72H.0 R/W Bit 0 of port 0C P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C P0C2 FLG 0.72H.2 R/W Bit 2 of port 0C P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C P0D0 FLG 0.73H.0 R/W Bit 0 of port 0D P0D1 FLG 0.73H.1 R/W Bit 1 of port 0D P0D2 FLG 0.73H.2 R/W Bit 2 of port 0D P0D3 54 MEM FLG 0.73H.3 R/W Bit 3 of port 0D µPD17215 PD17215, 17216, 17217, 17218 Table 11-2 Reserved Symbols (2/2) Symbol Name Attribute Value R/W Description P0E0 FLG 0.6FH.0 R/W Bit 0, port 0E P0E1 FLG 0.6FH.1 R/W Bit 1, port 0E P0E2 FLG 0.6FH.2 R/W Bit 2, port 0E P0E3 FLG 0.6FH.3 R/W Bit 3, port 0E SP MEM 0.81H R/W Stack pointer SYSCK FLG 0.82H.0 R/W Selects system clock WDTRES FLG 0.83H.3 R/W Resets watchdog timer BTMCK FLG 0.83H.2 R/W Selects basic interval timer mode BTMRES FLG 0.83H.1 R/W Resets basic interval timer mode INT FLG 0.8FH.0 R NRZBF FLG 0.91H.0 R/W NRZ buffer data NRZ FLG 0.92H.0 R/W NRZ data P0EBPU0 FLG 0.97H.0 R/W Pull-up resistor setting flag for P0E0 P0EBPU1 FLG 0.97H.1 R/W Pull-up resistor setting flag for P0E1 P0EBPU2 FLG 0.97H.2 R/W Pull-up resistor setting flag for P0E2 P0EBPU3 FLG 0.97H.3 R/W Pull-up resistor setting flag for P0E3 IEG FLG 0.9FH.0 R/W Selects interrupt edge for INT pin P0EBIO0 FLG 0.0A7H.0 R/W I/O setting flag, P0E0 P0EBIO1 FLG 0.0A7H.1 R/W I/O setting flag, P0E1 P0EBIO2 FLG 0.0A7H.2 R/W I/O setting flag, P0E2 P0EBIO3 FLG 0.0A7H.3 R/W I/O setting flag, P0E3 IPBTM FLG 0.0AFH.2 R/W Interrupt enable flag of basic interval timer IP FLG 0.0AFH.1 R/W INT interrupt enable flag IPTM FLG 0.0AFH.0 R/W 8-bit timer interrupt enable flag TMEN FLG 0.0B3H.3 R/W 8-bit timer count enable flag TMRES FLG 0.0B3H.2 R/W 8-bit timer reset flag TMCK1 FLG 0.0B3H.1 R/W Selects clock source for 8-bit timer TMCK0 FLG 0.0B3H.0 R/W Selects clock source for 8-bit timer IRQBTM FLG 0.0BDH.0 R/W Basic interval timer interrupt request flag IRQ FLG 0.0BEH.0 R/W INT interrupt request flag IRQTM FLG 0.0BFH.0 R/W 8-bit timer interrupt request flag TMC DAT 05H R 8-bit counter TMM DAT 06H W 8-bit modulo register NRZLTMM DAT 03H R/W NRZ low level period setting modulo register NRZHTMM DAT 04H R/W NRZ high level period setting modulo register AR DAT 40H R/W Address register INT pin status 55 µPD17215 PD17215, 17216, 17217, 17218 Fig. 11-1 Register Files (1/2) Column Address 0 1 Row Address 2 * * 3 * 4 * * Bit 3 0 0 1 0 0 * 7 * * 0 BTMCK 0 0 6 0 WDTRES 0 Bit 2 0 5 0 BTMRES 0 SP Bit 1 Bit 0 1 SYSCK 0 0 0 Bit 3 0 0 0 P0EBPU3 0 Bit 2 0 0 0 0 P0EBPU2 0 Bit 1 1 0 0 0 0 0 P0EBPU1 0 NRZ 0 P0EBPU0 0 Bit 0 NRZBF 0 Bit 3 P0EBIO2 0 Bit 1 P0EBIO1 0 Bit 0 2 P0EBIO3 0 Bit 2 P0EBIO0 0 Bit 3 TMRES 0 Bit 1 TMCK1 0 Bit 0 3 TMEN 1 Bit 2 TMCK0 0 *: On reset Fig. 11-2 Data Memory Configuration 0 1 2 3 4 5 6 Column address 7 8 9 A 0 B C D E F DBF3DBF2DBF1DBF0 DBF Row address 1 2 3 4 5 P0E0 -P0E3 6 7 AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW System register P0D 0 -P0D3 P0C0 -P0C3 P0B 0 -P0B 3 P0A 0 -P0A3 56 µPD17215 PD17215, 17216, 17217, 17218 Fig. 11-1 Register Files (2/2) Column Address Row Address 8 9 * A B * * C * D * E * F * * Bit 3 Bit 2 0 0 Bit 1 0 0 INT P Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 1 0 Bit 0 0 0 IEG 0 0 0 Bit 3 2 IPBTM 0 Bit 2 Bit 1 IP 0 Bit 0 IPTM 0 Bit 3 3 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 IRQBTM 0 Bit 0 IRQ 0 IRQTM 1 *: On reset P: When INT pin is high level, 1 or when INT pin is low level, 0. Table 11-3 Peripheral Hardwre Name Address Valid Bit Description TMC 05H 8 8-bit timer count register TMM 06H 8 8-bit timer modulo register NRZLTMM 03H 8 Low level period setting modulo register for remote controller carrier generation NRZHTMM 04H 8 High level period setting modulo register for remote controller carrier generation AR 40H 16 Address register 57 µPD17215 PD17215, 17216, 17217, 17218 12. INSTRUCTION SET 12.1 Instruction Set Outline b15 0 b14-b11 1 BIN. HEX. 0000 0 ADD r, m ADD m, #n4 0001 1 SUB r, m SUB m, #n4 0010 2 ADDC r, m ADDC m, #n4 0011 3 SUBC r, m SUBC m, #n4 0100 4 AND r, m AND m, #n4 0101 5 XOR r, m XOR m, #n4 0110 6 OR r, m OR m, #n4 INC AR INC IX MOVT DBF, @AR BR @AR CALL @AR RET RETSK EI DI 0111 7 RETI PUSH AR POP AR GET DBF, p PUT p, DBF PEEK WR, rf POKE rf, WR RORC r STOP s HALT h NOP 1000 LD r, m ST m, r 1001 9 SKE m, #n4 SKGE m, #n4 1010 A MOV @r, m MOV m, @r 1011 B SKNE m, #n4 SKLT m, #n4 1100 C BR addr (Page 0) CALL addr 1101 D BR addr (Page 1) MOV m, #n4 1110 E BR addr (Page 2) SKT m, #n 1111 58 8 F BR addr (Page 3) SKF m, #n µPD17215 PD17215, 17216, 17217, 17218 12.2 Legend AR : Address register ASR : Address stack register specified by stack pointer addr : Program memory address (lower 11 bits) BANK : Bank register CMP : Compare register CY : Carry flag DBF : Data buffer h : Halt releasing condition INTEF : Interrupt enable flag INTR : Register automatically saved to stack in case of interrupt INTSK : Interrupt stack register IX : Index register MP : Data memory row address pointer MPE m : Memory pointer enable flag : Data memory address specified by mR, mC mR : Data memory row address (high) mC : Data memory column address (low) n : Bit position (4 bits) n4 : Immediate data (4 bits) PAGE : Page (bit 11 and 12 of program counter) PC : Program counter p : Peripheral address pH : Peripheral address (higher 3 bits) pL : Peripheral address (lower 4 bits) r : General register column address rf : Register file address rfR : Register file address (higher 3 bits) rfC : Register file address (lower 4 bits) SP : Stack pointer s : Stop releasing condition WR : Window register (×) : Contents addressed by × 59 µPD17215 PD17215, 17216, 17217, 17218 12.3 List of Instruction Sets Instruction Code Group Mnemonic Operand Operation OP Code Operand r, m (r) (r) + (m) 00000 mR mC r m, #n4 (m) (m) + n4 10000 mR mC n4 r, m (r) (r) + (m) + CY 00010 mR mC r m, #n4 (m) (m) + n4 + CY 10010 mR mC n4 AR AR AR +1 00111 000 1001 0000 IX IX IX +1 00111 000 1000 0000 r, m (r) (r) ­ (m) 00001 mR mC r m, #n4 (m) (m) ­ n4 10001 mR mC n4 r, m (r) (r) ­ (m) ­ CY 00011 mR mC r m, #n4 (m) (m) ­ n4 ­ CY 10011 mR mC n4 r, m (r) (r) (m) 00110 mR mC r m, #n4 (m) (m) n4 10110 mR mC n4 r, m (r) (r) (m) 00100 mR mC r m, #n4 (m) (m) n4 10100 mR mC n4 r, m (r) (r) (m) 00101 mR mC r m, #n4 (m) (m) n4 10101 mR mC n4 SKT m, #n CMP 0, if (m) n = n, then skip 11110 mR mC n SKF m, #n CMP 0, if (m) n = 0, then skip 11111 mR mC n SKE m, #n4 (m)-n4, skip if zero 01001 mR mC n4 SKNE m, #n4 (m)-n4, skip if not zero 01011 mR mC n4 SKGE m, #n4 (m)-n4, skip if not borrow 11001 mR mC n4 SKLT m, #n4 (m)-n4, skip if borrow 11011 mR mC n4 RORC r 00111 000 0111 r LD r, m (r) (m) 01000 mR mC r ST m, r (m) (r) 11000 mR mC r @r, m if MPE = 1 : (MP, (r) (m) if MPE = 0 : (BANK, mR, (r) (m) 01010 mR mC r m, @r if MPE = 1 : (m) (MP, (r) if MPE = 0 : (m) (BANK, mR, (r) 11010 mR mC r m, #n4 (m) n4 11101 mR mC n4 DBF, @AR SP SP ­ 1, ASR PC, PC AR DBF (PC), PC ASR, SP SP + 1 00111 000 0001 0000 ADD Addition ADDC INC SUB Subtraction SUBC OR Logical AND XOR Judge Compare Rotate Transfer MOV MOVT 60 CY (r)b3 (r)b2 (r)b1 (r)b0 µPD17215 PD17215, 17216, 17217, 17218 Instruction Code Group Mnemonic Operand Operation OP Code Operand PUSH AR SP SP ­ 1, ASR AR 00111 000 1101 0000 POP AR AR ASR, SP SP +1 00111 000 1100 0000 PEEK WR, rf WR (rf) 00111 rfR 0011 rfC POKE rf, WR (rf) WR 00111 rfR 0010 rfC GET DBF, p (DBF) (p) 00111 pH 1011 pL PUT p, DBF (p) (DBF) 00111 pH 1010 pL Transfer µPD17215 PD17215 µPD17218 PD17218 PC10­0 addr, PAGE 1 01101 01100 PC10­0 addr, PAGE 1 01101 01110 01100 PC10­0 addr, PAGE 1 01101 PC10­0 addr, PAGE 2 01110 PC10­0 addr, PAGE 3 addr 01100 PC10­0 addr, PAGE 0 BR PC10­0 addr, PAGE 0 PC10­0 addr, PAGE 2 µPD17217 PD17217 Branch 01100 PC10­0 addr, PAGE 0 µPD17216 PD17216 PC10­0 addr 01111 addr @AR PC AR 00111 addr SP SP ­ 1, ASR PC, PC10­0 addr, PAGE 0 11100 @AR SP SP ­ 1, ASR PC, PC AR 00111 000 0101 0000 RET PC ASR, SP SP +1 00111 000 1110 0000 RETSK PC ASR, SP SP +1 and skip 00111 001 1110 0000 RETI PC ASR, INTR INTSK, SP SP +1 00111 100 1110 0000 EI INTEF 1 00111 000 1111 0000 DI INTEF 0 00111 001 1111 0000 CALL Subroutine Interrupt 000 0100 0000 addr STOP Other s STOP 00111 010 1111 s HALT h HALT 00111 011 1111 h No operation 00111 100 1111 0000 NOP 61 µPD17215 PD17215, 17216, 17217, 17218 12.4 Assembler (AS17K AS17K) Built-In Macro Instruction Legend flag n: FLG type symbol < >: Contents in < Mnemonic > can be omitted Operand Operation n Built-in macro SKTn flag 1, .flag n if (flag 1) to (flag n) = all "1", then skip 1n4 SKFn flag 1, .flag n if (flag 1) to (flag n) = all "0", then skip 1n4 SETn flag 1, .flag n (flag 1) to (flag n) 1 1n4 CLRn flag 1, .flag n (flag 1) to (flag n) 0 1n4 NOTn INITFLG BANKn 62 flag 1, .flag n if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 flag 1, if description = NOT flag n, then (flag n) 0 ··· if description = flag n, then (flag n) 1 (BANK) n 1n4 1n4 n = 0, 1 µPD17215 PD17215, 17216, 17217, 17218 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Item Symbol Conditions Ratings Unit ­0.3 to +7.0 V Supply Voltage VDD Input Voltage VI ­0.3 to VDD+0.3 V Output Voltage VO ­0.3 to VDD+0.3 V Peak value ­36.0 mA Effective value ­24.0 mA Peak value ­7.5 mA Effective value ­5.0 mA Peak value ­22.5 mA Effective value ­15.0 mA REM pin High-Level Output Current* IOH 1 pin (P0E pin) Total of P0E pins 1 pin (P0C, P0D, P0E, REM or WDOUT pin) 7.5 mA Effective value 5.0 mA Total of P0C, P0D, Peak value 22.5 mA WDOUT pins Effective value 15.0 mA Peak value 30.0 mA Effective value Low-Level Output Current* Peak value 20.0 mA IOL Total of P0E pins Operating Ambient Temperature TA ­40 to +85 °C Storage Temperature Tstg ­65 to +150 °C Power Dissipation Pd 180 mW TA = 85 °C *: Calculate effective value by this expression: [Effetive value] = [Peak value] × Duty Caution: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. 63 µPD17215 PD17215, 17216, 17217, 17218 Recommended Operating Ranges (VDD = 2.0 to 5.5 V, TA = ­40 to +85°C) Item Symbol VDD2 Supply Voltage TYP. MAX. 3.0 5.5 High-speed mode (Instruction execution time: 4 µs) fx = 1 MHz MIN. 2.0 VDD1 Conditions 2.2 3.0 5.5 High-speed mode (Instruction execution time: 2 µs) 3.5 5.0 5.5 High-speed mode (Instruction execution time: 16 µs) Ordinary mode (Instruction execution time: 8 µs) fx = 4 MHz VDD3 VDD4 Unit fx = 8 MHz V Oscillation Frequency fx 1.0 4.0 8.0 MHz Operating Temperature Ta ­40 +25 +85 °C Low-Voltage Detector Circuit* (Mask Option) TCY 32 µS Ta = ­10 to +85°C 8 *: Reset if the status of VDD = 0.8 to 2.2 V lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected (when the RESET pin and WDOUT pin are connected). Some oscillators stop oscillating before the reset function is effected. f X vs V DD (MHz) 10 9 8 7 6 System clock: f X (Ordinary mode) 5 4 3 Operation guaranteed area 2 1 0.4 0 2 2.2 3 3.5 4 5 5.5 6 (V) Supply voltage: V DD Remark: The region indicated by the broken line in the above figure is the guaranteed operating range in the high-speed mode. 64 µPD17215 PD17215, 17216, 17217, 17218 System Clock Oscillator Circuit Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 5.5 V) Recommended Constants Resonator X IN X OUT Ceramic Item Conditions Oscillation stabilization time*2 TYP. MAX. Unit 1.0 Oscillation frequency (fx)*1 MIN. 4.0 8.0 MHz 4 ms After VDD reached MIN. in oscillation voltage range * 1: The oscillation frequency only indicates the oscillator characteristics. 2: The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution: To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: · Keep wiring length as short as possible. · Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. · Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. · Do not extract signals from the oscillator circuit. External circuit example XIN XOUT R1 C3 C2 65 µPD17215 PD17215, 17216, 17217, 17218 Ceramic resonators Manufacturer Product Name Recommended Circuit Constants Oscillation Voltage Range C1 (pF) C2 (pF) R1 (k) MIN. (V) MAX. (V) CSB1000J CSB1000J 100 100 4.7 2.0 5.5 CSA2.00MG 30 30 ­ 2.0 5.5 CSA4.00MG 30 30 ­ 2.0 5.5 CSA6.00MG 30 30 ­ 2.0 5.5 CSA8.00MTZ 00MTZ 30 30 ­ 2.1 5.5 CST2.00MG ­ ­ ­ 2.0 5.5 CST4.00MGW 00MGW ­ ­ ­ 2.0 5.5 CST6.00MGW 00MGW ­ ­ ­ 2.0 5.5 CST8.00MTW 00MTW ­ ­ ­ 2.1 5.5 KBR-1000Y/F KBR-1000Y/F 100 100 ­ 2.0 5.5 KBR-2.0MS 47 47 ­ 2.0 5.5 KBR-4.0MSA 33 33 ­ 2.0 5.5 KBR-4.0MKS/MWS ­ ­ ­ 2.0 5.5 KBR-6.0MSA 33 33 ­ 2.2 5.5 KBR-6.0MKS/MWS ­ ­ ­ 2.0 5.5 KBR-8.0M 33 33 ­ 2.2 5.5 PBRC2.00A 47 47 ­ 2.0 5.5 PBRC3.58A 33 33 ­ 2.0 5.5 PBRC4.00A 33 33 ­ 2.0 5.5 PBRC6.00A 33 33 ­ 2.0 5.5 PBRC8.00A 33 33 ­ 2.0 5.5 FCR2.0M3 33 33 ­ 2.0 5.5 FCR2.0MC3 ­ ­ ­ 2.0 5.5 FCR4.0M5 33 33 ­ 2.0 5.5 FCR4.0MC5 ­ ­ ­ 2.0 5.5 CCR4.0MC3 ­ ­ ­ 2.0 5.5 Matsushita Electronics Com- EFOEC2004A4 EFOEC2004A4 ­ ­ ­ 2.0 5.5 ponents Co., Ltd. EFOEC4004A4 EFOEC4004A4 ­ ­ ­ 2.0 5.5 EFOEC6004A4 EFOEC6004A4 ­ ­ ­ 2.0 5.5 EFOEC8004A4 EFOEC8004A4 ­ ­ ­ 2.0 5.5 EFOEN2004A4 EFOEN2004A4 33 33 ­ 2.0 5.5 EFOEN4004A4 EFOEN4004A4 33 33 ­ 2.0 5.5 EFOEN6004A4 EFOEN6004A4 33 33 ­ 2.0 5.5 EFOEN8004A4 EFOEN8004A4 33 33 ­ 2.0 5.5 Murata Mfg, Co., Ltd. Kyocela Corp. TDK Corp. 66 µPD17215 PD17215, 17216, 17217, 17218 DC Characteristics (VDD = 2.0 to 5.5 V, TA = ­40 to +85°C) Item Symbol Conditions MIN. TYP. MAX. Unit VIH1 0.8VDD VDD V VIH2 P0A, P0B 0.7VDD VDD V VIH3 P0E 2.0 V VDD < 3.0 V VDD­0.3 VDD V VIH4 P0E 3.0 V VDD 5.5 V VDD­0.5 VDD V VIH5 XIN 0.8VDD VDD V VIL1 RESET, INT pin 0 0.2VDD V VIL2 P0A, P0B 0