PD17015 PD17015GS- U10416EJ1V0DS00 AS17K 0000H 05F7H 07FFH 05F8H 74H-7FH 0000B - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD17015 4-BIT SINGLE-CHIP MICROCONTROLLER FOR PORTABLE RADIOS The µPD17015 is a super

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD17015 PD17015 4-BIT SINGLE-CHIP MICROCONTROLLER FOR PORTABLE RADIOS The µPD17015 PD17015 is a super low-voltage 4-bit single-chip microcontroller for digital tuning applications. It features a prescaler that can operate at frequencies up to 220 MHz, a PLL synthesizer, and an LCD controller/driver, all configured in one chip. Since, for its CPU, the µPD17015 PD17015 adopts a 17K architecture which allows data memory to be manipulated directly without accumulators, programming efficiency is enhanced. Each instruction is 16 bits (one word) long. Since this microcontroller can operate at low voltages (VDD = 1.8 to 3.6 V), it is ideal for controlling portable, batterypowered units such as portable radios, headphone stereo sets, and radio-cassette players. FEATURES · · · · · 17K architecture : General registers Program memory (ROM) : 3K bytes (1528 × 16 bits) Data memory (RAM) : 97 × 4 bits General-purpose I/O ports : 12 Minimum required peripheral hardware is built into the chip. : 9 segments × 4 commons · LCD controller/driver · PLL frequency synthesizer and 220-MHz (MAX.) prescaler · Clock generator port : VDD = 1.8 to 3.6 V (TA = ­10 to +50 °C) · Low-voltage operation ORDERING INFORMATION Part number Package µPD17015GS- PD17015GS-×××-GJG 38-pin plastic shrink SOP (300 mil) Remark ××× is a ROM code number. The information in this document is subject to change without notice. Document No. U10416EJ1V0DS00 U10416EJ1V0DS00 (1st edition) Date Published September 1995 P Printed in Japan Major changes in this revision are indicated by stars (5) in the margins. © 1995 µPD17015 PD17015 FUNCTION OVERVIEW Item Function Program memory (ROM) General-purpose data memory · 97 × 4 bits Instruction execution time · 53.3 µs (when 75 kHz crystal is used) Stack levels · 1 level General-purpose ports 5 · 3K bytes (1528 × 16 bits) · I/O · Input only : 2 ports : 3 ports 12 · Output only : 7 ports BEEP output LCD controller/driver 5 1 (3 kHz) · 9 segments, 4 commons · 1/4 duty, 1/2 bias, frame frequency 62.5 Hz, driving voltage 3.0 V (TYP.) Timers 2 channels Reset Basic timer 0 : 125 ms Basic timer 1 : 5 ms · Power-on reset · Reset with the CE pin (by switching the CE pin from low to high) · Power-failure detection function PLL Frequency division frequency method synthesizer 2 · Direct division method · Pulse swallow method (VCOL pin (MF mode) : 8 MHz MAX.) (VCOL pin (HF mode) : 55MHz MAX.) (VCOH pin (VHF mode) : 220MHz MAX.) Reference frequency 1, 3, 5, or 25 kHz, selected by software. Charge pump Error-out output: 1 Phase comparator An unlocked state can be detected by software. Supply voltage Package 5 2 · 1.8 to 3.6 V (TA = ­10 to +50 °C) · 1.9 to 3.6 V (TA = ­20 to +50 °C) 38-pin plastic shrink SOP (0.65-mm pitches, 300 mil) µPD17015 PD17015 BLOCK DIAGRAM P0A0 LCD0 P0A1 LCD1 P0A P0A2 RF LCD2 P0A3 RAM 97 × 4 bits LCD3 LCD4 P0B0 P0B1 SYSTEM REGISTER LCD5 LCD Controller/ Driver P0B P0B2 LCD6 LCD7 ALU LCD8 P0C0 COM0 P0C1 Instruction Decoder P0C P0C2 COM1 COM2 P0C3 COM3 Beep P0OD0/BEEP ROM 1528 × 16 bits VLCD0 Voltage Doubler P0D EO PLL Stack 1 × 11 bits Basic Timer 1 CPU XIN XOUT CAP0 CAP1 Program Counter 11 bits Basic Timer 0 VLCD1 OSC Peripheral VCOH VCOL PLL Voltage Regulator Reset VREG VDD CE GND 3 µPD17015 PD17015 PIN CONFIGURATION (TOP VIEW) 38-pin plastic shrink SOP (300 mil) 38 P0B1 P0C0 2 37 P0B0 P0C1 3 36 VLCD0 P0C2 4 35 CAP0 P0C3 5 34 CAP1 P0D0/BEEP 6 33 VLCD1 P0A0 7 32 COM0 P0A1 8 31 COM1 P0A2 9 30 COM2 P0A3 10 29 COM3 CE 11 28 LCD0 XOUT 12 27 LCD1 XIN 13 26 LCD2 VDD 14 25 LCD3 GND 15 24 LCD4 EO 16 23 LCD5 VREG 17 22 LCD6 VCOH 18 21 LCD7 VCOL BEEP 1 19 20 LCD8 : BEEP output CAP0, CAP1 : Capacitor connection for LCD drive voltage CE : Chip enable input µ PD17015GS- PD17015GS-×××-GJG P0B2 P0B0 - P0B2 : Port 0B (input) P0C0 - P0C3 : Port 0C (output) P0D0 : Port 0D (output) VCOH, VCOL : Local oscillation input COM0 - COM3: LCD common output VDD : Main power supply EO : Error out VLCD0, VLCD1 : LCD power supply GND : Ground VREG : Voltage regulator output for PLL XIN, XOUT : Crystal connection LCD0 - LCD8 : LCD segment output P0A0, P0A1 4 : Port 0A (I/O) P0A2, P0A3 : Port 0A (output) µPD17015 PD17015 CONTENTS 1. PIN FUNCTIONS . 8 1.1 12 NOTES ON USE OF THE CE PIN . 13 PROGRAM MEMORY (ROM) . 14 OUTLINE OF PROGRAM MEMORY . 14 2.2 PROGRAM MEMORY CONFIGURATION . 14 2.3 PROGRAM COUNTER . 15 2.4 PROGRAM FLOW . 15 2.5 NOTES ON USE OF PROGRAM MEMORY . 16 ADDRESS STACK REGISTER (ASR) . 17 3.1 OUTLINE AND CONFIGURATION OF ADDRESS STACK REGISTER . 17 3.2 ADDRESS STACK REGISTER OPERATION . 17 3.3 NOTES ON USE OF ADDRESS STACK REGISTER . 17 DATA MEMORY (RAM) . 18 4.1 OUTLINE OF DATA MEMORY . 18 4.2 CONFIGURATION AND FUNCTIONS OF DATA MEMORY . 18 4.3 DATA MEMORY ADDRESSING . 21 4.4 5. HANDLING UNUSED PINS . 2.1 4. 9 1.4 3. 8 EQUIVALENT CIRCUIT OF EACH PIN . 1.3 2. PIN FUNCTIONS . 1.2 NOTES ON USING DATA MEMORY . 21 SYSTEM REGISTER (SYSREG) . 22 5.1 22 PROGRAM STATUS WORD (PSWORD) . 23 5.3 6. OUTLINE OF SYSTEM REGISTER . 5.2 NOTES ON USING SYSTEM REGISTER . 24 GENERAL-PURPOSE REGISTER (GR) . 25 6.1 25 GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS . 25 6.3 7. OUTLINE OF GENERAL-PURPOSE REGISTER . 6.2 NOTES ON USING GENERAL-PURPOSE REGISTER . 26 ARITHMETIC LOGIC UNIT (ALU) BLOCK . 27 7.1 OVERVIEW . 27 7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK . 28 7.3 ALU OPERATIONS . 28 7.4 NOTES ON USING THE ALU . 31 5 µPD17015 PD17015 8. 32 8.1 OVERVIEW . 32 8.2 RELATIONSHIP BETWEEN THE PERIPHERAL HARDWARE AND DATA BUFFER . 34 8.3 NOTES ON USING THE DATA BUFFER . 34 GENERAL-PURPOSE PORTS . 35 9.1 9. DATA BUFFER (DBF) . OVERVIEW . 35 9.2 GENERAL-PURPOSE I/O PORTS (P0A0 AND POA1 PINS) . 36 9.3 GENERAL-PURPOSE INPUT PORT (P0B0 TO P0B2 PINS) . 38 9.4 GENERAL-PURPOSE OUTPUT PORTS (P0A2, P0A3, P0C0 TO P0C3, AND P0D0 PINS) . 39 10. TIMERS . 41 10.1 OVERVIEW . 41 10.2 BASIC TIMERS 0 AND 1 . 41 11. PLL FREQUENCY SYNTHESIZER . 50 11.1 GENERAL . 50 11.2 INPUT SWITCHING BLOCK AND PROGRAMMABLE DIVIDER . 51 11.3 REFERENCE FREQUENCY GENERATOR . 56 11.4 PHASE COMPARATOR (-DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK . 57 11.5 PLL DISABLED STATE . 61 11.6 PLL FREQUENCY SYNTHESIZER USE . 61 11.7 STATE AT RESET . 64 12. BEEP . 65 12.1 CONFIGURATION AND FUNCTIONS . 65 12.2 STATE AT RESET . 66 13. LCD CONTROLLER/DRIVER . 67 13.1 OVERVIEW . 67 13.2 LCD DRIVING VOLTAGE GENERATION BLOCK . 68 13.3 LCD SEGMENT REGISTER . 69 13.4 TIMING CONTROL BLOCKS FOR OUTPUTTING COMMON SIGNAL AND SEGMENT SIGNAL . 71 13.5 COMMON SIGNAL AND SEGMENT SIGNAL OUTPUT WAVEFORMS . 72 13.6 USING THE LCD CONTROLLER/DRIVER . 74 13.7 STATE AT RESET . 76 14. STANDBY . 77 14.1 14.2 HALT FUNCTION . 79 14.3 CLOCK-STOP FUNCTION . 83 14.4 DEVICE OPERATION IN THE HALT AND CLOCK-STOP STATES . 86 14.5 PIN PROCESSING CAUTIONS IN HALT STATE AND CLOCK-STOP STATE . 87 14.6 6 STANDBY FUNCTIONS . 77 DEVICE OPERATION CONTROL BY THE CE PIN . 89 µPD17015 PD17015 15. RESET . 91 15.1 OUTLINE OF RESET FUNCTION . 91 15.2 POWER-ON RESET . 92 15.3 CE RESET . 95 15.4 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET . 99 15.5 POWER FAILURE DETECTION . 101 16. INSTRUCTION SET . 106 16.1 LIST OF INSTRUCTION SET . 106 16.2 INSTRUCTIONS . 107 16.3 ASSEMBLER (AS17K AS17K) BUILT-IN MACRO INSTRUCTIONS . 109 17. RESERVED SYMBOLS . 110 17.1 SYSTEM REGISTER (SYSREG) . 110 17.2 DATA BUFFER (DBF) . 110 17.3 LCD SEGMENT REGISTER . 111 17.4 PORT REGISTER . 111 17.5 PERIPHERAL CONTROL REGISTER . 112 17.6 PERIPHERAL HARDWARE REGISTER . 112 17.7 OTHERS . 112 18. ELECTRICAL CHARACTERISTICS . 113 19. PACKAGE DRAWING . 115 20. RECOMMENDED SOLDERING CONDITIONS . 116 APPENDIX DEVELOPMENT TOOLS. 117 7 µPD17015 PD17015 1. PIN FUNCTIONS 1.1 PIN FUNCTIONS Pin No. 37 38 1 P0B0 | P0B2 2 | 5 P0C0 | P0C3 6 P0D0/ BEEP Output type At power-on reset 3-bit input port. Input with a pulldown resistor Input 4-bit CMOS output port CMOS push-pull Low-level output 1-bit general-purpose output port and BEEP signal output CMOS push-pull Low-level output CMOS push-pull Input (P0A0, P0A1) Symbol Function · P0D0 · 1-bit output port · BEEP · 3-kHz BEEP output 7 | 10 P0A0 | P0A3 2-bit I/O and output ports · P0A0, P0A1 · 2-bit I/O port · Input or output mode can be specified in units of bits. Low-level output (P0A2, P0A3) · P0A2, P0A3 · 2-bit output port Input pin for the µPD17015 PD17015 operation selection and reset signal - 11 12 13 XOUT XIN Pins for connecting the crystal (75 kHz) for system clock oscillation. CMOS push-pull (XOUT) Load capacity: CI = 12 pF, CO = 33 pF 14 VDD Main power supply pin The pin supplies a voltage of 1.8 to 3.6 V (TA = ­10 to +50 °C) to enable all functions. Note that the voltage applied to each of the other pins must not exceed the voltage applied to the VDD pin. - - 15 GND Ground pin - - 16 EO 17 5 CE VREG Output from the charge pump of the PLL frequency synthesizer. Output pin for the PLL voltage regulator. Connect this pin to GND through a 0.1-µF capacitor. CMOS tristate output Input - Floating - - - Floating VREG (17) 0.1 µ F 18 19 8 VCOH VCOL Local PLL oscillator frequency input µPD17015 PD17015 1.2 EQUIVALENT CIRCUIT OF EACH PIN (1) P0A (P0A0, P0A1): (I/O) VDD VDD (2) P0B (P0B0, P0B1, P0B2): (Input) VDD High on-state resistance (3) P0A (P0A2, P0A3) P0C (P0C0, POC1, POC2, POC3) P0D (P0D0, BEEP) (Output) LCD0 - LCD8 EO VDD 9 µPD17015 PD17015 (4) COM0 - COM3: (Output) VLCD0 VLCD1 (5) VCOL: (Input) High on-state resistance VDD High on-state resistance VDD 10 µPD17015 PD17015 (6) VCOH: (Input) High on-state resistance VDD VDD (7) CE: (Schmitt-triggered input) VDD (8) XOUT: (Output), XIN: (Input) High on-state resistance VDD VDD XIN XOUT 11 µPD17015 PD17015 5 1.3 HANDLING UNUSED PINS When connecting unused pins, the following conditions and handling are recommended: Table 1-1 Handling Unused Pins Pin I/O type Recommended handling when unused P0B0-P0B2 Input Connect each pin to ground through a resistorNote 1. P0C0-P0C3 Port pin CMOS push-pull output Leave open. I/ONote 2 Set these pins to input mode by software. Then, connect each pin to VDD or ground through a resistorNote 1. P0D0/BEEP P0A2, P0A3 P0A0, P0A1 Non-port pin CAP0, CAP1 - Leave open. CE Input Connect to VDD through a resistorNote 1. COM0-COM3 Output Leave open. EO Output Leave open. LCD0-LCD8 Output Leave open. VCOH, VCOL Input Set these pins to the disabled state by software. Then, leave these pins open. VLCD0, VLCD1 - Leave open. VREG - Leave open. Notes 1. When a pin is pulled up (connected to VDD through a resistor) or pulled down (connected to ground through a resistor) outside the chip, caution is required. When using high-resistance pull-up or pull-down resistors, the pin approaches high-impedance and the consumption (through) current increases. Although the optimum pull-up or pull-down resistor varies with the application circuit, in general the use of a resistor of 10 to 100 kilohms is recommended. 2. I/O port is applicable at power-on, at clock stop, at CE reset, or in input mode. 12 µPD17015 PD17015 1.4 NOTES ON USE OF THE CE PIN The CE pin has the test mode selecting function for testing the internal operation of the µPD17015 PD17015 (IC test), besides the functions shown in Section 1.1. Applying a voltage exceeding VDD to the CE pin causes the µPD17015 PD17015 to enter the test mode. When noise exceeding VDD comes in during normal operation, the device is switched to the test mode. For example, if the wiring from the CE pin is too long, noise may be induced on the wiring, causing this mode switching. When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise yet arises, use an external part to suppress it as shown below. · Connect a diode with low VF between the pin · Connect a capacitor between the pin and VDD. and VDD. VDD VDD VDD Diode with low VF CE VDD CE 13 µPD17015 PD17015 2. PROGRAM MEMORY (ROM) 2.1 OUTLINE OF PROGRAM MEMORY Fig. 2-1 outlines program memory. As shown in Fig. 2-1, program memory is addressed with a program counter. Program memory is used to store programs. The program counter is used to specify an address in program memory. Fig. 2-1 Outline of Program Memory Program memory Program counter Addressing Instruction 2.2 PROGRAM MEMORY CONFIGURATION Fig. 2-2 shows the configuration of program memory. As shown in Fig. 2-2, program memory consists of 1528 steps × 16 bits. Program memory therefore has addresses 0000H 0000H to 05F7H 05F7H. All µPD17015 PD17015 instructions are 16-bit one-word instructions. Each instruction can be stored at a single address of program memory. Fig. 2-2 Program Memory Configuration 0000H 0000H 16 bits 1.5K steps 05F7H 05F7H Undefined 07FFH 07FFH 14 µPD17015 PD17015 2.3 PROGRAM COUNTER Fig. 2-3 shows the configuration of the program counter. As shown in Fig. 2-3, the program counter consists of a 11-bit binary counter. The program counter is used to specify an address in program memory. Fig. 2-3 Program Counter Configuration MSB PC10 LSB PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 11 bits 2.4 PROGRAM FLOW The execution flow of a program is controlled with the program counter, which specifies an address in program memory. This section describes the operation of several types of instructions. Fig. 2-4 shows the value set in the program counter when each instruction is executed. 2.4.1 Direct branch ("BR addr") A direct branch instruction can branch to all addresses of program memory, 0000H 0000H to 05F7H 05F7H. 2.4.2 Subroutines To call a subroutine, a direct subroutine call ("CALL addr") is used. A direct subroutine call instruction can call a subroutine starting at any address in program memory, 0000H 0000H to 05F7H 05F7H. RET or RETSK instruction is used as the return instruction from a subroutine. Fig. 2-4 Program Counter Value When Each Instruction Is Executed Program counter Instruction BR CALL Value of program counter b10 b9 b8 addr addr b6 b5 b4 b3 b2 b1 b0 0 0 Instruction operand (addr) RET RETSK At power-on reset or CE reset b7 Contents of address stack register (return address) 0 0 0 0 0 0 0 0 0 15 µPD17015 PD17015 2.5 NOTES ON USE OF PROGRAM MEMORY Although only addresses 0000H 0000H to 07FFH 07FFH can be specified by the program counter, the valid program memory addresses are 0000H 0000H to 05F7H 05F7H. Program memory addresses 05F8H 05F8H to 07FFH 07FFH contain undefined values. Therefore, note the following: (1) Do not write instructions to addresses 05F8H 05F8H to 07FFH 07FFH. (2) Use a branch instruction to write instructions at address 05F7H 05F7H. (3) Do not branch to addresses 05F8H 05F8H to 07FFH 07FFH. 16 µPD17015 PD17015 3. ADDRESS STACK REGISTER (ASR) 3.1 OUTLINE AND CONFIGURATION OF ADDRESS STACK REGISTER The address stack register is used to store the return address when a subroutine call instruction is executed. Fig. 3-1 shows the configuration of the address stack registers. As shown in Fig. 3-1, there is one address stack register, consisting of 11 bits. Fig. 3-1 Configuration of Address Stack Registers Address stack register (ASR) Bit b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 The return address of the program is stored when a subroutine call instruction is executed. 3.2 ADDRESS STACK REGISTER OPERATION When a subroutine call instruction is executed, the return address is stored in the address stack register. When a return instruction is executed, the contents (return address) of the address stack register are read back into the program counter (see Table 3-1). At power-on reset, the contents of the address stack register are undefined. At CE reset, or when the clock stop instruction is executed, the contents of the address stack register are retained. Table 3-1 Program Counter Operation Upon Execution of a Subroutine Call Instruction Instruction CALL addr Operation 3.3 Stores the program counter value to the address stack register. 2 RET RETSK 1 Transfers the value specified with an operand (addr) to the program counter. Reads the value of the address stack register back into the program counter. NOTES ON USE OF ADDRESS STACK REGISTER Note that a subroutine call of more than one level cannot be used because the address stack register has a oneregister configuration consisting of 11 bits. 17 µPD17015 PD17015 4. DATA MEMORY (RAM) 4.1 OUTLINE OF DATA MEMORY Fig. 4-1 outlines the data memory. As shown in Fig. 4-1, the data memory consists of a general-purpose data memory, system registers, data buffer, general-purpose registers, LCD segment registers, port registers, and peripheral control registers. The data memory is used to store data, transfer data to and from peripheral hardware, set peripheral hardware condition, set display data, transfer data to and from ports, and control the CPU. Fig. 4-1 Outline of Data Memory 0 1 2 3 4 5 A B 0 C D E F Data buffer (DBF) Used as the general-purpose register Data transfer Peripheral hardware Column address 6 7 8 9 Low address 1 2 3 Data memory 4 5 6 7 LCD segment register Peripheral control register Port register System register Data transfer Data transfer Setting condition Port LCD 4.2 Peripheral hardware CONFIGURATION AND FUNCTIONS OF DATA MEMORY Fig. 4-2 shows the configuration of the data memory. As shown in Fig. 4-2, the data memory consists of 128 nibbles made up of row addresses 0H to 7H by column addresses 0H to FH. The data memory is divided into the functional blocks described in Sections 4.2.1 through 4.2.7. By using data memory manipulation instructions, 4-bit operations, comparison, decision, and transfer operation can be performed for the data memory. Table 4-1 indicates the data memory manipulation instructions. 4.2.1 System Register (SYSREG) A system register, allocated to addresses 74H to 7FH, directly controls the CPU. With the µPD17015 PD17015, only PSWORD (program status word: addresses 7EH and 7FH) can be manipulated. See Chapter 5 for details. 18 µPD17015 PD17015 4.2.2 Data Buffer (DBF) A data buffer, allocated at addresses 0CH-0FH, transfers data to and from peripheral hardware. With the µPD17015 PD17015, the data buffer transfers data to and from the PLL data register (peripheral address 41H) when the data (16 bits) of the PLL frequency division ratio is set or read. See Chapter 8 for details. 4.2.3 General-Purpose Register (GR) With the µPD17015 PD17015, the general-purpose register cannot be moved because it is fixed to low address 0 of data memory (i.e., addresses 00H to 0FH). The general-purpose register can be used to perform an operation on data, or transfer data to and from the data memory, by means of a single instruction. The general-purpose register, like other data memory, can be controlled by issuing data memory manipulation instructions. For details, see Chapter 6. 4.2.4 LCD Segment Data Register (LCD Segment Register) The LCD segment register, allocated at addresses 61H to 69H, sets the display data for the LCD controller/driver. For details, see Chapter 13. 4.2.5 Port Data Register (Port Register) The port register, allocated at addresses 70H to 73H, sets the output data for each general-purpose port and reads the input port data. For details, see Chapter 9. 4.2.6 Peripheral Control Register The peripheral control register, allocated at addresses 6AH to 6FH, sets the condition of the peripheral hardware (such as PLL or timer). 4.2.7 General-Purpose Data Memory The general-purpose data memory consists of data memory other than the system register, LCD segment register, port register, and peripheral control register. For the µPD17015 PD17015, 97 nibbles (97 × 4 bits: addresses 00H to 60H) can be used as general-purpose data memory. 19 20 Fig. 4-2 Configuration of Data Memory 0 1 2 3 4 5 6 7 8 9 A B C D DBF3 0 DBF2 E F DBF1 DBF0 1 2 3 4 5 6 LCDD8 P0A P 0 7 A 3 P 0 A 2 P 0 A 1 LCDD7 LCDD6 P0C P 0 B 2 P 0 B 1 P 0 B 0 P 0 C 3 P 0 C 2 P 0 C 1 P 0 C 0 0 0 0 P 0 D 0 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 LCDE B P P E 0 0 E A A P B B 0 I I S OO E 1 0 L PLLMD CEJDG PLLULJDG BTM0CYJDG BTM1CYJDG P P P P C P B B E L T T L L L L L M M L L L L 0 1 MMR R 0 0 0 0 0 0 U 0 0 0 C 0 0 0 C L D D F F Y Y 1 0 C C K K 1 0 P0D P0B P 0 A 0 0 LCDD5 L C D E N System register AR0 AR1 AR2 AR3 WR BANK IXH MPH IXM MPH IXL RPH RPL PSW B CC Z CMY D P 0 0 µPD17015 PD17015 µPD17015 PD17015 Table 4-1 List of Data Memory Manipulation Instructions Function Operation Instruction Addition ADD ADDC Subtraction SUB SUBC Logical AND OR XOR Comparison SKE SKGE SKLT SKNE Transfer MOV LD ST Decision SKT SKF 4.3 DATA MEMORY ADDRESSING Fig. 4-3 shows how a data memory address is specified. A data memory address is specified with a bank, row address, and column address. A row address and column address are directly specified with a data memory manipulation instruction. Fig. 4-3 Data Memory Addressing Row address b2 Data memory address 4.4 M b1 b0 Column address b3 b2 b1 b0 Instruction operand NOTES ON USING DATA MEMORY Upon power-on reset, the contents of the general-purpose data memory are undefined. Initialize the general-purpose data memory as required. 21 µPD17015 PD17015 5. SYSTEM REGISTER (SYSREG) 5.1 OUTLINE OF SYSTEM REGISTER Fig. 5-1 shows where the system registers are located in the data memory, and also outlines the system register. As shown in Fig. 5-1, a system register is allocated to data memory addresses 74H-7FH 74H-7FH. The system registers are allocated in the data memory, so that the system registers can be manipulated using any manipulation instructions. For the µPD17015 PD17015, only the program status word (PSWORD: 7EH and 7FH) in the system register (addresses 74H to 7FH) can be manipulated. Fig. 5-1 Location on Data Memory and Outline of System Registers Column address 0 1 2 3 0 4 5 6 7 8 9 A B C D E F Data memory Low address 1 2 3 4 5 6 7 System register Address Name Outline 22 74H 75H Fixed to 0 7DH 7EH 7FH Program status word (PSWORD) Operation control µPD17015 PD17015 5.2 5.2.1 PROGRAM STATUS WORD (PSWORD) Format of Program Status Word Fig. 5-2 shows the format of the program status word. As shown in Fig. 5-2, the program status word consists of 5 bits: the least significant bit of 7EH (RPL) of the system register, and the 4 bits of address 7FH (PSW) of the system register. Bit 0 of 7FH is always 0. A different function is assigned to each bit of the program status word; the program status word consists of a BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Fig. 5-2 Format of Program Status Word Address 7EH 7FH Program status word (PSWORD) Register Symbol RPL PSW 5.2.2 b3 b2 b1 b0 b3 b2 b1 0 0 0 B C D C M P C Y Z Data Upon reset Bit b0 0 Power-on 0 0 Clock stop 0 0 CE 0 0 Program Status Word Functions The program status word is used to set conditions for transfer instructions and operations by the arithmetic logic unit (ALU), and also to indicate the states of the results of operations. Fig. 5-3 outlines the function of each flag of the program status word. See Chapter 7 for details. 23 µPD17015 PD17015 Fig. 5-3 Outline of Function of Each Flag of Program Status Word Program status word (PSWORD) RPL b3 b2 0 0 b1 0 PSW b0 b3 b2 b1 B C D C M P C Y b0 Z 0 Flag name Function Zero flag (Z) Carry flag (CY) Used to indicate the ocurrence of a carry or borrow as the result of an addition or subtraction instruction executed. This flag is cleared to 0 when neither a carry nor a borrow is produced. This flag is set to 1 when a carry or borrow is produced. This flag is used also as a shift bit for the RORC r instruction. Compare flag (CMP) Used to specify whether to store the result of an arithmetic operation in a general-purpose register or data memory area. 0 : Stores the result. 1 : Does not store the result. BCD flag (BCD) 5.2.3 Used to indicate that the result of an arithmetic operation is 0. Note that the states of 0 and 1 differ, depending on the value of the compare flag. Used to specify whether to perform an arithmetic operation in decimal. 0 : Performs a binary operation. 1 : Performs a decimal operation. Notes on Using Program Status Word When an arithmetic instruction (addition or subtraction) is executed for the program status word, the result of the arithmetic operation is stored. If an operation is performed which produces the result 0000B 0000B with a carry, for example, 0000B 0000B is stored in the PSW. 5.3 NOTES ON USING SYSTEM REGISTER Those data items in the program status word that are always set to 0 are not affected by an attempt to execute a write instruction. When those data items in the program status word that are always set to 0 are read, 0 is read. 24 µPD17015 PD17015 6. GENERAL-PURPOSE REGISTER (GR) 6.1 OUTLINE OF GENERAL-PURPOSE REGISTER Fig. 6-1 outlines the general-purpose register. For the µPD17015 PD17015, the general-purpose register is fixed to low address 0 of the data memory, consisting of 16 nibbles (00H to 0FH, 16 × 4 bits). 16 nibbles of the row address 0 specified as a general-purpose register is used to perform an operation with or transfer data to and from the data memory. This means that an operation or data transfer between data memory areas can be performed with one instruction. As with other data memory areas, a general-purpose register can be controlled using data memory manipulation instructions. Fig. 6-1 Outline of General-Purpose Register Column address 0 1 2 0 3 4 5 6 7 8 9 A B 1 Low address C D E F General-purpose register Transfer, operation 2 3 4 Data memory 5 6 7 System register 6.2 GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS Sections 6.2.1 and 6.2.2 below describe general-purpose register address generation when each instruction is executed. For the detailed operation of each instruction, see Chapter 7. 6.2.1 Addition Instructions (ADD r,m, ADDC r,m) Subtraction Instructions (SUB r,m, SUBC r,m) Logical Operation Instructions (AND r,m, OR r,m, XOR r,m) Direct Transfer Instructions (LD r,m, ST m,r), and Rotate Instruction (RORC r) Fig. 6-2 indicates a general-purpose register address R specified by operand r of an instruction. Operand r specifies only a column address. 25 µPD17015 PD17015 Fig. 6-2 General-Purpose Register Address Generation Low address b2 General-purpose register address R 6.2.2 b1 b0 Column address b3 b2 Fixed to 0 b1 b0 r Indirect Transfer Instructions (MOV @r,m, MOV m,@r) Fig. 6-3 indicates a general-purpose register address R specified by operand r of an instruction, and an indirect transfer address specified by @R. Fig. 6-3 General-Purpose Register Address Generation Low address b2 b1 Column address b0 b3 b2 b1 b0 General-purpose register address R r Indirect transfer address 6.3 Fixed to 0 Fixed to 0 Contents of R @R NOTES ON USING GENERAL-PURPOSE REGISTER No instruction is available for operation between a general-purpose register and immediate data. To execute an operation instruction between a general-purpose register and immediate data, the general-purpose register area must be handled as a data memory area. 26 µPD17015 PD17015 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK 7.1 OVERVIEW Fig. 7-1 is an overview of the ALU block. As shown in Fig. 7-1, the ALU block consists of the ALU, temporary storage registers A and B, program status word, decimal conversion circuit, and data memory address controller. The ALU performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. Fig. 7-1 Overview of the ALU Block Data bus Address controller Temporary storage register A Temporary storage register B Program status word Detecting a carry, borrow, or zero Setting decimal calculation or result storage Data memory ALU · Arithmetic operation · Logic operation · Bit discrimination · Comparative discrimination · Rotation · Transfer Decimal conversion 27 µPD17015 PD17015 7.2 7.2.1 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 Temporary Storage Registers A and B Temporary storage registers A and B temporarily hold the 4-bit data. These registers are automatically used when an instruction is executed. They cannot be controlled by a program. 7.2.3 Program Status Word A program status word controls the operation of the ALU and holds the status of the ALU. For details of the program status word, see Section 5.2. 7.2.4 Decimal Conversion Circuit If the BCD flag of the program status word is set to 1 when an arithmetic operation is executed, the decimal conversion circuit converts the results of the arithmetic operation to a decimal number. 7.2.5 Address Controller The address controller specifies an address in data memory. 7.3 ALU OPERATIONS Table 7-1 lists the operations performed by the ALU when instructions are executed. Table 7-2 lists the converted decimal data used in decimal operations. 28 µPD17015 PD17015 ALU function Table 7-1 ALU Operations Operation difference due to program status word (PSWORD) Instruction Value Value of the of the BCD flag CMP flag Addition r, m ADD m, #n4 Subtraction 0 0 1 0 1 1 r, m ADDC r, m SUB m, #n4 r, m SUBC m, #n4 Operation of the CY flag The result is stored. Binary operation The result is not stored. Decimal operation The result is stored. Operation of the Z flag Set if the operation result is 0000B 0000B. Otherwise, the flag is reset. Binary operation 0 1 m, #n4 Operation Set by a carry or borrow. Otherwise, the flag is reset. Decimal operation The result is not stored. Retains the status if the operation result is 0000B 0000B. Otherwise, the flag is reset. Set if the operation result is 0000B 0000B. Otherwise, the flag is reset. Retains the status if the operation result is 0000B 0000B. Otherwise, the flag is reset. r, m Logic operation OR m, #n4 r, m AND m, #n4 Optional Optional (hold) (hold) Not changed Optional Optional (reset) (hold) Not changed Not changed Retains the previous state. Retains the previous state. Retains the previous state. Retains the previous state. Retains the previous state. Retains the previous state. Retains the previous state. Retains the previous state. Value of b0 of the generalpurpose register Retains the previous state. r, m XOR Discrimination m, #n4 SKF m, #n SKE m, #n4 SKNE SKGE m, #n4 Optional Optional (hold) (hold) m, #n4 m, #n4 LD Comparison m, #n SKLT Transfer SKT r, m ST m, r m, #n4 MOV Optional Optional (hold) (hold) Not changed Optional Optional (hold) (hold) Not changed @r, m Rotation m, @r RORC r 29 µPD17015 PD17015 Table 7-2 Converted Decimal Data Operation result Hexadecimal addition Decimal addition Operation result Hexadecimal addition Decimal addition CY Operation result CY Operation result 0 0 0000B 0000B 0 0000B 0000B 0001B 0001B 1 0 0001B 0001B 0 0001B 0001B 0 0010B 0010B 2 0 0010B 0010B 0 0010B 0010B 0011B 0011B 0 0011B 0011B 3 0 0011B 0011B 0 0011B 0011B 0 0100B 0100B 0 0100B 0100B 4 0 0100B 0100B 0 0100B 0100B 5 0 0101B 0101B 0 0101B 0101B 5 0 0101B 0101B 0 0101B 0101B 6 0 0110B 0110B 0 0110B 0110B 6 0 0110B 0110B 0 0110B 0110B 7 0 0111B 0111B 0 0111B 0111B 7 0 0111B 0111B 0 0111B 0111B 8 0 1000B 1000B 0 1000B 1000B 8 0 1000B 1000B 0 1000B 1000B 9 0 1001B 1001B 0 1001B 1001B 9 0 1001B 1001B 0 1001B 1001B 10 0 1010B 1010B 1 0000B 0000B 10 0 1010B 1010B 1 1100B 1100B 11 0 1011B 1011B 1 0001B 0001B 11 0 1011B 1011B 1 1101B 1101B 12 0 1100B 1100B 1 0010B 0010B 12 0 1100B 1100B 1 1110B 1110B 13 0 1101B 1101B 1 0011B 0011B 13 0 1101B 1101B 1 1111B 1111B 14 0 1110B 1110B 1 0100B 0100B 14 0 1110B 1110B 1 1100B 1100B 15 0 1111B 1111B 1 0101B 0101B 15 0 1111B 1111B 1 1101B 1101B 16 1 0000B 0000B 1 0110B 0110B ­16 1 0000B 0000B 1 1110B 1110B 17 1 0001B 0001B 1 0111B 0111B ­15 1 0001B 0001B 1 1111B 1111B 18 1 0010B 0010B 1 1000B 1000B ­14 1 0010B 0010B 1 1100B 1100B 19 1 0011B 0011B 1 1001B 1001B ­13 1 0011B 0011B 1 1101B 1101B 20 1 0100B 0100B 1 1110B 1110B ­12 1 0100B 0100B 1 1110B 1110B 21 1 0101B 0101B 1 1111B 1111B ­11 1 0101B 0101B 1 1111B 1111B 22 1 0110B 0110B 1 1100B 1100B ­10 1 0110B 0110B 1 0000B 0000B 23 1 0111B 0111B 1 1101B 1101B ­9 1 0111B 0111B 1 0001B 0001B 24 1 1000B 1000B 1 1110B 1110B ­8 1 1000B 1000B 1 0010B 0010B 25 1 1001B 1001B 1 1111B 1111B ­7 1 1001B 1001B 1 0011B 0011B 26 1 1010B 1010B 1 1100B 1100B ­6 1 1010B 1010B 1 0100B 0100B 27 1 1011B 1011B 1 1101B 1101B ­5 1 1011B 1011B 1 0101B 0101B 28 1 1100B 1100B 1 1010B 1010B ­4 1 1100B 1100B 1 0110B 0110B 29 1 1101B 1101B 1 1011B 1011B ­3 1 1101B 1101B 1 0111B 0111B 30 1 1110B 1110B 1 1100B 1100B ­2 1 1110B 1110B 1 1000B 1000B 31 1 1111B 1111B 1 1101B 1101B ­1 1 1111B 1111B 1 1001B 1001B CY Operation result CY Operation result 0 0 0000B 0000B 0 0000B 0000B 1 0 0001B 0001B 0 2 0 0010B 0010B 3 0 4 Remark Correct decimal conversion is not possible in the shaded area. 30 µPD17015 PD17015 7.4 NOTES ON USING THE ALU 7.4.1 Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. The CY and Z flags of the program status word are usually set or reset according to the result of the arithmetic operation. If the arithmetic operation is performed on the program status word itself, the result of the operation is stored and a carry, borrow, or zero cannot be discriminated. If the CMP flag is set, the result of the arithmetic operation is not stored and the CY and Z flags are set to 1 or cleared to 0 as usual. 7.4.2 Notes on Performing Decimal Operations A decimal operation can be carried out only when the operation result is within the following ranges: (1) The result of addition is between 0 and 19 in decimal. (2) The result of subtraction is between 0 and 9 or ­10 and ­1 in decimal. If a decimal operation exceeding the above ranges is performed, the CY flag is set, resulting in a value greater than or equal to 1010B 1010B (0AH). 31 µPD17015 PD17015 8. DATA BUFFER (DBF) 8.1 OVERVIEW Fig. 8-1 shows an overview of the data buffer. The data buffer is configured in data memory and used to transfer data to and from peripheral hardware. Fig. 8-1 Overview of the Data Buffer Data buffer Reading data (GET instruction) Writing data (PUT instruction) Peripheral hardware Fig. 8-2 shows the configuration of the data buffer. As shown in Fig. 8-2, the data buffer consists of 16 bits of addresses 0CH to 0FH in data memory. The most significant bit (MSB) of the 16-bit data is bit b3 at address 0CH. The least significant bit (LSB) is bit b0 at address 0FH. The data buffer is configured in data memory and can thus be manipulated by any data memory manipulation instruction. 32 µPD17015 PD17015 Fig. 8-2 Configuration of the Data Buffer Column address 0 1 2 3 4 5 6 7 8 9 A B 0 C D E F Data buffer (DBF) 1 Low address 2 3 Data memory 4 5 6 7 Data memory System register Address 0CH 0DH 0EH 0FH Bit b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol DBF3 DBF2 DBF1 DBF0 < Data < Data buffer M S L S B < < 8.1.1 B Data Instructions for Controlling the Peripheral Hardware (PUT, GET) The PUT and GET instructions operate as described below: (1) GET DBF, p Data in the peripheral register at address p is read and written into the data buffer. (2) PUT p, DBF Data in the data buffer is set in the peripheral register at address p. 33 µPD17015 PD17015 8.2 Relationship between the Peripheral Hardware and Data Buffer Table 8-1 indicates the relationship between the peripheral hardware and data buffer. With the µPD17015 PD17015, the DBF transfers data to and from the PLL data register (peripheral address 41H) when data (16 bits) of the PLL frequency division ratio is set or read. Table 8-1 Relationship between the Peripheral Hardware and Data Buffer Peripheral register used to transfer data to or from the data buffer Peripheral hardware Name Symbol Peripheral Instruction that address can be used Function Number of data buffer Number of bits actually used Description 16 Sets N, by which PLL frequency is divided. input bits PLL frequency synthesizer 8.3 PLL data register PLLR 41H GET/PUT 16 NOTES ON USING THE DATA BUFFER If an attempt is made to read the data at an unused peripheral address, an undefined value will be read. If writing to the unused address is attempted, nothing changes. 34 µPD17015 PD17015 9. GENERAL-PURPOSE PORTS A general-purpose port outputs high and low signals to external circuits and reads high and low signals from the external circuits. 9.1 OVERVIEW Table 9-1 indicates the relationship between the ports and port registers. General-purpose ports are classified into three types: I/O ports, input ports, and output ports. I/O port is a bit I/O port, whose bit (each pin) can be set to input or output mode. Table 9-1 Relationship between Ports (Pins) and Port Registers Pin Data setting method Port register (data memory) Port No. Pin name I/O Address 7 Port 0A P0A0 8 P0A1 Symbol Bit symbol (reserved word) b0 P0A1 b2 70H P0A0 b1 I/O (bit I/O) Remarks I/O switching is performed by the P0ABIO0 or P0ABIO1 flag. P0A2 P0A 9 P0A2 10 P0A3 b3 P0A3 37 P0B0 b0 P0B0 38 P0B1 b1 P0B1 b2 P0B2 No target pin b3 - 2 P0C0 b0 P0C0 3 P0C1 b1 P0C1 Output Input 71H Port 0B 1 P0B P0B2 Output Port 0C 72H Fixed to 0. P0C 4 P0C2 b2 P0C2 5 P0C3 b3 P0C3 6 P0D0 b0 P0D0 b1 - b2 - b3 - Output 73H Port 0D No target pin P0D Switching to BEEP output is performed by the BEEP0SEL flag. Fixed to 0. 35 µPD17015 PD17015 9.2 9.2.1 GENERAL-PURPOSE I/O PORTS (P0A0 and P0A1 pins) Configurations of the I/O ports The configurations of the I/O ports are shown below. (1) P0A0 and P0A1 pin I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 Read instruction 0 9.2.2 Using the I/O Port The P0ABIO0 or P0ABIO1 flag of the LCD enable register sets the I/O port to input or output mode. P0A0 and P0A1 pins are bit I/O ports, each bit of which (each pin) can be set to input or output mode. To set the output data, write the data to the corresponding port register. To read the input data, execute an instruction to read the data. 9.2.3 Control Registers of the I/O Ports The P0ABIO0 and P0ABIO1 flags of the LCD enable register set P0A0 and P0A1 pins in input or output mode, respectively. Fig. 9-1 shows the configuration and functions of the LCD enable register. 36 µPD17015 PD17015 Fig. 9-1 Configuration and Functions of the LCD Enable Registers Flag symbol Register LCD enable register b3 b2 b1 b0 L C D E N B E E P 0 S E L P 0 A B I O 1 Address Read/write 6AH R/W P 0 A B I O 0 Sets pin P0A0 to input or output mode. 0 Sets pin P0A0 to input mode. 1 Sets pin P0A0 to output mode. Sets pin P0A1 to input or output mode. 9.2.4 Sets pin P0A1 to input mode. 1 Upon reset 0 Sets pin P0A1 to output mode. Power-on 0 0 0 0 Clock stop 0 0 0 0 CE Hold Using an I/O Port as an Input Port Select the pin to be set to input mode, using the P0ABIO0 and P0ABIO1 flags of the LCD enable register. The P0A0 and P0A1 pins can be set to input mode bit by bit. The specified input pin enters the floating (Hi-Z) status and waits for the input of an external signal. To read the input data, execute an instruction to read the contents of the port register P0A (such as SKT). If the signal input to the pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for the port register corresponding to an input port, the contents of the output latch are rewritten. 9.2.5 Using an I/O Port as an Output Port Select the pin to be set to output mode, using the P0ABIO0 and P0ABIO1 flags of the LCD enable register. The P0A0 and P0A1 pins can be set in the output mode bit by bit. The specified output pin outputs the contents of the output latch. To set the output data, execute a write instruction (such as MOV) for the port register P0A. To output a high signal to a pin, write 1. To output a low signal, write 0. To set a port to the floating state, set the port to input mode. If a read instruction (such as SKT) is executed for the port register corresponding to an output port, the contents of the output latch are read. 37 µPD17015 PD17015 5 Caution If a read instruction (such as SKT) is executed for a port register specified as an output port, the contents of the output latch and the read data may differ because the status of the output pin is read as is. 9.2.6 Statuses of the I/O Ports upon Reset (1) At power-on reset All pins are set to input mode. 5 The contents of the output latches are reset to 0. (2) At CE reset All pins are set to input mode. The contents of the output latches are retained. (3) At a clock-stop All pins are set to input mode. The contents of the output latches are retained. (4) In the halt state The previous statuses are retained. GENERAL-PURPOSE INPUT PORT (P0B0 to P0B2 pins) 9.3 9.3.1 Configuration of the Input Port The configuration of the input port is shown below: · P0B (P0B0 to P0B2 pins) Write instruction VDD Port register (1 bit) Input latch High on-state resistance 38 Read instruction Read instruction µPD17015 PD17015 9.3.2 Using the Input Port To read the input data, execute an instruction to read the contents of port register P0B (such as SKT). If the signal input to a pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for a port register, nothing changes. 9.3.3 Notes on Using the Input Port P0B is internally pulled down. 9.3.4 Statuses of the Input Port upon Reset (1) At power-on reset All pins are set to input mode. (2) At CE reset All pins are set to input mode. (3) At a clock-stop All pins are set to input mode. (4) In the halt state The previous statuses are retained. GENERAL-PURPOSE OUTPUT PORTS (P0A2, P0A3, P0C0 to P0C3, and P0D0 pins) 9.4 9.4.1 Configurations of the Output Ports The configurations of the output ports are shown below. · P0A (P0A2 and P0A3 pins), P0C (P0C0 to P0C3 pins), P0D (P0D0 pin) VDD Output latch VDD Write instruction Port register (1 bit) Read instruction 39 µPD17015 PD17015 9.4.2 Using the Output Port The output port outputs the contents of the output latch from each pin. To set the output data, execute a write instruction (such as MOV) for the port register corresponding to each pin. To output a high signal to a pin, write 1. To output a low signal, write 0. 5 Caution If a read instruction (such as SKT) is executed for a port register, the contents of the output latch and the read data may differ because the status of the output pin is read as is. 9.4.3 Statuses of the Output Port upon Reset (1) At power-on reset The contents of the output latches are output. 5 The contents of the output latches are reset to 0. (2) Upon CE reset The contents of the output latch are output. The output latch retains the data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (3) Upon a clock stop All pins are set to input mode. The output latch retains the last data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (4) In the halt state The previous statuses are retained. 40 µPD17015 PD17015 10. TIMERS The timers in the µPD17015 PD17015 are used to manage the time required to execute programs. 10.1 OVERVIEW Fig. 10-1 shows the block diagrams of the timers. The µPD17015 PD17015 contains the following two different timers. · Basic timer 0 · Basic timer 1 Basic timers 0 and 1 are realized by detecting the state of a flip-flops that is set at constant intervals, using software. Fig. 10-1 Overview of Timers 125 ms(8 Hz) 75 kHz Set/clear Basic timer 1 carry flip-flop Set/clear BTM0CY flag Frequency divider 5 ms(200 Hz) 10.2 Basic timer 0 carry flip-flop BTM1CY flag BASIC TIMERS 0 AND 1 10.2.1 Overview of Basic Timers 0 and 1 Basic timer 0 is realized by detecting the state of a basic timer 0 carry flip-flop, using the BTM0CY flag (bit 0 at address 6EH). Basic timer 1 is realized by detecting the state of a basic timer 1 carry flip-flop, using the BTM1CY flag (bit 0 at address 6FH). The contents of the flip-flops correspond to the states of the BTM0CY and BTM1CY flags on a one-to-one basis, respectively. Time intervals (pulses) at which the BTM0CY and BTM1CY flags are set are as follows: BTM0CY flag set pulse: 125 ms (8 Hz) BTM1CY flag set pulse: 5 ms (200 Hz) When the BTM0CY and BTM1CY flags are read-accessed for the first time after a power-on reset, these flags are read as 0. Subsequently, the BTM0CY flag is set to 1 after an interval of 125 ms and the BTM1CY flag is set to 1 after an intervals of 5 ms. Basic timer 0 also controls the timing of the reset (CE reset) by the CE pin. After the CE pin goes from a low level to a high level, a CE reset occurs simultaneously when the BTM0CY flag is set next time. A power failure can therefore be detected by reading the BTM0CY flag when a system reset (power-on or CE reset) occurs. See Chapter 15 for power failure detection. 41 µPD17015 PD17015 10.2.2 Basic Timer 0 Carry Flip-Flop, Basic Timer 1 Carry Flip-Flop, BTM0CY Flag, and BTM1CY Flag The flip-flop is set at constant intervals, and its state is detected using the BTM0CY and BTM1CY flags. The BTM0CY and BTM1CY flags are read-only. These flags are reset by reading their contents using the instructions listed in Table 10-1 (Read & Reset). The BTM0CY and BTM1CY flags are "0" at a power-on reset. It becomes "1" at a CE reset. So, it can be used as a power failure detection flag. Even when power is supplied, the BTM0CY and BTM1CY flags will not be set until their contents have been read using the instructions listed in Table 10-1. Once a read instruction is executed, the flag is set at constant intervals. Fig. 10-2 shows the configuration and function of the basic timer 0 carry flip-flop judge register. Fig. 10-3 shows the configuration and function of the basic timer 1 carry flip-flop judge register. Table 10-1 Instructions Used to Reset the BTM0CY and BTM1CY Flags Mnemonic Operand Mnemonic ADD ADDC SUB ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE SUBC AND OR XOR LD SKT SKF Operand m, #n4 MOV r, m m, #n @r, m m, @rNote Note When the low address of m is 6H, and 0EH or 0FH is written into r. Remark m = 6EH or 6FH 42 µPD17015 PD17015 Fig. 10-2 Configuration of the Basic Timer 0 Carry Flip-Flop Judge Register Flag symbol Register Basic timer 0 carry flip-flop judge register b3 0 b2 0 b1 b0 0 B T M 0 C Y Address Read/write 6EH Read & Reset Detects the state of the basic timer 0 carry flip-flop. 0 The basic timer 0 carry flip-flop is not set. 1 The basic timer 0 carry flip-flop is set. Upon reset Fixed to 0 Power-on 0 0 0 0 Clock stop 1 CE 1 Fig. 10-3 Configuration of the Basic Timer 1 Carry Flip-Flop Judge Register Flag symbol Register Basic timer 1 carry flip-flop judge register b3 0 b2 0 b1 b0 0 B T M 1 C Y Address Read/write 6FH Read & Reset Detects the state of the basic timer 1 carry flip-flop. 0 The basic timer 1 carry flip-flop is not set. 1 The basic timer 1 carry flip-flop is set. Upon reset Fixed to 0 Power-on 0 0 0 0 Clock stop 1 CE 1 43 µPD17015 PD17015 10.2.3 Example of Using Basic Timer 0 A sample program follows. The following program performs process A at every one second. Example MEM 0.10H ; 1 second counter SKT1 BTM0CY ; Branches to NEXT if BTM0CY is 0. BR NEXT M1 LOOP: ADD M1, #0100B 0100B ; Adds 4 to M1. SKT1 CY ; Branches to NEXT if CY flag is 0. BR NEXT ; Performs process A if CY flag is 1. Process A NEXT: Process B BR 10.2.4 ; Performs B and branches to LOOP. LOOP Time Interval Error in Basic Timers 0 and 1 The time interval at which the BTM0CY and BTM1CY flags are detected must be shorter than the time interval at which the BTM0CY and BTM1CY flags are set. (See Section 10.2.5.) Assuming that the BTM0CY or BTM1CY flag is detected at intervals of tCHECK and set at intervals of tSET (125 or 5 ms, respectively), the relationship between tCHECK and tSET must be as follows: tCHECK < tSET Under this condition, the time interval error encountered when the BTM0CY and BTM1CY flags are detected is as follows: 0 < error < tSET Fig. 10-4 Basic Timers 0 and 1 Error Related to the Detection Time of the BTM0CY and BTM1CY Flags BTM0CY flag set pulse H BTM1CY flag set pulse L tSET BTM0CY flag 1 BTM1CY flag 0 tCHECK1 SKT1 BTM0CY or SKT1 BTM1CY 1 44 tCHECK2 SKT1 BTM0CY or SKT1 BTM1CY 2 tCHECK3 SKT1 BTM0CY or SKT1 BTM1CY 3 SKT1 BTM0CY or SKT1 BTM1CY 4 µPD17015 PD17015 As shown in Fig. 10-4, when the BTM0CY and BTM1CY flags are detected at 2 , the timer is updated because the flag is "1". When the flag is detected at 3 , because it is "0", the timer is not updated until it is detected again at 4 10.2.5 . Therefore, the timer is incremented by tCHECK3. Cautions for Using Basic Timers 0 and 1 (1) BTM0CY and BTM1CY flags detection time interval As described in Section 10.2.4, keep the BTM0CY and BTM1CY flags detection time interval shorter than the BTM0CY and BTM1CY flags set time interval. Otherwise, the BTM0CY and BTM1CY flags cannot be set if the time required for process B is longer than the BTM0CY and BTM1CY flags set time interval, as shown in Fig. 10-5. Fig. 10-5 Detection of the BTM0CY and BTM1CY Flags BTM0CY flag set pulse BTM1CY flag set pulse H BTM0CY flag 1 BTM1CY flag 0 L 1 2 SKT1 BTM0CY or SKT1 BTM1CY 3 5 SKT1 BTM0CY or SKT1 BTM1CY SKT1 BTM0CY or SKT1 BTM1CY Process A 4 Process B Because the time required for process B is long after the BTM0CY and BTM1CY flags, which is set to "1" at 2 , is detected, the BTM0CY and BTM1CY flags, which is set to "1" at 3 , cannot be detected. (2) Sum of the timer update process time and the BTM0CY and BTM1CY flags detection time interval As explained in (1), the BTM0CY and BTM1CY flags detection time interval must be kept shorter than the BTM0CY and BTM1CY flags set time interval. Even when the BTM0CY and BTM1CY flags detection time interval is short, however, if the timer update process time is long, a CE reset may prevent a normal timer update process. The following conditions must therefore be satisfied. tCHECK + tTIMER < tSET where tCHECK : BTM0CY and BTM1CY flags detection time interval tTIMER : Timer update process time tSET : BTM0CY and BTM1CY flags set time interval The coding that meets these conditions is given below. 45 µPD17015 PD17015 Example Timer update process and BTM0CY flag detection time interval ; Program address 0000H 0000H START: Process A BTIMER: ; 1 SKT1 ; Updates the timer if the BTM0CY flag is set to 1. BTM0CY BR AAA Timer update BR BTIMER AAA: Process B BR BTIMER The timing chart for this coding is as follows: H CE pin L H BTM0CY flag set pulse L 1 BTM0CY flag 0 BTM0CY detection time interval tCHECK 1 SKT1 BTM0CY 1 Timer update process tTIMER SKT1 BTM0CY A CE reset occurs if this timer update process takes long time. CE reset 46 µPD17015 PD17015 10.2.6 Cautions for Using Basic Timer 0 (1) Correcting the basic timer 0 at a CE reset The following paragraphs describe an example of correcting the timer at a CE reset. As explained in the example, it is necessary to correct the timer at a CE reset, if the BTM0CY flag is used both to detect a power failure and to control the clock timer. The BTM0CY flag is cleared (0) when the supply voltage is first applied (at power-on reset). It is not set until its contents have been read by an instruction listed in Table 10-1. When the CE pin goes from a low level to a high level, a CE reset occurs in synchronization with the rising edge of the BTM0CY flag set pulse, setting the BTM0CY flag to "1" and making it active. Detecting the state of the BTM0CY flag at a system reset (power-on or CE reset) can therefore check for a power failure. If the flag is "0", it means that a power-on reset has occurred. If it is "1", it means that a CE reset has occurred (power failure detection). In this case, a clock timer must keep operating even at a CE reset. However, reading the BTM0CY flag for power failure detection clears the flag to 0 and makes it impossible to detect the set (1) state of the flag for one cycle. To solve this problem, it is necessary to update the clock timer if an attempt to detect a power failure detects a CE reset. See Section 15.5 for power failure detection. Example Correcting the timer at a CE reset (when the BTM0CY flag is used for both power failure detection and timer update) ; Program address 0000H 0000H START : Process A ; 1 SKT1 BTM0CY BR INITIAL ; Built-in macro ; Checks the BTM0CY flag and branches to INITIAL ; if the flag is "0" (power failure detected). BACKUP : ; 2 Timer update by 125 ms ; Timer correction because of backup (CE reset) Process B ; While performing process B, LOOP: ; 3 SKF1 BTM0CY BR BR ; tests the BTM0CY flag and updates the timer. BACKUP LOOP INITIAL : Process C BR LOOP Fig. 10-6 shows the timing chart for the above program. 47 µPD17015 PD17015 Fig. 10-6 Timing Chart 3.0 V 0V H CE L 8 Hz H VDD internal pulse BTM0CY flag set pulse BTM0CY flag L H L 1 0 A Program processing Program instruction Supply voltage applied C 1 B 3 Start at address 0 on a power-on reset B 3 B 3 Timer incremented B 3 B 3 B 3 Timer incremented B 3 B B 3 Timer incremented 3 B 3 Timer incremented B 1 Start at address 0 on a CE reset B 3 B 3 Timer incremented Timer updated because the BTM0CY flag has been detected to be set (1) BTM0CY flag detected Point A A Point B Point C Point D Point E As shown in Fig. 10-6, when supply voltage VDD is applied, the 8 Hz internal pulse rises to make the program start at address 0000H 0000H. When the BTM0CY flag is detected at point A, the BTM0CY flag appears to be cleared (0) because it is just after power is supplied. Consequently, it is determined that a power failure (power-on reset) has occurred. Then, process C is performed. So, process C is performed to select 100 ms as the BTM0CY flag set pulse. Because the BTM0CY flag is once read-accessed at point A, the BTM0CY flag will be set (1) at intervals of 125 ms. Even when the CE pin goes to a low at point B and goes to a high at point C, the program continues to update the clock while performing process B, unless the clock stop instruction is executed. Because the CE pin goes from a low to a high at point C, a CE reset occurs at point D, where the BTM0CY flag set pulse rises, to start the program at address 0000H 0000H. When the BTM0CY flag is detected at point E, it is determined that a backup (CE reset) has occurred, because the flag appears to be set (1). Also, as easily seen from the figure, if the clock is not updated by 125 ms at point E, the clock loses 125 ms every time a CE reset occurs. If process A takes more than 125 ms to detect for a power failure at point E, it is impossible to detect the BTM0CY flag for two cycles. Therefore, process A must be performed within 125 ms. It is necessary, therefore, to detect the BTM0CY flag for power failure detection after the program starts at address 0000H 0000H and before the BTM0CY flag is set. 48 µPD17015 PD17015 (2) When the BTM0CY flag is detected simultaneously with a CE reset As described in (1), a CE reset occurs at the same time the BTM0CY flag is set (1). Under this condition, if a read instruction is executed for the BTM0CY flag simultaneously with a CE reset, the read instruction takes preference. Therefore, if a BTM0CY flag read instruction occurs simultaneously with the rising edge of the BTM0CY flag set pulse that occurs after the CE pin goes from a low to a high, a CE reset occurs when the BTM0CY flag is set on the next cycle. This operation is illustrated in Fig. 10-7. Fig. 10-7 Operation That Occurs If a CE Reset Occurs Simultaneously with a BTM0CY Flag Read Instruction H L BTM0CY flag H set pulse L 1 BTM0CY flag 0 CE pin SKT 1 BTM0CY SKT 1 BTM0CY CE reset H BTM0CY flag set pulse L 1 BTM0CY flag 0 Instruction SKT1 BTM0CY 53.3 µ s If the BTM0CY flag is read during this period, a CE reset is deferred by one cycle. Normally, the program starts at address 000H at this point, but a CE reset does occur because the program to read the BTM0CY flag also happens to run. 49 µPD17015 PD17015 11. PLL FREQUENCY SYNTHESIZER The PLL (Phase Locked Loop) frequency synthesizer is used to lock MF (Medium Frequency), HF (High Frequency) or VHF (Very High Frequency) band frequencies to a fixed frequency using a phase error comparison system. 11.1 GENERAL Fig. 11-1 outlines the PLL frequency synthesizer. A PLL frequency synthesizer can be built by connecting a low pass filter (LPF), voltage controlled oscillator (VCO), and prescaler externally. The PLL frequency synthesizer divides the signal input from the VCOH or VCOL pin using a programmable divider and outputs the phase error with the reference frequency to the EO pin. The PLL frequency synthesizer operates only when the CE pin is high level. When the CE pin is low level, the PLL frequency synthesizer is disabled. For a description of the PLL disabled state, see Section 11.5. Fig. 11-1 PLL Frequency Synthesizer DBF VCOH VCOL Input switching block Programmable divider Phase comparator ( -DET) Reference frequency generator EO Unlock detection block Charge pump Note 75 kHz Low-pass filter (LPF) Note Voltage controlled oscillator (VCO) PLLMD0 flag PLLMD1 flag PLLRFCK0 flag PLLRFCK1 flag PLLUL flag Note External circuit. Remarks 1. PLLRFCK0 and PLLRFCK1 (bits 0 and 1 of PLL mode selection register: see Fig. 11-3): Set the PLL frequency synthesizer reference frequency fr. 2. PLLMD0 and PLLMD1 (bits 2 and 3 of PLL mode selection register: see Fig. 11-3): Set the frequency division method of the PLL frequency synthesizer. 3. PLLUL (bit 0 of PLL unlock flip-flop judge register: see Fig. 11-8): Detects the state of the unlock flip-flop. 50 µPD17015 PD17015 11.2 INPUT SWITCHING BLOCK AND PROGRAMMABLE DIVIDER 11.2.1 Configuration Fig. 11-2 shows the configuration of the input switching block and programmable divider. The input switching block consists of the VCOH and VCOL pins and their input amplifiers. The programmable divider consists of a two-modulus prescaler, swallow counter, programmable counter, and division method selection switches. Fig. 11-2 Input Switching Block and Programmable Divider PLLMD0 flag DBF PLLMD1 flag 16 PLL data register 2-4 decoder 12 bits MF VHF 4 PSC 2-modulus prescaler 1/16, 1/17 VCOH 12 VHF HF HF VHF 4 bits Swallow counter (4 bits) Programmable counter (12 bits) fN To -DET MF HF VCOL MF PLL disable signal 51 µPD17015 PD17015 11.2.2 Functions The input switching block and programmable divider select the input pin and division method to be used by the PLL frequency synthesizer. Either the VCOH or VCOL pin can be selected as the input pin. The selected pin will have an intermediate potential (about half of VDD). The input to the pin is provided by an AC amplifier. The DC element should be eliminated from the input signal by connecting a capacitor in series with the pin. As the division method, either direct division or pulse swallow can be selected. The programmable divider divides the signal input by means of the selected division method, using the division ratio set by the swallow counter and programmable counter. Table 11-1 lists the division methods and input pins (VCOH and VCOL pins) to be used. The input pin and division method to be used are selected according to the PLLMD0 and PLLMD1 flags of the PLL mode select register. Fig. 11-3 shows the configuration of the PLL mode select register, together with its functions. The division ratio of the programmable divider is set by the PLL data register via data buffers. Section 11.2.3 describes the programmable divider and PLL data register. Table 11-1 Input Pins and Division Methods Division method Pin used Input frequency range (MHz) Input amplitude (Vp-p) Possible division ratio Division ratio that can be set in the data buffers Direct division (MF) VCOL 0.5 to 8 0.2 16 to 212 ­ 1 010×H - FFF×H (×: Don't care about low-order 4 bits.) Pulse swallow (HF) VCOL 6 to 55 0.2 256 to 216 ­ 1 0100H-FFFFH 0100H-FFFFH Pulse swallow (VHF) VCOH 40 to 220 0.2 256 to 216 ­ 1 0100H-FFFFH 0100H-FFFFH 52 µPD17015 PD17015 Fig. 11-3 Configuration and Functions of the PLL Mode Select Register Flag symbol Address b3 PLL mode select register b2 b1 P L L M D 0 P L L R F C K 1 P L L R F C K 0 R/W b0 P L L M D 1 Read/write 6BH Name Sets reference frequency fr of the PLL frequency synthesizer.Note 0 0 1 kHz 0 1 3 kHz 1 0 5 kHz 1 1 25 kHz Sets the division method used by the PLL frequency synthesizer. 0 Disables pins VCOL and VCOH 0 1 Selects direct division (VCOL pin, MF mode). 1 0 Selects pulse swallow (VCOH pin, VHF mode). 1 Upon reset 0 1 Selects pulse swallow (VCOL pin, HF mode). Power-on 0 0 0 0 Clock-stop 0 0 0 0 CE Hold Note For details of the reference frequency, see Section 11.3. Items (1) to (4), below, outline the division methods: (1) Direct division (MF) The VCOL pin is used. The VCOH pin enters the floating state. In direct division, the signal input is divided according to the programmable counter only. (2) Pulse swallow (HF) The VCOL pin is used. The VCOH pin enters the floating state. When using pulse swallow, the signal input is divided according to the settings of the swallow counter and programmable counter. (3) Pulse swallow (VHF) The VCOH pin is used. The VCOL pin enters the floating state. When using pulse swallow, the signal input is divided according to the settings of the swallow counter and programmable counter. 53 µPD17015 PD17015 (4) VCOL and VCOH pins disabled The VCOL and VCOH pins enter the floating state. In this state, the phase comparator and reference frequency generator stop the output, and the charging pump sets the EO output pin to the floating state. This operation is the same as that performed in the PLL disable state, described in Section 11.5. 11.2.3 Programmable Divider and PLL Data Register The programmable divider divides the signal input from the VCOH or VCOL pin, using the division ratio set by the swallow counter and programmable counter. The swallow counter and program counter are 4-bit and 12-bit binary down-counters, respectively. The division ratios for the swallow counter and program counter are set in the PLL data register (PLLR: peripheral address 41H) via data buffers. Data is written to and read from the PLL data register by the PUT PLLR, DBF and GET DBF, PLLR instructions. The division ratio is referred to as the N value. For details of setting division ratio (N value) for each division method, see Section 11.6. (1) PLL data register and data buffer Fig. 11-4 shows the relationship between the PLL data register and data buffers. In direct division, the high-order 12 bits are valid. When pulse swallow is being used, all 16 bits are valid. In direct division, the above 12 bits are set in the programmable counter. When pulse swallow is being used, the high-order 12 bits are set in the programmable counter while the loworder four bits are set in the swallow counter. (2) Relationship between division value N of the programmable divider and the divided output frequency The following expressions indicate the relationship between value N, set in the PLL data register, and frequency fN of the signal output divided by the programmable divider: (a) Direct division (MF) fN = fIN N (N: 12 bits) (b) Pulse swallow (HF, VHF) fN = 54 fIN N (N: 16 bits) µPD17015 PD17015 Fig. 11-4 Relationship between the PLL Data Register and Data Buffers Name Data buffer Symbol DBF3 DBF2 DBF1 DBF0 Address 0CH 0DH 0EH 0FH Bit b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Transfer data Data GET instruction allowed 16 PUT instruction allowed Peripheral register Name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address Peripheral hardware Valid data PLL data register PLLR 41H PLL frequency synthesizer Sets the division ratio of the PLL frequency synthesizer. 0 Don't care | Not to be set 15 (00FH) 16 (010H) Direct division Don't care Don't care | x Don't care Division ratio N:N = x | 212­1 (FFFH) Don't care 0 | Not to be set 255 (00FFH 00FFH) 256 (0100H 0100H) Pulse swallow | x Division ratio N:N = x | 216­1 (FFFH) 55 µPD17015 PD17015 11.3 REFERENCE FREQUENCY GENERATOR Fig. 11-5 shows the configuration of the reference frequency generator. The reference frequency generator generates the PLL frequency synthesizer reference frequency "fr" by dividing the 75-MHz signal of a crystal oscillator. The reference frequency fr can be selected from among 1 kHz, 3 kHz, 5 kHz, and 25 kHz. The reference frequency fr is selected with the PLLRFCK0 and PLLRFCK1 flags of the PLL mode selection register (see Fig. 11-3). Fig. 11-5 Reference Frequency Generator PLLRFCK0 flag PLLRFCK1 flag 75 kHz Frequency divider 2-4 decoder 1 kHz 3 kHz fr 5 kHz 25 kHz Selector 56 To -DET µPD17015 PD17015 11.4 11.4.1 PHASE COMPARATOR (-DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK Configuration of Phase Comparator, Charge Pump and Unlock Detection Block Fig. 11-6 shows the configuration of the phase comparator, charge pump and unlock detection block. The phase comparator compares the phase of the divided frequency (fN) signal output from the programmable divider and that of the reference frequency (fr) signal output from the reference frequency generator and outputs an up request signal (UP) or down request signal (DW). The charge pump outputs the output of the phase comparator from the error out pin (EO pin). The unlock detection block detects the PLL frequency synthesizer unlocked state from UP and DW. Sections 11.4.2 to 11.4.4 describe the operation of the phase comparator, charge pump, and unlock detection block. Fig. 11-6 Phase Comparator, Charge Pump and Unlock Detection Block PLLUL flag Reference frequency generator fr UP Unlock detection block Phase comparator ( -DET) Programmable divider fN Charge pump EO DW PLL disable signal 57 µPD17015 PD17015 11.4.2 Phase Comparator Functions As shown in Fig. 11-6, the phase comparator compares the phase of the programmable divider divided (fN) output and that of the reference frequency (fr) signal and outputs an up request signal or down request signal. That is, if divided frequency "fN" is lower than reference frequency "fr", an up request signal is output, and if divided frequency "fN" is higher than reference signal "fr", a down request signal is output. Fig. 11-7 shows the relationship among the reference frequency fr, division frequency fN, up request signal, and down request signal. In the PLL disabled state, neither an up request signal nor a down request signal is output. The up request and down request signals are input to the charge pump and unlock detection block. Fig. 11-7 fr, fN, UP, and DW Signal Relationship (a) When fN phase lags fr phase fr fN UP DW (b) When fN phase leads fr phase fr fN UP DW (c) When fN and fr are same phase fr fN UP DW (d) When fN frequency lower than fr frequency fr fN UP DW 11.4.3 Charge Pump As shown in Fig. 11-6, the charge pump outputs the up request signal or down request signal sent from the phase comparator, from the error out pin (EO pin). Error output pin output, division frequency fN, and reference frequency fr have the following relation: When reference frequency fr > division frequency fN: Low level output When reference frequency fr < division frequency fN: High level output When reference frequency fr = division frequency fN: Floating 58 µPD17015 PD17015 11.4.4 Functions of Unlock Detection Block As shown in Fig. 11-6, the unlock detection block detects the PLL frequency synthesizer unlocked state from the phase comparator up request and down request signals. That is, since the up request signal or down request signal outputs low level while the PLL frequency synthesizer is in the unlocked state, the unlocked state can be detected by monitoring this low level signal. When the PLL frequency synthesizer is in the unlocked state, the unlock flip-flop is set (1). The state of the unlock flip-flop is detected by the PLLUL flag of PLL unlock flip-flop judge register (see Fig. 11-8). The unlock flip-flop is set at the period of the reference frequency fr selected at the time. The contents of the PLL unlock flip-flop judge register are read with instructions shown in Table 11-2 and reset (Read & Reset). The unlock flip-flop must be detected at a period longer than reference frequency fr period 1/fr. Fig. 11-8 Configuration and Functions of PLL Unlock Flip-Flop Judge Register Flag symbol Address Register b3 PLL unlock flip-flop judge register 0 b2 0 b1 0 P L L U L Read/write 6DH Read & Reset b0 Detects the state of the unlock flip-flop. 0 Unlock flip-flop = 0 : PLL locked 1 Unlock flip-flop = 1 : PLL unlocked Upon reset Fixed to 0. Power-on 0 0 0 * Clock stop Hold CE rest Hold * Undefined 59 µPD17015 PD17015 Table 11-2 Instructions Which Reset the PLL Unlock Flip-Flop Judge Register Mnemonic Operand Mnemonic ADD ADDC SUB SUBC ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE AND OR XOR LD SKT SKF m, #n4 MOV Note When the low address of m is 6H, and 0DH is written into r. Remark m = 6DH 60 Operand r, m m, #n @r, m m, @rNote µPD17015 PD17015 11.5 PLL DISABLED STATE The PLL frequency synthesizer is disabled while the CE pin (pin 13) is low level. The PLL frequency synthesizer is also disabled when VCOH/VCOL pin disabled is selected by the PLL mode selection register, even if the CE pin is set to high level. Table 11-3 shows the state of each block at PLL disabled. Since the PLL mode selection register is not initialized (previous state is held) at CE reset, it is reset to its previous state when the CE pin rises to high level after dropping to low level and PLL disabled is set. Therefore, when PLL disabled must be set at CE reset, the PLL reference clock selection register must be initialized by program. At power-on reset, PLL disabled is set. Table 11-3 Operation of Each Block at PLL Disabled Condition Block CE pin = low level (PLL disabled) CE pin = high level (PLLMD = 0000B 0000B: VCOH/VCOL pin disabled) VCOL/VCOH pin Floating Programmable divider Frequency division stopped Reference frequency generator Output stopped Phase comparator Charge pump 11.6 EO pin floated PLL FREQUENCY SYNTHESIZER USE To control the PLL frequency synthesizer, the following data is necessary: (1) Frequency division method : Direct division (MF), pulse swallow (HF, VHF) (2) Pins to be used : VCOL and VCOH pins (3) Reference frequency : fr (4) Division value : N Sections 11.6.1 to 11.6.3 describe the PLL data setting method for each division method (MF, HF, or VHF). 11.6.1 Direct Division Method (MF) (1) Selecting the division method to be used The direct division method is selected by setting the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOL pin becomes available when the direct division method is selected. (3) Reference frequency fr setting The reference frequency is set by the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. 61 µPD17015 PD17015 (4) Division value N computation method Division value N is computed as follows: N= fVCOL fr fVCOL : VCOL pin input frequency fr : Reference frequency (5) PLL data setting example The method of setting the data to receive a MF band broadcast station is shown below. Receiving frequency : 1422 kHz (MW band) Reference frequency : 3 kHz Intermediate frequency : +450 kHz Division value N is: N= fVCOL fr = 1422 + 450 3 = 624 (decimal) = 270H (hexadecimal) Data is written to the PLL data register and PLL mode selection register as follows: PLLR PLLMD 0010 0000 2 11.6.2 0111 7 Any value 0 0101 MF, 3 kHz Pulse Swallow Method (HF) (1) Selection of the division method The pulse swallow method is selected by the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOL pin becomes available when the pulse swallow method is selected. (3) Reference frequency fr setting The reference frequency is set with the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. (4) Division value N computation Division value N is computed as follows: N= fVCOL fr fVCOL 62 : VCOL pin input frequency fr : Reference frequency µPD17015 PD17015 (5) PLL data setting example The data to be set to receive a SW band broadcast station is shown below. Receiving frequency : 25.50 MHz (SW band) Reference frequency : 5 kHz Intermediate frequency : +450 kHz Division value N is: N= fVCOL fr = 25500 + 450 = 5190 (decimal) 5 = 1446H 1446H (hexadecimal) Data is written into the PLL data and PLL mode selection registers as follows: PLLMD PLLR 0001 0100 0110 1110 1 11.6.3 0100 4 4 6 HF, 5 kHz Pulse Swallow Method (VHF) (1) Selection of division method The pulse swallow method is selected by setting the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOH pin becomes available when the pulse swallow method is selected. (3) Reference frequency fr setting The reference frequency is set by the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. (4) Division value N computation method Division value N is computed as follows: N= fVCOH fr fVCOH : VCOH pin input frequency fr : Reference frequency 63 µPD17015 PD17015 (5) PLL data setting example The data to be set to receive an FM band broadcast station is shown below. Receiving frequency : 100.0 MHz (FM band) Reference frequency : 25 kHz Intermediate frequency : +10.7 kHz Division value N is: N= fVCOH fr = 100.0 + 10.7 0.025 = 4428 (decimal) = 114CH 114CH (hexadecimal) Data is written into the PLL data and PLL mode selection registers as follows: PLLMD PLLR 0001 0100 1100 1011 1 11.7 0001 1 4 C VHF, 25 kHz STATE AT RESET 11.7.1 At Power-On Reset Since the PLL mode selection register is initialized to 0000B 0000B, the PLL disabled state is set. 11.7.2 At Clock-Stop The PLL disabled state is set at the time the CE pin drops to low level. 11.7.3 At CE Reset (1) CE reset caused by clock stop Since clock-stop initializes the PLL mode selection register to 0000B 0000B, the PLL disabled state is set. (2) CE reset when clock not stopped Since the PLL mode selection register retains its previous state, the previous state is set when the CE pin rises to high level. 11.7.4 During the Halt State If the CE pin is high level, the set state is held. 64 µPD17015 PD17015 12. BEEP 12.1 CONFIGURATION AND FUNCTIONS Fig. 12-1 shows an overview of BEEP. A 3-kHz clock is output from the P0D0/BEEP pin. According to the settings of the BEEP0SEL flag of the LCD enable register, the output switching block controls whether the P0D0/BEEP pin functions as a general-purpose output port or as a BEEP output pin. The clock generation block generates the 3-kHz clock to be output to the BEEP pin. Fig. 12-2 shows the configuration and functions of the LCD enable register. Fig. 12-1 Overview of BEEP BEEP0SEL flag Output switching block P0D0/BEEP 3 kHz Clock generation block Fig. 12-2 Configuration and Functions of the LCD Enable Register Flag symbol Name LCD enable register Address b3 b2 b1 L C D E N B E E P 0 S E L P 0 A B I O 1 P 0 A B I O 0 Read/write b0 4 6AH R/W Sets the function of the P0D0/BEEP pin. Uses the P0D0/BEEP pins as a general-purpose output port. 1 Upon reset 0 Uses the P0D0/BEEP pin as a BEEP output pin. Power-on 0 0 0 0 Clock-Stop 0 0 0 0 CE Hold 65 µPD17015 PD17015 12.2 12.2.1 STATE AT RESET At Power-On Reset The BEEP0SEL flag is reset. Consequently, the P0D0/BEEP pin is used as a general-purpose output port. Because the latch value for the output port is not defined, the port outputs undefined data. 12.2.2 At Clock-Stop Reset The BEEP0SEL flag is reset. Consequently, the P0D0/BEEP pin is used as a general-purpose output port. Because the latch value is not defined for the output port, the port outputs undefined data. 12.2.3 At CE Reset The P0D0/BEEP pin holds the previous output state. 12.2.4 During the Halt State The P0D0/BEEP pin holds the previous output state. 66 µPD17015 PD17015 13. LCD CONTROLLER/DRIVER The LCD (liquid crystal display) controller/driver, in combination with the segment signal output, controls an LCD display of up to 36 segments. 13.1 Overview Fig. 13-1 shows an overview of the LCD controller/driver. The LCD controller/driver controls a display consisting of up to 36 segments by using both the common signal output (COM0 to COM3 pins) and segment signal output (LCD0 to LCD8 pins). The driving method features a 1/4 duty cycle and 1/2 bias, a frame frequency of 150 Hz, and a driving voltage of VDD - VLCD0. Fig. 13-1 Overview of LCD Controller/Driver LCD0 pin Segment signal output timing control block LCD segment register (data memory space) LCD8 pin COM0 pin COM3 pin Common signal output timing control block Basic clock for timing control LCDEN flag VLCD0 pin VLCD1 pin CAP0 pin CAP1 pin LCD driving voltage generation block Remark LCDEN (bit 3 of the LCD enable register; see Fig. 13-6) turns the entire LCD display on or off. 67 µPD17015 PD17015 13.2 LCD DRIVING VOLTAGE GENERATION BLOCK The LCD driving voltage generation block generates the voltage needed to drive the LCD. An external doubler of the µPD17015 PD17015 supplies the LCD drive voltage. To configure the doubler, connect capacitors to the VLCD0, CAP0, CAP1, and VLCD1 pins. 5 Fig. 13-2 shows a sample doubler configuration. To use a voltage of 3.0 V (TYP.), connect capacitors as shown in Fig. 13-2. 5 Fig. 13-2 Sample Doubler Configuration C1 VLCD0 (36) CAP0 (35) C3 CAP1 (34) VLCD1 (33) C2 C1 = C2 = 0.1 µ F C3 = 0.01 µ F Remark Pin numbers are enclosed in parentheses. Note that the LCD driving voltage (VLCD) output by the doubler depends on the values of C1, C2, and C3. 68 µPD17015 PD17015 13.3 LCD SEGMENT REGISTER The LCD segment register sets the data indicating the LCD segments to be turned on or off. Fig. 13-3 shows the configuration and position of the LCD segment register in data memory. The LCD segment register exists in data memory and can, therefore, be controlled by all data memory manipulation instructions. One nibble of the LCD segment register sets the display data (turn-on/off data) for four segments. When a bit of the segment register is set to 1, the corresponding LCD segment is lit. When the bit is set to 0, the segment is not lit. Fig. 13-4 indicates the relationship between the LCD segment register and LCD segments, together with display examples. Fig. 13-3 Configuration of LCD Segment Register in Data Memory Column address Row address 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 A B C D E F Data memory LCD segment register System register LCD segment register Address 61H 62H 63H 64H 65H 66H 67H 68H 69H Symbol LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 LCDD8 b3 b2 b1 b0 69 70 Fig. 13-4 Relationship Between LCD Segment Register and LCD Segments, and Examples of Display LCD segment register Address 61H 62H 63H 64H 65H 66H 67H 68H 69H Symbol LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 Bit b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Display segment a b c d a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a e a e a e a e b b f b f b f b f c g c g c g c g d COM2 pin a c COM3 pin d h d h d h d h COM1 pin COM0 pin LCD8 pin LCD7 pin LCD6 pin LCD5 pin a LCD4 pin LCD3 pin a LCD2 pin LCD1 pin a LCD0 pin a a b c d f g e b f e c d g h b f c d g e h b f c d g e h b c d h µPD17015 PD17015 µPD17015 PD17015 13.4 TIMING CONTROL BLOCKS FOR OUTPUTTING COMMON SIGNAL AND SEGMENT SIGNAL Fig. 13-5 shows the configuration of the timing control blocks for outputting the common signal and segment signal. The common signal output timing control block controls the timing of the common signal output on pins COM0 to COM3. The segment signal output timing control block controls the timing of the segment signal output on pins LCD0 to LCD8. The common signal and segment signal are output when the LCDEN flag of the LCD enable register is set to 1. Setting the LCDEN flag to 0 turns off the entire LCD display. (See Fig. 13-6.) When the LCD display is turned off, the signals output from pins COM0 to COM3 and pins LCD0 to LCD8 are held low. Fig. 13-5 Configuration of Timing Control Blocks for Outputting Common Signal and Segment Signal b0 Segment signal LCD0 | LCD8 Segment signal output timing control block b1 b2 LCDD0 | LCDD8 b3 Basic clock for timing control Common signal COM0 | COM3 LCDEN flag Common signal output timing control block Fig. 13-6 Configuration and Functions of LCD Enable Register Flag symbol Name Address b3 LCD enable register b2 b1 L C D E N B E E P 0 S E L P 0 A B I O 1 P 0 A B I O 0 Read/write 6AH R/W b0 Turns the entire LCD display on or off. Turns the display off. (The output from all the segment and common pins is held low.) 1 Upon reset 0 Turns the display on. Power-on 0 0 0 0 Clock-stop 0 0 0 0 CE Hold 71 µPD17015 PD17015 13.5 COMMON SIGNAL AND SEGMENT SIGNAL OUTPUT WAVEFORMS Fig. 13-7 shows sample waveforms for common signal and segment signal output. The µPD17015 PD17015 outputs signals at a frame frequency of 62.5 Hz when driving at a 1/4 duty cycle and 1/2 bias (voltage 5 averaging method). The common signals output from pins COM0 to COM3 have a relative phase difference of 1/8 and three voltage levels (VLCD0, VLCD1, and VDD). The middle voltage level VLCD1 of the output common signals increases or decreases by 1/2 VDD. This display method is referred to as the 1/2-bias driving method. Each segment signal output pin outputs the segment signal with two voltage levels (0 and VDD) and phases corresponding to the display segments. As shown in Fig. 13-7, a single segment pin is used for four display segments (A, B, C, and D). Each segment pin can output 16 different combinations of phases, corresponding to the turning on and off of the display segments. A display segment is lit when the voltage difference between the common signal and segment signal is VDD. 5 The display segments are turned on in 1/4 duty cycles at a frequency of 62.5 Hz. This is referred to as the 1/4-duty display method. The frequency is referred to as the frame frequency. 72 µPD17015 PD17015 Fig. 13-7 Common Signal and Segment Signal Output Waveforms COM0 pin A COM1 pin B COM2 pin C COM3 pin D Segment signal output pin (LCDn pin) Common signal Single frame (6.7 ms) 1.7 ms COM0 pin COM1 pin VLCD1 VLCD0 GND VLCD1 VLCD0 GND VLCD1 COM2 pin VLCD0 GND COM3 pin VLCD0 GND VLCD1 Segment signal (examples) A, B, C, and D turned off VLCD1 LCDn pin GND A, B, C, and D turned on VLCD1 LCDn pin GND A, B, and C turned on; D turned off VLCD1 LCDn pin GND 73 µPD17015 PD17015 13.6 USING THE LCD CONTROLLER/DRIVER Fig. 13-8 shows an example of LCD panel connection. The following sample program turns on the 7-segment display with the LCD0 and LCD1 pins. Example WORK MEM 0.00H ; Work area PMNO MEM 0.01H ; Storage area of preset memory number CH FLG LCDD0.1 ; Defines the low-order one bit of LCDD0 as the symbol CH display. ; Display segment data ;LCDDATA: ; ; abcdefg­ DW 0000000011111100B 0000000011111100B ; 0FCH0 ; DW 0000000001100000B 0000000001100000B ; ; DW 0000000011011010B 0000000011011010B ; 0DAH2 ; DW 0000000011110010B 0000000011110010B ; 0F2H3 ; DW 0000000001100110B 0000000001100110B ; 66H4 ; DW 0000000010110110B 0000000010110110B ; 0B6H5 ; DW 0000000010111110B 0000000010111110B