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TURBO-ENCO-PM-UT3 Lattice Semiconductor Corporation IP CORE TURBO ENCODER ECP2M visit Digikey Buy
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turbo encoder model simulink

Catalog Datasheet MFG & Type PDF Document Tags

vhdl code for DES algorithm

Abstract: XAPP921c Reed-Solomon Decoder 4 Reed-Solomon Encoder 4 Turbo Convolutional Code Decoder, CDMA2000/3GPP2 4 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 4 UMTS/3GPP Turbo Convolutional Decoder 4 UMTS/3GPP Turbo Convolutional Encoder 4 IEEE 802.16 TPC Encoder 4 IEEE 802.16 TPC , (MC-XIL-RSDEC) 4 Avnet Reed Solomon Encoder (MC-XIL-RSENC) 4 Avnet Turbo Decoder, 3GPP 4 , Turbo Encoder, DVB-RCS (S2001) 4 iCoding Technology, Inc. Turbo Product Code Decoder, 160 Mbps
Xilinx
Original
vhdl code for DES algorithm XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model XILINX vhdl code REED SOLOMON encoder decoder

verilog code for 2-d discrete wavelet transform

Abstract: XAPP921c Interleaver / De-interleaver Reed-Solomon Decoder Reed-Solomon Encoder Turbo Convolutional Code Decoder, CDMA2000/3GPP2 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 UMTS/3GPP Turbo Convolutional Decoder UMTS/3GPP Turbo Convolutional Encoder IEEE 802.16 TPC , Solomon Decoder (MC-XIL-RSDEC) Avnet Reed Solomon Encoder (MC-XIL-RSENC) Avnet Turbo , ) TurboConcept Turbo Encoder, DVB-RCS (S2001) iCoding Technology, Inc. Turbo Product Code Decoder
Xilinx
Original
verilog code for 2-d discrete wavelet transform simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl fpga based wireless jamming networks

turbo encoder model simulink

Abstract: xilinx TURBO decoder 5, 2006 Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurements Using System , high performance forward error correction (FEC) algorithms, such as the Turbo Encoder/Decoder, can be , Xilinx 3GPP Turbo Encoder and Decoder cores is incorporated into a System Generator design to provide , sheet for the Turbo Encoder V2_0. · tcc_decoder_3gpp_v1_0 - the data sheet for the Turbo Decoder , , logic gates, etc.) and custom blocks, such as the Xilinx Turbo encoder and decoder. Figure 2 shows that
Xilinx
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XAPP948 ML402 xilinx TURBO decoder FER performance of the Turbo code matlab code turbo encoder design using xilinx Turbo decoder Xilinx vhdl code for siso shift register

matlab codes for wcdma rake receiver

Abstract: 3G HSDPA circuits diagram synthesizable VHDL netlist from Simulink model. This netlist includes IP blocks that have been carefully , processing for data additionally includes turbo encoding and decoding. Chip-rate processing involves the , techniques such as FIR filters, FFT/IFFT, and turbo convolution coding/decoding are being used in baseband , SRL16s can be seen by using a simple Reed-Solomon encoder example. Implementing a single-channel Reed-Solomon encoder in a Virtex-4 device can consume 56 logic slices. For a 16-channel implementation, one
Xilinx
Original
matlab codes for wcdma rake receiver 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink XAPP726

soft 16 QAM modulation matlab code

Abstract: ofdm modem simulink processing IP blocks provided with the DSP Builder to create a hardware implementation of a Simulink system model. The DSP Builder contains bit- and cycle-accurate Simulink fixed-point blocks, which cover basic , Turbo Decoder Function Turbo Encoder Function Viterbi Compiler, High-Speed Parallel Decoder Viterbi , Plus RTL simulation allows you to simulate an RTL model of a MegaCore function in your design. You can , Figure 4. DSP Builder: Quartus II & MATLAB/Simulink Interface The Altera DSP Builder is a DSP
Altera
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soft 16 QAM modulation matlab code ofdm modem simulink GSM 900 simulink matlab 16 QAM modulation matlab code matlab code for audio equalizer programmable interrupt controller 8259A

CRC matlab

Abstract: dsp processor design using vhdl data-intensive DSP functions such as Viterbi encoder/decoder and FIR filters. To work around this problem, DSP , Viterbi coprocessor, turbo coprocessor and the enhanced filter coprocessor. While such coprocessor blocks , a DSL router, a DSL modem, a JPEG encoder, a digital broadcast system, or a backplane switch fabric , , Rjindael) Error-correction cores (e.g., Viterbi, Turbo, CRC) Each of these functions are parameterized , DSP algorithms and Simulink for system-level modeling. The algorithms and the system-level models are
Altera
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CRC matlab dsp processor design using vhdl how dsp is used in radar radar dsp processor VHDL code of DCT by MAC qpsk simulink matlab

vhdl code for ofdm transceiver using QPSK

Abstract: soft 16 QAM modulation matlab code Turbo Encoder Function Altera Corporation Viterbi Compiler, High-Speed Parallel Decoder Altera , RTL model of a MegaCore function in your design. You can perform simulation using either the Visual , , simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools , and Simulink blocks with Altera DSP Builder blocks and fx Altera IP MegaCore functions to link , create a hardware implementation of a system modeled in Simulink in sampled time. DSP Builder contains
Altera
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vhdl code for ofdm transceiver using QPSK verilog code for ofdm transmitter dac 0808 interfacing with 8051 microcontroller vhdl code for ofdm transmitter uart 16750 16 QAM adaptive modulation matlab ARM922T

netxtreme 57xx gigabit controller

Abstract: Broadcom 57xx 3GPP Turbo Encoder/Decoder Forward Error Correction system is performed. © 2007 Xilinx, Inc. All , (similar to the model described in the "Simulink Simulation" section). For the second timeline, a single , model that is shown in Figure 5. See "Simulink Simulation," page 18 for detailed information , Simulation A normal Simulink simulation is performed on the demonstration model without any modifications , into the Simulink® simulation environment. · understand the motivation for and operation of
Xilinx
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XAPP1031 netxtreme 57xx gigabit controller Broadcom 57xx FIR FILTER implementation xilinx netxtreme 2007A broadcom netxtreme 57xx

abstract for wireless technology in ieee format

Abstract: abstract for mobile bug significant processing capabilities. In addition, several advanced signal processing techniques such as Turbo , performed by first passing the data in block format through the RS encoder and then passing it through a zero-terminating convolutional encoder. To implement these schemes, Altera provides the RS Compiler and Viterbi , . Turbo convolutional codes and Turbo Block codes are specified as optional FEC schemes in the standard , algorithms involved in WiMAX system design are usually implemented by designers in a high level model such
Altera
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abstract for wireless technology in ieee format abstract for mobile bug simulink model adaptive beamforming matlab code for mimo ofdm stc OFDM MRC Matlab code rls simulink

turbo encoder model simulink

Abstract: vhdl code for interleaver Specifications DSP Builder Feature & Simulation Support You can create Simulink Model Files (.mdl) using , .24 Using the Core with Simulink & DSP Builder , /Deinterleaver MegaCore function, customized for Altera devices, works with error-correction encoder/decoders , environment. You can combine existing MATLAB functions and Simulink blocks with Altera DSP Builder blocks to , algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink
Altera
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vhdl code for interleaver vhdl code for block interleaver design for block interleaver deinterleaver umts simulink matlab umts simulink block interleaver in modelsim

CTC 313

Abstract: bpsk simulink matlab measurements. Within the hardware design, a noisy channel model is used to test the encoder/decoder , referred to as encoder and decoder) perform duo binary turbo encoding and decoding of channel data as , test bench comprising: · UniSim® model of the CTC Encoder UniSim model of the CTC Decoder Advanced simulation using a test bench comprising: UniSim model of the CTC Encoder UniSim model , decoder must be generated. Generating the IEEE 802.16e CTC Encoder UniSim Model 1. Create a new
Xilinx
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XAPP1103 DS525 DS634 CTC 313 bpsk simulink matlab DO-DI-AWGN ML506 tcl script ModelSim ISE UG497 DS210

mini projects using matlab

Abstract: vhdl mini projects Access Controller FIR Complier Turbo Decoder Turbo Encoder PCI Master/Target PCI Target Parallel RapidIO Block Convolutional Encoder Block Viterbi Decoder CIC filter Correlator FFT Interleaver/De-interleaver NCO RS Decoder RS Encoder DDR DSRAM Controller DDR DSRAM Controller Pipelined , Generation New Examples 17 17 MATLAB/Simulink 18 Two New Blocks 18 Simulink Support for Additional , Simulink Block Does Not Support Saturation Logic 41 Limit on Interpolation Factor 42 Map Design Process
Lattice Semiconductor
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mini projects using matlab vhdl mini projects mini project simulink CODE VHDL TO LPC BUS INTERFACE matlab mini projects verilog code for digital calculator 1-800-LATTICE LCMXO640C LCMXO1200C

W75027

Abstract: interleaver 64-bit 10/100 Ethernet MAC Gigabit Ethernet MAC Reed Solomom Encoder Reed Solomom Decoder Turbo Encoder Turbo Decoder Block Viterbi Decoder Interleaver , . . . . . . . . . . . . . . . . . . . . . . . .4 ispLeverDSP and MATLAB/Simulink Support . . . . . , Intellectual Property Cores Support ispLeverDSP and MATLAB/Simulink Support Automake Browser , Controller ispLEVER 4.2 Release Notes - PC ispLeverDSP and MATLAB/Simulink Support Lattice has
Lattice Semiconductor
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W75027 interleaver ispLEVER project Navigator EC20 Schematic ifft ISC-1532

saf7730

Abstract: saf7730 audio Instruments TMS32003C6000 Texas Instruments TMS32003DRI20030 www.edn.com tool, Simulink, and allows , high-performance device tarworks.com) Matlab and Simulink software to HDL geting low system cost for wired and , DSP1641X architecture and instruction design and RTL testbench from Simulink. These files set include , using TSMC's 90-nm all copper, els in Verilog HDL, VHDL, model format for the Matlab envilow-K , and Simulink that facilitate algorithm prototyping in a drag-andphysical ports for both video in/out
DSP Directory
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saf7730 saf7730 audio wind energy simulink matlab Philips SAF7730 turbo codes matlab simulation program 64 point FFT radix-4 VHDL documentation

lcmxo2-1200

Abstract: LCMXO2-4000 Interleaver/De-interleaver P P P P P P Turbo Decoder P P Turbo Encoder , P PCI Express x4 PCS Pipe P P P Tri-Rate SDI PHY P Block Convolutional Encoder , P Dynamic Block Reed-Solomon Encoder P P P P FFT Compiler P P P P P , P P Block Convolutional Encoder P P Block Viterbi Decoder P P P Dynamic Block RS Decoder P P P P Dynamic Block RS Encoder P P P P FFT Compiler
Lattice Semiconductor
Original
lcmxo2-1200 LCMXO2-4000 DDR3 pcb layout guide DDR3 sodimm pcb layout schematic isp Cable lattice hw-dln-3c LCMXO2-640 I0211

vhdl program for parallel to serial converter

Abstract: schematic isp Cable lattice hw-dln-3c Numerically-Controlled Oscillator Turbo Decoder Turbo Encoder DDR SDRAM Controller - Pipelined DDR2 SDRAM Controller , ) P P P P P P P P Turbo Decoder Turbo Encoder P P P P 2D Edge , Detector 2D FIR Filter 2D Scaler Advanced FIR Filter Block Convolutional Encoder Block Viterbi Decoder , Arithmetic (DA) FIR Filter Dynamic Block Reed-Solomon Decoder Dynamic Block Reed-Solomon Encoder FFT , Convolutional Encoder P P P P Block Viterbi Decoder P P P P CIC Filter P P
Lattice Semiconductor
Original
vhdl program for parallel to serial converter I0211F

TMS320C6713 simulink

Abstract: F28335 with MATLAB . 55 MATLAB® and Simulink® for DSP Implementation . 40 Xilinx, Inc. Xilinx ISE , model that you create is best if you have a clear, undistorted measure of the signal going to the , as well by the time it reaches you. You are no longer able to develop an accurate model of the echo , without removing that person's speech. In order to remove the echo, you need to model the characteristics , interconnect · Universal test and operation PHY interface for ATM (UTOPIA) · Viterbi and Turbo coprocessors
Texas Instruments
Original
TMS320C6713 simulink F28335 with MATLAB voice recognition matlab simulink space vector modulation F28335 TMS320C5510 MATLAB TMS320C67XX* internal architecture XDS560R XDS510USB XDS510 XDS510PP C2000 XDS10LC

Single-Phase power monitor with two-level control

Abstract: TMS320f2812 pwm vector code source are wordmarks of ARM Limited Company. MATLAB and SIMULINK are trademarks of The Mathworks, Inc , infrastructure · Viterbi decoder co-processor (VCP) supports over 350 voice channels at 12.2 kbps · Turbo , on-chip Turbo (TCP) and Viterbi (VCP) coprocessors. ° HPI is selectable, 32-bit or 16-bit. § The DM642
Texas Instruments
Original
Single-Phase power monitor with two-level control TMS320f2812 pwm vector code source motorola vip 1853 tutorial TMS320f2812 pwm vector PIC Microcontroller GSM Modem Block Diagram of Trapezoidal Controller for BLDC TMS320C6000TM TMS320C5000TM TMS320C2000TM TMS320C64

tms320c6713 camera interfacing

Abstract: TMS320C5416 echo cancellation 12.2 kbps · New Turbo decoder co-processor (TCP) supports 35 data channels at 384 kbps 6 , is for TMS devices only. *UTOPIA pins muxed with a third McBSP. *Plus on-chip Turbo (TCP) and , Decoder Coprocessor User's Guide SPRU533 TMS320C6211 Data Sheet SPRS073 Turbo Decoder , Analog-to-Digital Converters for the TMS320C6000 DSP Platform Model fs , 0.6 mW/+2.7/+5 V 3.64 Res. Model (Bits) 50 kSPS < fs
Texas Instruments
Original
tms320c6713 camera interfacing TMS320C5416 echo cancellation TMS320C6713 DSK image processing kit diagram tms320c5416 architecture diagram TMDS320006711 TMS320C6713-150

night vision technology documentation

Abstract: DP8051 Matlab/Simulink environment (available separately from The Mathworks). The ispLEVER 4.2 release
Lattice Semiconductor
Original
night vision technology documentation DP8051 radix-2 DIT FFT vhdl program atmel 336 M25PXX 16 point FFT radix-4 VHDL ECP-DSP20 NL0109
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