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ttl 7474 14 PIN

Catalog Datasheet MFG & Type PDF Document Tags

TTL 74ls74

Abstract: 74ls74 "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , '" KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3
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TTL 74ls74 74ls74 CI 7473 7476 JK TTL 7474 ttl 7474 14 PIN 54S/74S109 54LS/74LS109 54H/74H73 54LS/74LS73 54LS/74LS107 54H/74H103

7474 D flip-flop

Abstract: 2-DIGIT 7-SEGMENT LED DISPLAY schematic diagram reference voltage. · Over-range and under-range signals available for autoranging. · TTL compatible , HI 10 ICL8052A R LADDER ICL7103A IN LO 14 11 ANALOG GROUND 7 18 13 27 , anode pin of its respective 7 segment display. The position of the zero bit in the shaft register and , S 0.22µF 2N2007 10k #1 -15V #4 S STROBE (PIN 18) 1/4 - 7406 2N3686 D D , #1 14 1/4 - 7403 #2 9 +5V 30k DCV 1/4 - 7406 7 8 10µF 5
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7474 D flip-flop 2-DIGIT 7-SEGMENT LED DISPLAY schematic diagram zestron reed relay 7474 for shift register shift register by using D flip-flop 7474 application notes 74121 ICL7103A/ICL8052A AN028 ISO9000

TTL 74ls74

Abstract: 7474 14 PIN "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 , Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12
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7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73

ic D flip flop 7474

Abstract: T flip flop IC in a 14 pin dual-inline package. ABSOLUTE MAXIMUM RATINGS Supply voltage V(:c , TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops , output drive-capability normally gained with TTL circuits are retained. ABSOLUTE MAXIMUM RATINGS Supply , Temperature (soldering 10 PIN CONNECTION 3a QA GND KB 14 13 12 |11 10 CLEAR CLOCK fg lQ CLEAR CLOCK TT J |4 5 tü Vcc t> O TRUTH
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ic D flip flop 7474 T flip flop IC JK flip flop IC ic 7474 features of ic 7474 7474 j-k flip flop

ICL7103A

Abstract: zestron reed relay reference voltage. · Over-range and under-range signals available for autoranging. · TTL compatible , HI 10 ICL8052A R LADDER ICL7103A IN LO 14 11 ANALOG GROUND 7 18 13 27 , anode pin of its respective 7 segment display. The position of the zero bit in the shaft register and , S 0.22µF 2N2007 10k #1 -15V #4 S STROBE (PIN 18) 1/4 - 7406 2N3686 D D , #1 14 1/4 - 7403 #2 9 +5V 30k 1/4 - 7406 7 8 10µF 5 Application
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ICL7103 7474 D flip-flop circuit diagram zestron 278 74121 application as pulse generator transistor 2N2007 Low Cost Digital Panel Meter Designs

ttl 7474 sine wave

Abstract: 74590 divides the 1.2288MHz signal by 214, which results in a 75Hz signal being fed into Pin 3 of the 7474. The 7474 further divides this signal by four, to 18.75Hz. This signal will appear at Pin 9 depending upon the signal level at Pins 1 and 10. If Pins 1 and 10 are low, Pin 9 will be held at a TTL high. If Pins , capacitor, RT and Ct, are selected such thatthisoto + 1V signal seen at Pin 4 results in a Oto 500kHz output frequency. The pull-up resistor, R3. ensures that the AD654 output meets the logic levels required atT1 (Pin
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AN-276 ttl 7474 sine wave 74590 INTERFACING OF SEVEN SEGMENT DISPLAY WITH 8051 74ls221 circuits diagram frequency counter using 8051 74LS04* hEX INVERTER

MC4044

Abstract: frequency counter using 8051 frequency directly into the counter input pin of the 7208 counter-decoder-driver. The 4020Bs are 14 , -bit binary counters with output registers, one 4020B 14-stage binary counter, one 7474 dual D-type flip-flop , results in a 75Hz signal being fed into Pin 3 of the 7474. The 7474 further divides this signal by four , Pins 1 and 10 are low. Pin 9 will be held at a TTL high. If Pins 1 and 10 are high, the 18.75Hz square , capacitor, RT and CT, are selected such that this 0 to +1V signal seen at Pin 4 results in a Oto 500kHz
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MC4044 Voltage-to-Frequency Converters 74LS221 74ls04hex 7208 display driver 74LS221 P SN7474 MC6801

CI 7474

Abstract: CI 7473 "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , '" KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3
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CI 7474 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 54S/74S114 54LS/74LS 54LS/74LS78 93L14 54LS/74LS279 54LS/74LS196

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H , - K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S/74S114, 54LS/74LS114 4 J> 10 i 3 â'" J sd Q â'" S 11 Sd J Q 13- CP CP 2â'" K Cd 0 0-6 12 K Co 0 Vcc = Pin 14 GND = Pin 7 13-50 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS Item Function DEVICE NO. Inputs , 4 10 3â'" 1 2 Sd J 0 -5 1-i J S° 0 CP 13-0 CP K _ Co Q oâ'"6 3£ K ^ Cd 0 Vcc = Pin 5 GND =
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7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 7473 pin diagram 7476 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113

7472 PIN DIAGRAM

Abstract: 74574 J O â'" 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 1ÌE0 J S° o â'" 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED So J Q â'" 8 CP K O 0â'"6 Cd Vcc = Pin 14 GND = Pin 7 13-48 FAIRCHILD DIGITAL TTL TTL , D54 54/7470 13 Vcc = Pin 14 GND = Pin 7 T 13 Vcc = Pin 14 GND = Pin 7 19-olâ'"^ So CP KCo ~~7 Vcc = Pin 14 GND = Pin 7 111 O D 111 O z o (9 111 > H < (9 ui Z o (0 111 u z < z o 3
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74574 TTL 7472 7473 dual JK 7472 ttl O9111 7472 ci 54H/74H71 54H/74H101 74H71 54LS/74LS113
Abstract: -1 6 Pin Dual-in-line Power Ceramic Package UC1717 UC3717 -V m -+5V ENAA +Vm 3,14 , .45V Input Voltage Logic Inputs (Pins 7 8 9) 6V Analog Input (Pin 1 0 ) . Vcc Reference Input (Pin Note 1: AI1 voltages are with respect to ground, Pins 4,5 12, 13. Pin numbers refer to DIL-16 package , DIAGRAM VCC AOUT BOUT 5/93 6-71 â  T 3 4 a s n DQiaaat, ?a â  3,14 VM UC1717 -
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UC1717SP UC3717N UC1717JP DD132T3

C2717

Abstract: 7474 pin out diagram itations a n d considerations o f package. BLOCK DIAGRAM Vcc AOUT BOUT 3,14 VM 7/95 10-97 , ).6V Analog Input (Pin 1 0 ) . Vcc Reference Input (Pin 1 1 , PIN FUNCTION FUNCTION PIN N/C 1 Bo u t 2 Timina 3 Vm 4 Gnd 5 N/C 6 Gnd 7 Vcc 8 h 9 Phase 10 N/C 11 lb 12 Current 13 Vr 14 Gnd 15 N/C 16 Gnd 17 Vm 18 A out 19 Emitters 20 [T Ï6] Em itters 15] A o u
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C2717 7474 pin out diagram pin diagram of 7474 7474 pin configuration three phase pulse generator wind Stepping Motors diagram UC2717 UC1717J
Abstract: ). 6V Analog Input (Pin 1 0 ) . Vcc Reference Input (Pin 1 1 , 50°C Note 1: All voltages are with respect to ground, Pins 4,5, 12, 13. Pin numbers refer to DIL , DIAG RAM VCC AOUT BOUT â I 3,14 VM ^34051=] 001474fcj 5^3 UC1717 UC3717 CO NN ECTIO , 16 7 13] Gnd 17 6 Vm 15 14 8 12j Gnd Gnd [5 vg Vcc H 9 10 11 12 13 -
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UC3717S

pin diagram 7400 series

Abstract: CI 7474 15 +15V Pin 11 Analog Ground Pin 14 Analog in Pin 12 N/C (int.ref.models) -V ref in (ext.ref.models , .670 mW, Typical â  Wide Operating Temperature Range. -55°C to + 125°C â  Small Size.24-Pin , with a 1 MHz clock. HS 5210 Series hybrid microcircuit converters are housed in hermetically-sealed 24-pin , 5211/14), ±10 volts (HS 5212/15), and 0 to +10 volts (HS 5216). For each of these input ranges, the , (Models HS5213. 14, 15) volt« SPECI FICATIONS (Ta=25°C, Voltages ±15, +5 Unless otherwise stated
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pin diagram 7400 series hs 111-0 7400 fan-out TTL CI 7400 74164 7474 PIN DIAGRAM MIL-STD-883 HS52XXC HS52XXB

7476 truth table

Abstract: 7474 truth table 8-272 8-72 8-76 8-79 8-80 8-265 8-265 8-265 Dual 4 -Input 24 48 22 24 48 12 30 28 28 28 19 14 , s A X 25 10 15 50 TTL/MSI 93178/54178, 74178 93179/54179, 74179 4-BIT SHIFT , 13 12 15 14 I ° A °B CLOCK I °C I °D I rd d a I o I I O o Dq a , Hold Parallel Entry Shift Right Shift Right LOAD L H L H S H IFT i 4 i f 6 8 i 10 Pin nu , c da °C >4 2 L ,3 » C ,2 ^ c 3 C « c 14 Ds ^OUT SHIFT 13 12 AOUT CLOCK
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82S62 7476 truth table 7474 truth table se 9315-1 fairchild 9322 signetics 8281 93L22 93L09 93L12 93S12 93H00 93S00

full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of evaluation. · TTL/CMOS I/O compatibility. · Design implemented using Altera's A+PLUS Development System · Advanced CHMOS circuitry features low power, high performance, and high noise immunity · Includes 68-pin , speeds and density of the EP1800 series make it suitable for LSI replacement of Low power Schottky TTL in , commonly used TTL SSI and MSI functions. These aid the first time user since the function of these blocks
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full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 OUT10

ic 7483 BCD adder

Abstract: 9N01 PHILIPS FAIRCHILD PIN FOR PIN REPLACEMENT 9N74, 7474 9390,7490 9391,7491 9375,7475 9N76, 7476 9393,7493 , 11 12 7 4x2 5 5 4 12 9 4 30 20 55 18 40 16 14 Power Dissipation mW 105 150 250 176 390 400 110 450 , TTL/MSI 93176/54176, 74176 93177/54177,74177 BCD DECADE/4-BIT BINARY COUNTER TO EE ANNOUNCED , 11 LOG IC D IA G R A M 93176/54176, 74176 Pin nu m b ers are show n fo r D IP o n ly . CO , 7400 8200 8210 8211 8213 8220 8223 8280 8281 8283 i i FAIRCHILD PIN FOR PIN REPLACEMENT FAIRCHILD
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ic 7483 BCD adder 9N01 ic 7483 full adder function of ic 7490 IC 7490 pin configuration 9N03 93H183 93S41 93S42 93L24 93S62 93H87

TC430

Abstract: external DIAGRAM OF IC 7474 j z 0.1 pF 100 3 11 14 74S74 1 6 TC430 5 -O 01 12 2 7 TTL START IN 13 4 1 a9 ' -O 02 1 i 100 1 14 1/2 7474 0.1 JIF 0.1 pF 2 kO , TC430 FAST CMOS CCD DRIVER FEATURES Operating Range 4.5V « (V dd - Vss) « 12V TTL , Diode Driver Differential Line Driver PIN Diode Driver Level Shifting Driver FUNCTIONAL DIAGRAM V DD , swings between positive and negative supplies without sacrificing AC performance when driven from TTL
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external DIAGRAM OF IC 7474 teledyne tsc TC430C IC 7474 pin configuration logic ic 7474 pin diagram QGD73 Q0073

TC430CPA

Abstract: V01Q TTL START IN 13 4 1 7 *1 2 9 2 TC 430 7 -O 02 14 5 12 1 +5V -A A /V Z Z 0.1 nF 10£i 1 6 5 -O 01 io n tI 1 1/2 7474 7 6 - O TIMING SIGNAL OUT 14 0.1 tiF 0.1 (JF 2kO < I , .4.5V « (V dd - Vss) « 12V TTL/CMOS-Compatible Inputs Low Delay T im e , MOSFET Driver Laser Diode Driver Differential Line Driver PIN Diode Driver Level Shifting Driver , frequencies to 10 MHz and drives loads greaterthan 2200 pF. Peak current output is 3A. The input is TTL/CMOS
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TC430CPA V01Q DS0026 power mosfet driver

MH1SS1

Abstract: TESLA mh 7400 , OC, TTL 15 V TTL 3 NOR-Gatter, je 3 E TTL NAND-Gatter mit 8 E DIP 1* DIP 14 DIP DIP DI? DIP DIP , 14 14 14 4 Bit-Volladdierer 4 Bit-Vergleicher TTL TTL 4 . Exklusiv-OR-Gatter, je 2E TTL , Binärer Q au ^-PrioritätSenkodex* TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL DIP 16 DIP 14 DIP 14 DIP 16 , DIP -14 DIP 14 DIP 14 2 NAND-Treiber, je 2 E TTL BCD- zu 7-Segment-Dekoder-/ TTL Treiber BCD , und AE TTL DIP 16 -25/85 2 NAND-Gatter, je Gatter TTL DIP 14 0/70 1 separater Ein-;/Ausgang 6
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MH1SS1 TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L
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