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Part Manufacturer Description Datasheet BUY
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
CD4504BKMSR Intersil Corporation HEX TTL/CMOS TO CMOS TRANSLATOR, INVERTED OUTPUT, CDFP16 visit Intersil
SN74122J-00 Texas Instruments TTL/H/L SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 visit Texas Instruments
SN74123J Texas Instruments TTL/H/L SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP14 visit Texas Instruments
SN74121J-00 Texas Instruments TTL/H/L SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 visit Texas Instruments
SN74221J Texas Instruments TTL/H/L SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16 visit Texas Instruments

ttl 74183

Catalog Datasheet MFG & Type PDF Document Tags

7408 CMOS

Abstract: TTL 7452 intervals along the row and column of the chip, also consist of I/O pads which are compatible of CMOS or TTL , Toggling Frequency: 40MHz â'¢ High density 3.5 micron geometries â'¢ TTL and CMOS I/O compatibility â , OF LS TTL TTL Pari No. Count TTL Part No. Count TTL Part No. Count TTL Part No. Count 7400 4 7470 , 39 7438 4 74103 20 74183 16 74362 44 7440 4 74106 20 74184 100 74363 28 7442 29 74107 20 74185 100
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IC TTL 7432

Abstract: IC 7402, 7404, 7408, 7432, 7400 IC Tester Software version 2.08 Series 54/74 TTL ICs 7400 7401 7402 7403 7404 7405 7406 7407 , 74174 74175 74176 74177 74178 74179 74180 74181 74182 74183 74184 74185 74188 74189 74190 , the TTL section 4000 4001 4002 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016
ABI Electronics
Original

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 /Vila are TTL level normal input buffers Vihb/Vilb are CMOS level normal input buffers Vmc/Vac are TTL , Min. Typ. Max, TTL level schmitt Trigger input threshold voltage VT+ - â'" 1,2 1.7 2.3 V VT- 0.8 , mm 1.0 1.5 2.0 ns 2ND (I: metal wiring length) 1.4 2.1 2.3 TTL level input buffer delay time , '" Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS , -42-41 Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS
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IC AND GATE 7408 specification sheet

Abstract: 74LS96 Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3 , Page 325 PLS-EDIF Data Sheet Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 2 o , 74161 74162 74163 74164 74165 74166 74168 74169 74173 74174 74175 74181 74183 74190 74191 74192 74193 , . TTL Function Mappings in Altera-Provided LMFs (Part 3 o f 3) MAX+PLUS 74260 74261 74273 74279 74280
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74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 74169 74173 74174 74175 74181 74183 Page 334 Altera Corporation Data Sheet PLS-WS/HP , a NETED function to map. If no equivalent function currently exists in the MAX+PLUS II TTL , > Step 2: Design an equivalent circuit in AHDL if no equivalent function exists in the MAX+PLUS II TTL , relational operations. It is hierarchical, so that frequently used functions such as TTL and bus
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ic 74226

Abstract: jk flip flop 74103 N UM B ER OF GATES · TTL 7 4 0 0 SERIES TTL Part N o. 7400 7401 7402 7403 7404 7405 7406 7407 7408 , 45 6 5 8 7 7 6 6 6 9 8 8 16 15 14 20 15 14 20 14 20 17 80 27 57 80 73 12 19 320 TTL Part N o. 7490 , 74172 74173 74174 74175 74176 74177 74178 74179 74180 74181 74182 74183 74184 74185 74190 74191 G ate E , 100 100 80 76 TTL Part N o. 74192 74193 74194 74195 74196 74197 74198 74199 74225 74226 74245 74246
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asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , '¢ Macro functional block: 84 types (TTL MSI equivalent) â'¢ All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available.) â'¢ All pins of pull-up or pull-down MOS (100 KÂ , level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5 BST Invert schmitt trigger
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sn 74373

Abstract: SN 74114 app ed to corresp o n d in g prim itive and T T L functions in the M A X + P L U S II TTL M a croF u , libraries can be m app ed to corresp o n d in g prim itive and TTL functions in the M A X + P L U S 11 T T L , 74LS153 - MAX+PLUS il TTL Macrofunction 74147 74148 74151 74153 74154 74155 74156 74157 74158 74160 74161 74162 74163 74164 74165 74166 74169 74173 74174 74175 74181 74183 74190 74191 74192 74193 74194 , 74LS377 74LS379 74LS381 74LS390 74LS393 MAX+PLUS II TTL Macrofunction 74279 74280 74283 74290 74293
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC QIC-24

truth table for ic 74138

Abstract: 16CUDSLR truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , includes basic logic gates and flipflops. The A+PLUS TTL M acroFunction Library has m ore than 120 TTLe q u , . Partial List of A+PLUS Macrofunctions Type Adder Com parator Converter Counter 7480, 7482, 7483, 74183
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truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table

priority encoder 74148

Abstract: priority encoder 74147 convert levels of both CMOS and TTL for all input/output buffers. Five types of master chips are prepared , â'¢ Macro functional block: 84 types (TTL MSI equivalent) â'¢ All pins of schmitt input circuit are available. (Both CMOS and TTL levels are availa-ble.f â'¢ All pins of pull-up or pull-down resistance (120 , . of buffer cell Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL
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MSM72000 priority encoder 74148 priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 MSM70000 MSM71000 MSM73000 MSM74000 MSM75000

counter 74168

Abstract: 3-8 decoder 74138 is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , functional block: 84 types (TTL MSI equivalent) â'¢ All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available.) â'¢ All pins of pull-up or pull-down MOS (100 Ki2) are available , buffer cell Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5
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counter 74168 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74169 binary counter MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop convert levels of both CMOS and TTL for all input/output buffers. Ten types of master chips are prepared , : 31 types â'¢ I/O block: 57 types â'¢ Macro functional block: 84 types (TTL MSI equivalent) â'¢ All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available ) â'¢ All , Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5 BST Invert schmitt
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74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 jk flip flop to d flip flop conversion 74541 buffer design excess 3 counter using 74161 MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000
Abstract: ⺠Vcc PE CEP CET Do D a Di 54/74LS162/ OR 54/74183 OR 54/74LS163/ TC CP , 70 TEST CIRCUITS AND WAVEFORMS VM = 1.3V for 74LS; VM = 1.5V for all other TTL families -
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LS160A LS161A LS162A LS163A 74LS160A 74LS163A

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 , available, Pull-up/pull-down Input buffers available. Single 5V power supply. TTL com patible I/O, CM O S , Industry-standard TTL devices. They are Identical In application to user macroa. Using F-Macros, a designer may , function of many popular Industry-standard TTL devices and RAM macros which provide from 1K to 2K of , 's F-Macros are direct software macro Implementations of popular Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate
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up down counter using IC 7476 full adder using Multiplexer IC 74151 74154 shift register IC full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 0010S MB65XXXX MB66XXXX MB67XXXX

7408, 7404, 7486, 7432 use NAND gate

Abstract: JLCC-68 10.0 mA, available. Puli-up/pull-down input buffers available. Single 5V power supply. TTL , F-Macros are created and offered by Fujitsu to emulate the function of popular Industry-standard TTL , (F-Macros) which duplicate the function of many popular Industry-standard TTL devices and RAM macros which , Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate array will find the F-Macro a particularly useful Implementation
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LCC-64 JLCC-68 7408, 7404, 7486, 7432 use NAND gate ci 74386 jLCC68 74153 full adder cI 74150 C4002 C1502 CDIP-16 CDIP-18

counter 7468

Abstract: umi u26 5V power supply. TTL compatible I/O, CMOS input and Schmitt trigger Input. Popular CAE , created and offered by Fujitsu to emulate the function of popular industry-standard TTL devices. They are , industry-standard TTL devices and RAM macros which provide from 1K to 2K of single-port static RAM on chip. Also , Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate array will find the F-Macro a particularly useful Implementation
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counter 7468 umi u26 74181 74175 clock ci 7483 74154 chip configuration D-6000 J22833 CA95054-3197

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER ICTTL/CMOS and Schmitt trigger I/O compatibility â'¢ Slew-rate output buffers â'¢ High density Static , hardware platform for a multitude of high performance systems previously requiring TTL, Schottky TTL and , provide standard 1.5V and 3.5V input levels. TTL input buffers provide standard 0.8V and 2.0V input levels. Schmitt trigger input cells offer 1.2V of hysterisis for CMOS levels and 0.7V for TTL levels. More details , D 1.80 DRVTx Clock Driver with TTL Level Input Buffer U D 1.29 IBUFx CMOS Level Input Buffer N U D
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74ls82 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 TC140G SC12D4

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC gate delays in the order of 0.4 ns · 200 MHz toggle frequency · ADVANCELL(TM > compatible · TTL/CMOS , performance systems previously requiring TTL, Schottky TTL and ECL solutions. Siemens Aktiengesellschaft 1 , 1.5V and 3.5V input levels. TTL input buffers provide standard 0.8V and 2.0V input levels. Schmitt trigger input cells offer 1.2V of hysterisis for CMOS levels and 0.7V for TTL levels. More details of , Level Input Buffer Clock Driver with CMOS Level Schmitt Input Buffer Clock Driver with TTL Level Input
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ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 4 BIT COUNTER 74669 XF107 SC18D4 SC27D4 SC37D4 SC44D4 SC54D4 SC68D4

LEAPER-3

Abstract: 74189 ,EEPROM, FLASH EPROM, PAL, ISPLSI, GAL, PEEL, TTL,PLD, MACH, CMOS, MAX,Microcontroller, SRAM/ DRAM, I , ,EEPLD,FPL, GAL ,PEEL ,CPL ,CMOS PAL: AMD ,ATME ,Cypress , HYUNDAI,ICT¡,GOULD,Lattice * TTL/CMOS:54 , 74179 74180 74181 74182 74183 74184 74185 74189 74190 74191 74192 74193 74194 74195 74196 74197 74198 , . *CPU 8751 and 8748 disassembler file. LEAP-SU1 TTL 54/74, CMOS 40/45, DRIVER, PPO, OPTO, SRAM , . *Built in 6 functions and 10 numerical keys. *Identifies over 1800 CMOS/TTL digital ICs (up to 24 pins
Leap Electronic
Original
LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration SU-2000 PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 va ila b le . S in g le 5V p o w e r s u p p ly . TTL c o m p a tib le I/O , C M O S In p u t a n d S , F-Macros are created and offered by Fujitsu to emulate the function of popular industry-standard TTL , duplicate the function of many popular industry-standard TTL devices and RAM macros which provide from 1K to , Fujitsu' s F-M acros are direct software macro implementations of popular Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL
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IC 3-8 decoder 74138 pin diagram full adder using ic 74138 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder IC 74195
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