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Part Manufacturer Description Datasheet BUY
10484S10C Integrated Device Technology Inc SB-28, Tube visit Integrated Device Technology
10480S10D Integrated Device Technology Inc CDIP-20, Tube visit Integrated Device Technology
10484S7C Integrated Device Technology Inc SB-28, Tube visit Integrated Device Technology
10484S8CB Integrated Device Technology Inc SB-28, Tube visit Integrated Device Technology
10480S15D Integrated Device Technology Inc CDIP-20, Tube visit Integrated Device Technology
10484S5CB Integrated Device Technology Inc SB-28, Tube visit Integrated Device Technology

trw 1048

Catalog Datasheet MFG & Type PDF Document Tags

trw 1048

Abstract: trw1048 Integrateli De vice Technology, Inc. CMOS FLASH A/D CONVERTER IDT75C48 FEATURES: 8-bit resolution 30 MSPS conversion rate Guaranteed no missing codes Pin- and function-compatible with TRW 1048 Low power consumption: 500mW Extended analog input range On-chip EDC (Error Detection and Correction) Improved output logie HIGH drive, no pull-up needed No sample and hold required Differentsai Phase < 1 Degree Diff-e rential Gain < 2% Selectable output formats TTL-compatible Availabfe in 28-pin CERDIP and
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trw 1048 trw1048 VlH24 Sample and Hold Amplifiers c 2579 power transistor MIL-STD-883 IDT75C4 75C48 16-II
Abstract: CMOS FLASH A/D CONVERTER Integrated Device Technology* Inc. IDT75C48 FEATURES: 8-bit resolution 30 MSPS conversion rate Guaranteed no missing codes Pin- and function-compatible with TRW 1048 Low power consumption: 500mW Extended analog input range On-chip EDC (Error Detection and Correction) Improved output logic HIGH drive, no pull-up needed No sample and hold required Differential Phase < 1 Degree Differential Gain < 2% Selectable output formats TTL-compatible Available in 28-pin CERDIP and LCC -
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trw1048

Abstract: trw 1048 CMOS FLASH A/D CONVERTER FEATURES: · 8-bit resolution · 30 MSPS conversion rate · Guaranteed no missing codes · Pin- and function-compatible with TRW 1048 · Low power consumption: 500mW · Extended analog input range · On-chip EDC (Error Detection and Correction) · Improved output logic HIGH drive, no pull-up needed · No sample and hold required · Differential Phase < 1 Degree · Differential Gain < 2% · Selectable output formats · TTL-compatible · Available in 28-pin Plastic DIP, CERDIP and LCC · Military
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C5-C14 HA-2539-5 UA741C LM313 2N2907
Abstract: M ITSUBISHI SEMICONDUCTORS & s n sc*o^e 5 M5M4C1000P,J,L-10,-12,-15 -n 1048 5 7 6 -B IT (1048 576-W ORD BY 1 -B IT ) DYNAM IC RAM â'"Fast Page Modeâ'" S E P , 16, 1986 , SEMICONDUCTORS M5M4C1000P,J,L-10,-12,-15 1048 5 7 6 -B IT (1 0 4 8 576-W ORD BY 1 -B IT )D Y N A M IC RAM , Remark Fast page mode id e n tic a l M ITSUBISHI SEMICONDUCTORS M5M4C1000P,J,L-10,-12,-15 1048 5 7 6 -B IT (1048 S76-WORD BY 1 -B IT )D Y N A M IC RAM ABSOLUTE MAXIMUM RATINGS Parameter -
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M5M4C1000J-10 M5M4C1000J-12 M5M4C1000J-15
Abstract: FLEX­ IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS The Lattice pLSI 1048 is a High-Density , Interconnectivity The basic unit of logic on the pLSI 1048 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 ,.F7, (see figure 1). There are a total of 48 GLBs in the pLSI 1048 device. Each GLB has , pLSI 1048 device are selected using the Clock Distribution Network. Four dedicated clock pins (YO, Y1 , Network can also be driven from a special clock GLB (DO on the pLSI 1048 device). The logic of this GLB -
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120-P LS11048 1048-80LQ 1048-70LQ 1048-50LQ 1048-50LQI
Abstract: reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLS11048E device adds two , > " u .6 6.5 7.5 13.5 15.0 15.0 th l tsu2 tco2 th2 tr1 trw l tptoeen tptoedis tgoeen tgoedis twh , .) fmax (Ext.) fmax (Tog.) tsul tcol thl tsu2 tco2 th2 tr1 trw l tptoeen tptoedis tgoeen tgoedis twh twl -
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1048C

CLCC 64 pins footprint

Abstract: 238Q . Max. Min. Max. Reset/Preset Parameters tRW Asynchronous Reset Width 10 12 15 20 ns tRR , â  r Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK " tRW " X X -tRcr zxxxx - *RR ' r , Pd = 928 mW. Add 15 mff per output for a total output Pd = 120 mW. Therefore, the total Pd = 1048 mW , commercial temperature range, for the PLCC: Tj = (1.048 W)(45°C/W) + 75"C = 122"C at 500 LFPM Tj = (1.048 W
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CY7C371 CY7C372 FLASH370 CLCC 64 pins footprint 238Q 7C371-66 7C371-83 100MH 22V10 T-90-20

ACT1020

Abstract: CY7C383-1JC tcwi.o Clock LOW Time 3.6 3.6 3.6 3.6 3.6 ns tsw Set Width 2.1 2.1 2.1 2.1 2.1 ns tRW Reset Width 1.9 1.9 ,   â'¢set tRW â  tRESET X Output Delay OUTPUT t0UTLH toUTHL 4-284 CYPRESS SEMICONDUCTOR bSE D 256^2 , . Therefore, the total Pd = 1048 mW. For a PLCC, 8ja = 45°C/W at 500 LFPM, and ©ja = 64'CAV for still air , Ta and Ta = 75'C worst-case commercial temperature range, for the PLCC: Tj = (1.048 W)(45°C/W) + 75"C = 122"C at 500 LFPM Tj = (1.048 W)(64°C/W) + 75'C = 142°C in still air This calculation is for
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CY7C384 ACT1020 CY7C383-1JC CY7C384-1GI 7c383 48 pin clcc footprint O443 CY7C383

trw 1048

Abstract: OF 8 pin DIP IC 1251 A/D Converters rnvw TRW offers a line o f high perform ance A /D converters that addresses applications from 50kH z to 100M Hz. For video bandwidths (on the order o f 10M H z), w e have converters with , d u s try -S ta n d a rd V ideo A /D . S ingle + 5 V P o w e r Supply. TD C 1048 P e rfo rm a n c e , = - 2 0 ° C to 9 5 ° C . TRW LSI Products Inc. 1 A/D Converters Product TMC1175 , e d M ilita r y D ra w in g , T ^ = - 5 5 ° C to 1 2 5 °C . 2 TRW LSI Products Inc.
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OF 8 pin DIP IC 1251 TDC1048 OD-1020 C1061 TDC1044 TDC1046 TDC1029 TDC1047 TDC1147

1048-50LQ

Abstract: isplsi device layout Semiconductor Corporation Features Lattice ispLSI and pLSI 1048 High-Density Programmable , T he ispLSI and pLSI 1048 are H igh-D ensity Program m able Logic D evices w hich contain 288 , is a rchitecturally and pa ra m e trica lly com patible to the pLSI 1048 device, but m ultiplexes , ispLSI and pLSI 1048 d evices is the G eneric Logic B lock (GLB). T he G LB s are labeled A0, A1 . F7 (see figure 1). T here are a total of 48 G LBs in the ispLSI and pLSI 1048 devices. Each G LB has 18
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isplsi device layout S9089 I1048 22222822225-2S

ORP10

Abstract: 1048 is a High-Density I 'rogi^mihabte Logic Device which contains 288 Regis ters, 9(5JJnjyersal I/O , total ol 48 GLBs in the pLSI 1048/883 device. Each GLB has 18 inputs, a pro grammable AND/OR/XOR array , Specifications pLSf 1048/883 T-4 6 -19-07 GND to 3.0V S3ns 10% to 90% 1.5V 1.5V See Figure 2 Figure 2 , u l to o l th1 tsu2 tco2 th2 trl trw l ten tdis twh twl tsu5 th5 1. 2. 3. 4. 5. UNITS 24 ns ns , pLSl 1048 883 Tim ing Model GRP Feedback I Pod. In #26 I/O Reg Bypass 4 PT Bypass #33 D
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ORP10 STD-6183 B13/C8 LS11048/883 G0S443 T-46-19-07 132-P
Abstract: Instruments Incorporated c 181 Dynamic R A M Modules TM4Z56FC1. TM4257FC1 1.048,576 BY 1 BIT , tW C S *CW L fRW L l CA H l RAH *AR t DH *DHR l DH fRCH tRRH tW CH *W CR tp c tPCM tRC *WC tRW C *CP , interval tRW D *REF l RCD 30 60 ns 120 4 ns ms Dynamic R A M Modules Continued next , Write-command hold time after C A S low W rite-command hold time after *W CS *CW L tRW L l CA H *RAH *AR *DH *DHR *DH tRCH *RRH tW CH *W CR tp c *PCM *RC (W C tRW C *CP *CPN *C A S tRP *RA S tW P *T XA S C l A SR -
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TM4256FC1 FC1-20 H551-H 77Q01
Abstract: 1048/883 in-system programmable Large Scale Integration High-Oensity Programmable Logic - - F ^ d 'r , » and parametrically compatible to the pLSI 1048/883 de - Synchronous and Asynchronous docks vice, but , are labeled A0, A1 . F7 (see figure 1). There are a total of 48 GLBs in the ispLSI 1048/883 device , trw l ten tdls twh twl tsu5 th5 1. 2. 3. 4. 5. T-46-19-07 -50 MIN. MAX. 24 ns :ji s v'i; % 30.7 , C O N D U C T O R SSE D GGGEMfiti 223 LAT Lattice ispLSI 1048 883 Timing Model -
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1/064J 1X372 LS11048-50LG/883
Abstract: ' 1048 High-Density Programmable Logic Functional Block Diagram - tpd = 15 ns Propagation Delay - , |^ Ì% f j| y ia tfo rm s - PC: steMijfppPlatfc Î Description }LSl%nd pLSI 1048 are High-Density , to the pLSI 1048 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the ispLSI and pLSI 1048 devices is the Generic Logic Block (GL.B). , 1048 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be -
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0212-B0B-
Abstract: pLSÌ 1048 Lattice programmable Large Scale Integration High-Density Programmable Logic , Description The Lattice pLSI 1048 is a High-Density Programmable Logic Device which contains 288 Registers , Interconnectivity The basic unit of logic on the pLSI 1048 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 ,.F7, (see figure 1). There are a total of 48 GLBs in the pLSI 1048 device. Each GLB has , and the output drivers can source 4 mA or sink 8 mA. Clocks in the pLSI 1048 device are selected -
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ispLS11048

Abstract: 548-5N ispLSI 1048 In-System Programmable High Density PLD Functional Block Diagram Description The i|g L , Pool (GRP). The GRP [§Wides complete interconnectivity between all of these elements. The ispLSI 1048 , universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks. The GRP has as , tc o l th1 tsu2 tco2 th2 tr1 trw l ten tdis twh tw l tsu5 th5 1. 2. 3. 4. DESCRIPTION1 Data , Specifications ispLS11048 ispLSI 1048 Tim ing Model I/O Cell GRP Feedback GLB ORP I/O Ceil ^
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ispLS11048 548-5N 0212-80B 1048-70LG A-48-
Abstract: Lattice ispLSr 1048 in-system programmable Large Scale Integration High-Density Programmable , Interconnectivity The basic unit of logic on the ispLSI 1048 device is the Generic Logic Block (GLB). The GLBs , . Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048 device , driven from a special clock GLB (DO on the ispLSI 1048 device). The logic of this GLB allows the user to , universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks. 2 3/93. Rev -
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Abstract: isp L si 1048 I a t t ir p H I U w in-system programmable Large Scale Integration , input pins to control in-system pro­ gramming. The basic unit of logic on the ispLSI 1048 device is , compatible voltages and the output drivers can source 4 mA or sink 8 mA. Clocks in the ispLSI 1048 device , driven from a special clock GLB (DO on the ispLSI 1048 device). The logic of this GLB allows the user to , 1 12 Ext. Reset Pin to Output Delay - 17 - 17 - 22.7 ns trw l - 13 -
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Abstract: Specifications ispLSI and pLS11048 Lattice ispLSI and pLSI 1048 ;Semiconductor I , '" Optimized Global Routing Pool Provides Global Interconnectivity The ispLSI and pLSI 1048 are , truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1048 , unit of logic on the ispLSI and pLSI 1048 devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 . F7 (see figure 1). There are a total of 48 GLBs in the ispLSI and pLSI 1048 devices -
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LS11048-80LQ
Abstract: p L S r 1048 programmable Large Scale Integration Features J Functional Block Diagram , and Timing Simulation â'" PC and Workstation Platforms Description The Lattice pLSI 1048 is a , complete interconnectivity between all of these elements. The basic unit of logic on the pLSI 1048 device , igure 1. p L S 1 1048 rararara 01 90 8 9 66 rarav ora 87 66 85 64 ra ra ra ra 63 8 2 61 8 0 , GRP have been equalized to minimize timing skew and logic glitching. Clocks in the pLSI 1048 device -
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S8SSSE83
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