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Part Manufacturer Description Datasheet BUY
ISL73096RHVF Intersil Corporation RF POWER TRANSISTOR visit Intersil
ISL73096RHVX Intersil Corporation RF POWER TRANSISTOR visit Intersil
ISL73127RHVF Intersil Corporation RF POWER TRANSISTOR visit Intersil
ISL73128RHVF Intersil Corporation RF POWER TRANSISTOR visit Intersil
TIL604HR2 Texas Instruments Photo Transistor, PHOTO TRANSISTOR DETECTOR visit Texas Instruments
HS0-6254RH-Q Intersil Corporation 5 CHANNEL, UHF BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR, DIE-16 visit Intersil

transistor p02

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: current will normally continue to flow until the transistor turns on again. Most lowvoltage motor drive , the reset pin is held low. By using an inverting driver, the power transistor will be off in the , of 0xFF corresponds to a duty cycle of Rev. 1.1 3 AN191 â'˜F300 P0.2 +12V Q3 +12V , signal is applied to transistor Q1. To drive the motor in the reverse direction, Q3 is turned on and a , P0.7 â'˜F300 VDD Speed Reverse +12 V P0.2 +12 V DC Motor P0.0/CEX0 P0 Silicon Laboratories
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C8051F3

dc motor interface with 8051

Abstract: pwm using pca transistor turns on again. Most low-voltage motor drive circuits employ Schottky power rectifiers for the , an inverting driver, the power transistor will be off in the default state. If a non-inverting , AN191 `F300 +12V +12V Q3 Q4 P0.2 DC Motor Q1 Q2 P0.0/CEX0 P0.1/CEX0 P0 , direction, Q4 is turned on and a PWM signal is applied to transistor Q1. To drive the motor in the reverse , 5 AN191 VDD Speed P0.6/ADC0P VDD P0.7 Reverse +12 V `F300 P0.2 +12 V DC
Silicon Laboratories
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dc motor interface with 8051 pwm using pca brushless f330 optical quadrature encoder IR2104S PITTMAN encoder

transistor p02

Abstract: SKs TRANSISTOR transistor P02/SEG18, P03/SEG19 Note1 Note2 LCD power supply FR01 Ak OP0A instruction D T Q PU01 , (STCK) = f(XIN/8) 5 µA (Ta = 25 °C, VDD = 3.0 V, f(XCIN) = 32 kHz) 0.1 µA (Ta = 25 °C, output transistor , transistor Skip decision Register Y Decoder SZD instruction CLD instruction SD instruction RD instruction , transistor K32 Key-on wakeup input Edge detection circuit Skip decision Register Y Decoder SZD instruction CLD instruction SD instruction RD instruction R Q FR21 PU32 Pull-up transistor Note1 S D5/INT
Renesas Technology
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transistor p02 SKs TRANSISTOR LCD Power Supply SKs 22 TRANSISTOR sks 46 REJ03B0214-0001

cmos 4553

Abstract: ic 4553 P03 pull-up transistor OFF P03 pull-up transistor ON P02 pull-up transistor OFF P02 pull-up , 13 2 3 4 5 6 7 8 9 10 11 12 P23/SEG20 P00/SEG21 P01/SEG22 P02/SEG23 , CNVSS XOUT XIN VSS VDD C/CNTR D5/INT D4 D3 PLQP0048KB-A(48P6Q-A) P10/SEG20 P03/SEG19 P02 , SEG23 P02 SEG22 P01 SEG21 P00 0 1 0 1 0 1 0 1 At RESET11112 SEG28 P13 SEG27 P12 , P02 function switch bit C11 Port P01 function switch bit C10 Port P00 function switch bit
Renesas Technology
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4553H cmos 4553 ic 4553 transistor p13 4559 pin of ic 4553 w41 transistor SEG16 SEG24 SEG19 SEG25 SEG20

ilpi 129

Abstract: mosfet transistor p02 PROTECTION CIRCUITRY 2 PWR-82331 and PWR-82333 P-02/05-0 FIGURE 1. PWR-82331/82333 BLOCK DIAGRAM , nsec nsec nsec Data Device Corporation www.ddc-web.com 3 PWR-82331 and PWR-82333 P-02/05-0 , Conditions see note 6 +5 V, Io=30 A peak PWR-82331, Vcc=140 V PWR-82333, 270 V 400 150 each transistor jc Ts , -82333 can switch at 25 kHz. A flyback diode parallels each output transistor and controls the regenerative , . PWR-82331 and PWR-82333 P-02/05-0 10% (REFERENCE TABLE 2. ALSO.) FIGURE 2. INPUT/OUTPUT
Data Device
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ilpi 129 mosfet transistor p02 ilpi -115 PWR-8233X-XX0X 82333 TIP61C MIL-STD-883 MILSTD-883 P-02/05-0 1-800-DDC-5757

transistor AL P11

Abstract: FR20 transistor Pull-up transistor Off Port P02 pull-up transistor control bit at RAM back-up: state retained 0 , output functions. Ports P00 through P02 share their pins with Serial interface ports SIN, SOUT, and SCK , , whereas the pull-up transistor function can be switched On/Off also by setting register PU0. Further , "002" or "102" to registers J11 and J10 when using the pin as port P01. Note3: Port P02 shares its pin , P02. REJ05B0900-0100/Rev.1.00 2006.05 Page 2 of 18 4509 Group Input/Output Port 3.2
Renesas Technology
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transistor AL P11 FR20 transistor FR03 FR10 FR13 FR20 REJ05B0900-0100/R

transistor p02

Abstract: M57704M '¢ Junction temperature of the final stage transistor Tj3 = (Vcc x It3 - Po +P02) x Rth(J-3,+Tc = (12.5 x 2.0 , transistor Rth(j-e)i = 15°C/W (Typ.) b) Second stage transistor Rth(j-c)2 =6°C/W (Typ.) c) Final stage transistor Rth(i-C)3 =2.5°C/W (Typ.) (2) Junction temperature of incorporated transistors at standard , rating), P01(Note 1) = 1.5W, P02(2> = 6W, lT = 3.OA (lT1(3) = 0.25A, lT2(4) = 0.75A, lT3(5> = 2.0A) Note 1 : Output power of the first stage transistor Note 2: Output power of the second stage transistor
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OCR Scan
M57704M transistor 60 13w p02 transistor 430-450MH 430-450MHZ

w32 transistor

Abstract: w33 transistor transistor OFF P10, P11 pull-up transistor ON P02, P03 pull-up transistor OFF P02, P03 pull-up transistor , : state retained P03 pull-up transistor ON P02 pull-up transistor OFF P02 pull-up transistor ON P01 , PU00, PU01 are pull-up control register of P00 ~ P01 and P02 ~ P03, respectively P00 ~ P03 Port , P03/SEG19 P02/SEG18 P01/SEG17 P00/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 , register C1 C13 P03/SEG19 pin function switch bit C12 P02/SEG18 pin function switch bit
Renesas Technology
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w32 transistor w33 transistor transistor w32 transistor k33 34 transistor p31 ic 4559 M3455AG8FP M3455AG8-XXXFP M34559G6FP M34559G6-XXXFP M3455AGCFP M3455AGC-XXXFP
Abstract: incorporated transis­ tors at standard operation. Junction temperature o f the second stage transistor Tj'2 = (V cc x >T2 - P02 + Pol 1 > x Rt h (j-c )2 + T C â'¢ = (12.5 x 0.55 - 4.5 + 1) x 6 + T c = 20.3 + T c (°C) Junction temperature o f the final stage transistor T j 3 = (V c c X lT 3 - Po + p02) X R th (j-c )3 + T c = (12.5 x 2.5 - 14 + 4.5) x 2 + Tc (1) Thermal resistance between ju n ctio n and package o f incorporated transistors. a) First stage transistor 2. F*th(j-c)i -
OCR Scan
450MH M57716

transistor p02

Abstract: m57714 incorporated transistors. a) First stage transistor Rth(j-c)i =20°c/w (Type) b) Second stage transistor Rth(i-c)2 = 10°C/W (Type) c) Final stage transistor Rth,j-c>3 = 5°C/W (Typ.) (2) Junction , 7W, Vcc = 12.5V, Pin = 0.1W, r?T = 38% (minimum rating), P01 (Note 1) = 0.8W, P02(2> = 3.2W, lT = 1.47 A (lT1
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OCR Scan
m57714 Mitsubishi transistor rf final M57714 450-470MHZ 450-470MH

M57744

Abstract: stage transistor T j 2 = (V c c x ! t 2 - P02 + P o 1 ) x Rt h ( j- c l 2 + = ( 1 2 . 5 x 0 . 7 5 - 6 + 1.6) x 6 + T c T C = 2 9 .9 + Tc CC) Junction temperature o f the final stage transistor T , transistor ,h(° ' a) c) Final stage transistor Rth (;â'" )3 = 2.5°C/W (Typ.) c (2) Junction , 13W, V Cc = 12.5V, P|n = 0.4W, i?T = 35% (m ini­ mum rating), P0 i * Note = 1.6W, P02 *2* = 6W, l j , stage transistor Note 2: O u tp ut power o f the second stage transistor â'¢ â'¢ T j, = 119Â
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OCR Scan
M57744 889-915MH
Abstract: temperature of device Junction temperature of the second stage transistor Tj 2 = (Vcc x I t 2 - P02 + P0 1 , the final stage transistor T j3 = (Vcc x !t3 " P0 + P02 > x Rth(j-c)3 + Tc = (12.5 x 1.17 - 7 + 3.6 , and package of incorporated transistors. a) First stage transistor R ,h(j-cn =13°C/W (Tvp.) b) Second stage transistor R .h(j-c)2=9°C /W (Typ.) c) Final stage transistor R ,h(j-c)3= 4°C /W (Typ , first stage transistor Note 2: Output power of the second stage transistor Note 3: Circuit current of -
OCR Scan
M57749 903-905MHZ GG17212

1205 transistor

Abstract: Buzzer 4khz RES P11 X P12 S1 P13 S2 P00 32HZ P01 T3 P02 CUP2 P03 CUP1 , 25 26 27 28 29 30 31 32 33 Pad Name BAK VSS S4 S3 P10 P11 P12 P13 P00 P01 P02 , P03 SEG23 COM4 23 13 58 P02 SEG24 SEG13 12 SEG25 24 11 25 57 , Application Circuit (1) Ag battery used application (1/2 bias 1/4 duty) P00 P01 P02 P03 (2) Li battery used application (1/2 bias 1/4 duty) COM1 COM2 COM3 COM4 P00 P01 P02 P03 LCD GLASS
SANYO Electric
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LC5739 1205 transistor Buzzer 4khz QFP64 transistor A 1205 12 Y buzzer 1205 SEG17 SEG32 P10-13 P00-03

w32 transistor

Abstract: c30 C3J ) instruction Register A Ak Pull-up transistor P02/SEG18, P03/SEG19 Note1 Note2 LCD power supply FR01 , transistor is cut-off state) Function Notice: This is not a final specification. Some parametric limits are , specification. Some parametric limits are subject to change. Table 4 Pin P00 P01 P02 P03 P10 P11 P12 P13 P20 , Multifunction P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 D5 D6 D7 C SEG0 SEG1 SEG2 Pin , pull-up, keyon wakeup and output structure selection function - Port P0 P00/SEG16, P01/SEG17, P02
Renesas Technology
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c30 C3J marking c3j REJ03B0224-0100

1205 transistor

Abstract: buzzer 1205 SEG9 SEG8 SEG7 SEG6 SEG5 ALM1 VDD2 VDD1 BAK VSS S4 S3 Y P10 P11 P12 P13 P00 P01 P02 P03 , S4 S3 P10 P11 P12 P13 P00 P01 P02 P03 COM4 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 , P12 P13 P00 P01 P02 VDD2 VDD1 P03 NC S4 S3 5/18 LC5739 System , battery used application (1/2 bias 1/4 duty) P00 P01 P02 P03 P10 SEGOUT P11 P12 P13 KEY MATRIX S1 S2 S3 , GLASS 1/2 BIAS 1/4 DUTY (2) Li battery used application (1/2 bias 1/4 duty) P00 P01 P02 P03 P10
SANYO Electric
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transistor 1205 HO-1/18

CSA1316

Abstract: CSC3329 Continental Device India Limited An ISO/TS 16949, ISO 9001 and ISO 14001 Certified Company NPN SILICON PLANAR EPITAXIAL TRANSISTOR CSC3329 TO-92 Plastic Package Complementary CSA1316 ABSOLUTE , LEAD PARALLELISM PULL - OUT FORCE Flat Side of Transistor and Adhesive Tape Visible 2000 pcs , BOTTOM OF CLINCH AT TOP OF BODY AT TOP OF BODY %%P0.5 %%P0.2 +0.7 -0.5 %%P0.2 %%P0.5 23.25 11.0 4 %%P0.2 1.2 2.54 0.45 t1 0.3 - 0.6 +0.4, -0.1 1.45 3.0 0.22 6N NOTES 1
Continental Device India
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100MH C-120 CSC3329R 070102E

CSC2002

Abstract: Continental Device India Limited An ISO/TS 16949, ISO 9001 and ISO 14001 Certified Company NPN SILICON PLANAR EPITAXIAL TRANSISTOR CSC2002 TO-92 Plastic Package Designed for use in Driver Stage of High Voltage Audio Equipments. ABSOLUTE MAXIMUM RATINGS (Ta=25ºC unless specified otherwise , CLINCH HEIGHT LEAD PARALLELISM PULL - OUT FORCE Flat Side of Transistor and Adhesive Tape Visible , %%P0.5 %%P0.2 +0.7 -0.5 %%P0.2 %%P0.5 23.25 11.0 4 %%P0.2 1.2 2.54 0.45 t1 0.3 - 0.6
Continental Device India
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CSC2002R 090102E
Abstract: Continental Device India Limited An ISO/TS 16949, ISO 9001 and ISO 14001 Certified Company NPN SILICON PLANAR EPITAXIAL TRANSISTOR CSC2002 TO-92 Plastic Package Designed for use in Driver Stage of High Voltage Audio Equipments. ABSOLUTE MAXIMUM RATINGS (Ta=25ºC unless specified otherwise , H 3 2 1 MIN. A B F F Flat Side of Transistor and Adhesive Tape Visible 2000 pcs , %%P0.5 %%P0.2 +0.7 -0.5 %%P0.2 %%P0.5 23.25 11.0 4 %%P0.2 1.2 2.54 0.45 t1 0.3 - 0.6 Continental Device India
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Abstract: Continental Device India Limited An ISO/TS 16949, ISO 9001 and ISO 14001 Certified Company NPN SILICON PLANAR EPITAXIAL TRANSISTOR CSC3329 TO-92 Plastic Package Complementary CSA1316 ABSOLUTE , Flat Side of Transistor and Adhesive Tape Visible 2000 pcs./Ammo Pack SPECIFICATION ITEM 2 , MEASURED AT BOTTOM OF CLINCH AT TOP OF BODY AT TOP OF BODY %%P0.5 %%P0.2 +0.7 -0.5 %%P0.2 %%P0.5 23.25 11.0 4 %%P0.2 1.2 2.54 0.45 t1 0.3 - 0.6 +0.4, -0.1 1.45 3.0 0.22 6N Continental Device India
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CSC2002

Abstract: Continental Device India Limited An ISO/TS16949 and ISO 9001 Certified Company NPN SILICON PLANAR EPITAXIAL TRANSISTOR CSC2002 TO-92 Plastic Package Designed for use in Driver Stage of High Voltage Audio Equipments. ABSOLUTE MAXIMUM RATINGS (Ta=25ºC unless specified otherwise , CLINCH HEIGHT LEAD PARALLELISM PULL - OUT FORCE Flat Side of Transistor and Adhesive Tape Visible , %%P0.5 %%P0.2 +0.7 -0.5 %%P0.2 %%P0.5 23.25 11.0 4 %%P0.2 1.2 2.54 0.45 t1 0.3 - 0.6
Continental Device India
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