NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: applied at the input, the upper p-channel transistor (P1) is off and the lower n-channel transistor (N1 , ) through the transistor P1. When changing output states from high to low, transistor P1 begins to turn off , V+ P1 VOUT VIN N1 A) Inverter Logic Symbol B) Inverter Transistor Implementation , N-channel transistor (N1) is off while the upper P-channel transistor (P1) is on. There is a back flow of current from the high supply to the low supply through the resistor R and the transistor P1. This current ... | Original |
13 pages, |
TS5A6542 TS5A3159A TS5A26542 TS5A12301E TS3A44159 SN74LVC1T45 SCDA011 SCDA011 abstract |
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| Abstract: /hold clock pulse width T4 REFOUT (Pin 14) can drive up the base current of an external transistor (P1 , to the emitter of the external transistor. (The external transistor must have enough gain and current ... | OCR Scan |
6 pages, |
CXA1496Q CXA1496AQ QFP032-P-0707-A CXA1694Q CXA1693Q QFP-32P-L01 CXA1693Q abstract |
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| Abstract: Yes Yes FB Build-in Transistor External Transistor Build-in Transistor Build-in Transistor P1/10 Rev. B, July 2005 ML65 ML65A ML65A Pin Configuration Package Pin Number SOT23-3 , circuit, a Lx switch driver transistor, a reference voltage unit, an error amplifier for voltage , with low noise and ultra low supply current. Switching Transistor CE Function VDD Pin FB Pin Features Build-in Transistor No No No Lx External Transistor No No ... | Original |
10 pages, |
vlx60 sot89-3 sot89 ML65 8 pin 4v power supply converter 10uF CAPACITOR 35V tantalum so sot89 icel p3 sot89-5 datasheet abstract |
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| Abstract: transistor P1 is ON. The intermediate point between the N1 and N2 is actively pulled to VCC by P1. When , pass transistor. In addition to this NMOS transistor, there exists a parasitic NPN bipolar transistor , transistor is at 0V and the switch is OPEN or OFF. An undershoot condition actually creates two phenomena , source node voltage of the NMOS transistor becomes lower than that of the gate. The NMOS threshold , VBE on the parasitic NPN bipolar transistor will occur. The NPN will conduct current from the drain ... | Original |
4 pages, |
nmos transistor FSTU6800 Fairchild Bipolar Transistor High Beta AN-5008 IN 5008 DIODE AN-5008 abstract |
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| Abstract: transistor P1 is ON. The intermediate point between the N1 and N2 is actively pulled to VCC by P1. When , transistor. In addition to this NMOS transistor, there exists a parasitic NPN bipolar transistor (with a beta , from achieving a 650mV VTN and turning ON. When OE is HIGH, the gate of the NMOS transistor is at , voltage of the NMOS transistor becomes lower than that of the gate. The NMOS threshold voltage, VTN, for , VBE on the parasitic NPN bipolar transistor will occur. The NPN will conduct current from the drain ... | Original |
4 pages, |
FSTU6800 AN-5008 AN-5008 abstract |
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| Abstract: Build-in Transistor Build-in Transistor P1/10 Rev. B, June 2006 Marking: SOT23: ML63A ML63A series , oscillator, a PFM control circuit, a Lx switch driver transistor, a reference voltage unit, an error , TO-92 SOT23-5 SOT89-5 SOT23-5 SOT89-5 SOT23-5 SOT89-5 SOT23-5 SOT89-5 Switching Transistor CE Function VDD Pin FB Pin Features Build-in Transistor No No No Lx External Transistor No No No Ext Yes No No Lx+CE Yes No No Ext+CE ... | Original |
11 pages, |
marking code SS SOT23 marking code lx diode marking code of sot89 transistor ML63S ML63SA33 so sot89 sot23 transistor chip code sot23 Transistor marking p2 marking 93, sot-89 MARKING 93 SOT89 sot89-5 marking code CE SOT23-5 ML63S abstract |
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| Abstract: BIAS 13 VLD PHOTODIODE R2 10 R1 15 C7 0.01uF Optional Shutdown Transistor P1 , VCC VLD V7 V5 R3 V4 V2 V4 V2 V1 V5 P1 V3 V5 Q1 V4 Thermal ... | Original |
7 pages, |
SLT2170-LN OC48 MAX3737 MAX3735A MAX3735 MAX3656 HFRD-04 HFDN-26 HFAN-09 HFDN-26 abstract |
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| Abstract: BIAS 13 VLD PHOTODIODE R2 10 R1 15 C7 0.01uF Optional Shutdown Transistor P1 , VCC VLD V7 V5 R3 V4 V2 V4 V2 V1 V5 P1 V3 V5 Q1 V4 Thermal ... | Original |
7 pages, |
vlf ferrite SLT2170-LN MAX3850 MAX3737 MAX3735A MAX3735 MAX3656 HFAN-02 HFDN-26 HFDN-26 abstract |
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| Abstract: transistor P1 (§). When the voltage on the capacitor reaches Vref 2, the reset latch will clear, and will , to Vpp) a valid trigger is recognized, which turns on comparator C1 and N-channel transistor N1 (j). At the same time the output latch is set. With transistor N1 on, the capacitor Cx rapidly discharges toward Vgs until Vrefi is reached. At this point the output of comparator C1 changes state and transistor , transistor N1 off, the capacitor Cx begins to charge through the timing resistor, Rx, toward Vqd-When the ... | OCR Scan |
8 pages, |
4541B CD4528B MC14528B MC14538B MC14XXXBCL MC14XXXBDW 74hc4538a BA rx transistor 4538B CD4528 CD4098 mc4538a mc145388 mc4538 MC14538B abstract |
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| Abstract: in the state of the latch bit, transistor P1 will be turned on for two oscillator periods. This , P1 is turned on, it will in turn activate P3. The gate and P3 form a latch when P1 is turned off so , , AND 3) Figure 12� VCC DELAY = 2Tclk P1 VCC P2 PORT PIN Q FROM PORT LATCH VCC P3 ... | Original |
9 pages, |
DS5002FP DS5001FP DS5001/2FP DS5001/2FP abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| RECEIVE_INTERRUPT_ENABLE 0x01 // OUTPUT CONTROL register #define OUTPUT_CONTROL_TRANSISTOR_P1 0x80 #define OUTPUT_CONTROL_TRANSISTOR_N1 0x40 #define OUTPUT_CONTROL_POLARITY_1 0x20 #define OUTPUT_CONTROL_TRANSISTOR_P0 0x10 #define OUTPUT_CONTROL_TRANSISTOR_N0 0x08 #define OUTPUT_CONTROL_POLARITY_0 0x04 OUTPUT_CONTROL_SETUP (OUTPUT_CONTROL_TRANSISTOR_P0 | OUTPUT_CONTROL_TRANSISTOR_N0 | OUTPUT_CONTROL_MODE_1 tar:gwww.datasheetarchive.com/files/digital-logic/drivers/can/pci/peak/drivers/linux/peak-linux-driver.3.28.tar.gz!/peak-linux-driver.3.28.tar!/peak-linux-driver-3.28/driver/src/pcan_sja1000.c |
Digital Logic | 02/03/2006 | 255.3 Kb | GZ | peak-linux-driver.3.28.tar.gz |
| RECEIVE_INTERRUPT_ENABLE 0x01 // OUTPUT CONTROL register #define OUTPUT_CONTROL_TRANSISTOR_P1 0x80 #define OUTPUT_CONTROL_TRANSISTOR_N1 0x40 #define OUTPUT_CONTROL_POLARITY_1 0x20 #define OUTPUT_CONTROL_TRANSISTOR_P0 0x10 #define OUTPUT_CONTROL_TRANSISTOR_N0 0x08 #define OUTPUT_CONTROL_POLARITY_0 0x04 OUTPUT_CONTROL_SETUP (OUTPUT_CONTROL_TRANSISTOR_P0 | OUTPUT_CONTROL_TRANSISTOR_N0 | OUTPUT_CONTROL_MODE_1 tar:gwww.datasheetarchive.com/files/digital-logic/drivers/xp-w2k/can/mpc21b/develop/linux/peak-linux-driver.3.28.tar.gz!/peak-linux-driver.3.28.tar!/peak-linux-driver-3.28/driver/src/pcan_sja1000.c |
Digital Logic | 02/03/2006 | 255.3 Kb | GZ | peak-linux-driver.3.28.tar.gz |
| 1 P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 P1.5 / AN5 / T2EX P1.4 / AN4 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CC0 VSS VAGND P0.0 / AD0 P0.1 / AD1 P0 P1.0-P1.7 71-78 71 72 73 74 75 76 77 78 I/O Port 1 is an 8-bit quasi-bidirectional port with assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 www.datasheetarchive.com/files/infineon/mc_data/dave/products/c505l.dip!/c505l/documents/m505l.pdf |
Infineon | 06/06/2000 | 3932.36 Kb | DIP | c505l.dip |
| 3 PSE N P2.7 / A1 5 AL E P2.4 / A12 P2.3 / A11 XTAL2 XTAL1 P4.0 / TXD C P1.7 / AN7 / T 2 P3.2 / INT 0 P3.3 / INT 1 RESE T P1.6 / AN6 / CLKOU T P1.5 / AN5 / T2E X 111 6 34 39 44 16 21 22 MCP03285 MCP03285 MCP03285 MCP03285 P2 P3.5 / T 1 P3.1 / Tx D P1.4 / AN4 V V AREF AGND 2 3 4 5 7 8 109 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CCO P1.3 / AN3 / INT6 / CC3 P1.2 / AN2 / INT5 Number I/O*) Function P1.0-P1.7 40-44,1-3 40 41 42 43 44 1 2 3 I/O Port 1 is an 8-bit quasi www.datasheetarchive.com/files/infineon/mc_data/dave/products/c505a.dip!/c505a/documents/m505c.pdf |
Infineon | 01/02/2000 | 4539.55 Kb | DIP | c505a.dip |
| 3 PSE N P2.7 / A1 5 AL E P2.4 / A12 P2.3 / A11 XTAL2 XTAL1 P4.0 / TXD C P1.7 / AN7 / T 2 P3.2 / INT 0 P3.3 / INT 1 RESE T P1.6 / AN6 / CLKOU T P1.5 / AN5 / T2E X 111 6 34 39 44 16 21 22 MCP03285 MCP03285 MCP03285 MCP03285 P2 P3.5 / T 1 P3.1 / Tx D P1.4 / AN4 V V AREF AGND 2 3 4 5 7 8 109 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CCO P1.3 / AN3 / INT6 / CC3 P1.2 / AN2 / INT5 Number I/O*) Function P1.0-P1.7 40-44,1-3 40 41 42 43 44 1 2 3 I/O Port 1 is an 8-bit quasi www.datasheetarchive.com/files/infineon/mc_data/dave/products/c505ca.dip!/c505ca/documents/m505c.pdf |
Infineon | 01/02/2000 | 4716.25 Kb | DIP | c505ca.dip |
| 3 PSE N P2.7 / A1 5 AL E P2.4 / A12 P2.3 / A11 XTAL2 XTAL1 P4.0 / TXD C P1.7 / AN7 / T 2 P3.2 / INT 0 P3.3 / INT 1 RESE T P1.6 / AN6 / CLKOU T P1.5 / AN5 / T2E X 111 6 34 39 44 16 21 22 MCP03285 MCP03285 MCP03285 MCP03285 P2 P3.5 / T 1 P3.1 / Tx D P1.4 / AN4 V V AREF AGND 2 3 4 5 7 8 109 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CCO P1.3 / AN3 / INT6 / CC3 P1.2 / AN2 / INT5 Number I/O*) Function P1.0-P1.7 40-44,1-3 40 41 42 43 44 1 2 3 I/O Port 1 is an 8-bit quasi www.datasheetarchive.com/files/infineon/mc_data/dave/products/c505.dip!/c505/documents/m505c.pdf |
Infineon | 01/02/2000 | 3833.75 Kb | DIP | c505.dip |
| 3 PSE N P2.7 / A1 5 AL E P2.4 / A12 P2.3 / A11 XTAL2 XTAL1 P4.0 / TXD C P1.7 / AN7 / T 2 P3.2 / INT 0 P3.3 / INT 1 RESE T P1.6 / AN6 / CLKOU T P1.5 / AN5 / T2E X 111 6 34 39 44 16 21 22 MCP03285 MCP03285 MCP03285 MCP03285 P2 P3.5 / T 1 P3.1 / Tx D P1.4 / AN4 V V AREF AGND 2 3 4 5 7 8 109 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CCO P1.3 / AN3 / INT6 / CC3 P1.2 / AN2 / INT5 Number I/O*) Function P1.0-P1.7 40-44,1-3 40 41 42 43 44 1 2 3 I/O Port 1 is an 8-bit quasi www.datasheetarchive.com/files/infineon/mc_data/dave/products/c505c.dip!/c505c/documents/m505c.pdf |
Infineon | 01/02/2000 | 4108.68 Kb | DIP | c505c.dip |
| BUX86P BUX86P BUX86P BUX86P_87P_1 Product information page BUX86P BUX86P BUX86P BUX86P; BUX87P BUX87P BUX87P BUX87P; Silicon Diffused Power Transistor General info High voltage, high speed glass passivated npn power transistors in a SOT82 envelope Diffused Power Transistor 1-11-1995 Product Specification 6.0 41.4 Products Management Selection Guide 2005 (2005-01-03) Letter Symbols - Transistors General (1999-05-01) WWW www.datasheetarchive.com/files/philips/pip/bux86p_87p_1-v2.html |
Philips | 15/06/2005 | 5.22 Kb | HTML | bux86p_87p_1-v2.html |
| BUX86P BUX86P BUX86P BUX86P_87P_1 BUX86P BUX86P BUX86P BUX86P; BUX87P BUX87P BUX87P BUX87P Silicon Diffused Power Transistor High voltage, high speed glass passivated npn power transistors in a SOT82 envelope intended for use in - Transistors General (01-May-99) BUX86P BUX86P BUX86P BUX86P; BUX87P BUX87P BUX87P BUX87P Silicon Diffused Power Transistor 01-Nov-95 Product Specification www.datasheetarchive.com/files/philips/pip/bux86p_87p_1-v1.html |
Philips | 14/02/2002 | 7.3 Kb | HTML | bux86p_87p_1-v1.html |
| BUX86P BUX86P BUX86P BUX86P_87P_1 Product information page BUX86P BUX86P BUX86P BUX86P; BUX87P BUX87P BUX87P BUX87P; Silicon Diffused Power Transistor General info High voltage, high speed glass passivated npn power transistors in a SOT82 envelope intended for use in converters, inverters, switching regulators, motor control systems and switching applications. Parametrics TYPENUMBER Category I C (DC) (A Diffused Power Transistor 01-nov-95 Product Specification 6 41.4 Products and www.datasheetarchive.com/files/philips/pip/bux86p_87p_1.html |
Philips | 23/04/2003 | 3.05 Kb | HTML | bux86p_87p_1.html |