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TLC2272AMP Texas Instruments IC DUAL OP-AMP, 1500 uV OFFSET-MAX, 2.25 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier ri Buy
TLC2272QPWRG4Q1 Texas Instruments Automotive Catalog Advanced LinCMOS(TM) Rail-to-Rail Operational Amplifiers 8-TSSOP -40 to 125 ri Buy
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tcl 2272

Catalog Datasheet Results Type PDF Document Tags
Abstract: tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH -40 Min , ns ns ns ns Note Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 CK, CK CS 1 2 3 , defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for , -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 -32.8 -25.32 -36.48 -27.64 -40.08 ... Original
datasheet

22 pages,
458.26 Kb

tcl 2272 gddr5 samsung gddr5 x16 4464 dram K4D263238KVC50 K4D263238KVC40 K4D263238K GDDR GDDR2 GDDR3 GDDR4 GDDR5 K4D263238K-VC50 GDDR5 application note samsung samsung GDDR5 K4D263238K-VC40 K4D263238K abstract
datasheet frame
Abstract: tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH -40 Min , ns ns ns ns Note Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 CK, CK CS 1 2 3 , defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for , 0.96 -2.68 -2.92 -7.4 -6.56 -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 -32.8 ... Original
datasheet

20 pages,
409.97 Kb

K4D263238K K4D263238K abstract
datasheet frame
Abstract: adsp MATCH DIRTY VALID Figure 1. Cache Using Four CY7C1331s 2-272 BiflTbbe 0014^71 b6T This , lCYC Clock Cycle Time 15 15 20 ns tCH Clock HIGH 5 6 8 ns tCL Clock LOW 5 6 8 ns tAS , Waveforms Single Read!11! ADVANCED INFORMATION CY7C1331 CY7C1331 CY7C1332 CY7C1332 CLK - 'CH ‚-† -tcl- ^yyyxxyyi - , "tAS" XX>K 'ads - xiXXXX xxxxx DATA OUT √-E -tcSH - -tCL" ¬ŅEXXZZE lyxxxxxxx^ -tAH- ... OCR Scan
datasheet

12 pages,
425.7 Kb

zl9j CY7C1332 CY7C1331 tcl 2272 CY7C1331 abstract
datasheet frame
Abstract: time to DQS DQ and DM hold time to DQS tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS , tCK ns ns ns ns - ns - ns Simplified Timing @ BL=2, CL=3 tCH 0 1 tCL , period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency , -2.68 -2.92 -7.4 -6.56 -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 ... Original
datasheet

20 pages,
411.46 Kb

tcl 2272 K4D263238K-VC50 K4D263238K-VC40 K4D263238K K4D263238K abstract
datasheet frame
Abstract: tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.55 +0.55 , VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock , limits for tCL and tCH).For example, tCL and tCH are = 50% of the period, less the half period , cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration , 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 24.24 34.20 ... Original
datasheet

26 pages,
452.64 Kb

k4h641638n-lc DDR400 DDR333 DDR266 ap 6928 7472 truth table tsop 4036 K4H641638 K4H641638N K4H641638N abstract
datasheet frame
Abstract: AT91-ISP the application starts. 2.2.7.2 Initialization As the Debug Unit is part of the System ... Original
datasheet

24 pages,
294.95 Kb

project with at91sam7x256 AT91SAM at91sam7s ek AT91SAM7S-EK AT91SAM7S256 AT91SAM7SE-EK AT91SAM7SE512 AT91SAM7X-EK AT91SAM7X256 AT91SAM9260 Getting Started with the AT91SAM9261 object counter with ldr ARCHITECTURE OF AT91SAM9263 AT91SAM abstract
datasheet frame
Abstract: CK low level width tCL 0.45 0.55 0.45 0.55 tCK tDQSCK -0.6 0.6 -0.7 , is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance , 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 ... Original
datasheet

18 pages,
383.92 Kb

K4D261638 ap 6928 cs 2648 DIN 3968 K4D261638K-LC50 k4d261638k BT 4840 amp K4D261638K-LC40 K4D261638K K4D261638K abstract
datasheet frame
Abstract: 91H90 ) 1.61 √- (fCLOCK/20 MHz) 2.272 √- (fCLOCK/20 MHz) 2.90 √- (20 MHz/fCLOCK) 0 5.05 √- (20 MHz/fCLOCK) 0.0005 , without notice. S1 ANALOG INPUT S2 tC tCL tCH INPUT CLOCK tDI DATA OUTPUT tDS tH DAV , , CL = 20 pF, TMIN to TMAX unless otherwise noted) Symbol tC tDAV tDI tDS tCH tCL tH tRES¬≠DAV tCLK¬≠DAV ... Original
datasheet

9 pages,
109.92 Kb

AD9260 AD9260 abstract
datasheet frame
Abstract: time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST , clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 - , ) Minimum 0 -1.08 -4.212 -2.272 -10.152 -12.96 -15.48 -17.856 -20.052 -21.996 -23.832 -25.308 -26.64 -27.684 ... Original
datasheet

19 pages,
339.4 Kb

Samsung 9724 K4D261638I-LC50 28548 K4D261638I K4D261638I abstract
datasheet frame
Abstract: Clock half period Data output hold time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC tDQSQ tRPRE , any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent , 9.04 10.68 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 ... Original
datasheet

18 pages,
382.38 Kb

K4D261638K-LC50 K4D261638K-LC40 k4d261638k cs 2648 BT 4840 amp K4D261638K K4D261638K abstract
datasheet frame

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Hitachi 22/10/2000 92325.55 Kb ZIP gn99r1p1.zip
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Answers Database Index Number of Solutions: 4710 Xilinx Answer #100 : Xilinx Libraries: All Xilinx/Viewlogic components have a LEVEL= attribute to decrease runtime Xilinx Answer #101 : Viewsim: About ? Nodes in Timing Simulations Xilinx Answer #102 : FPGA Configuration: DONE Doesn't Go High; General XC4000 XC4000 XC4000 XC4000 D
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Xilinx 29/02/2000 662.64 Kb HTM rp00254.htm