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ISL32272EFVZ-T Intersil Corporation Quad, ±16.5kV ESD Protected, 3.0V to 5.5V, Low Power, RS-422 Transmitters; SOIC16, TSSOP16; Temp Range: -40° to 125°C visit Intersil Buy
ISL32272EIBZ-T Intersil Corporation IC,LINE DRIVER,4 DRIVER,BICMOS,SOP,16PIN,PLASTIC visit Intersil
ISL32272EIBZ Intersil Corporation QUAD LINE DRIVER, PDSO16, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16 visit Intersil
ISL32272EIVZ Intersil Corporation QUAD LINE DRIVER, PDSO16, ROHS COMPLIANT, PLASTIC, TSSOP-16 visit Intersil
ISL32272EIVZ-T Intersil Corporation IC,LINE DRIVER,4 DRIVER,BICMOS,TSSOP,16PIN,PLASTIC visit Intersil
ISL32272EFVZ Intersil Corporation Quad, ±16.5kV ESD Protected, 3.0V to 5.5V, Low Power, RS-422 Transmitters; SOIC16, TSSOP16; Temp Range: -40° to 125°C visit Intersil Buy

tcl 2272

Catalog Datasheet MFG & Type PDF Document Tags

tcl 2272

Abstract: zl9j CY7C1331s 2-272 BiflTbbe 0014^71 b6T This Material Copyrighted By Its Respective Manufacturer CYPRESS , . Min. Max. lCYC Clock Cycle Time 15 15 20 ns tCH Clock HIGH 5 6 8 ns tCL Clock LOW 5 6 8 , 'CH â  -tcl- ^yyyxxyyi - tcss - -tas" Ã"D5PH2] or ADSC WH, WD131 1ads - XXXXXXXf - , ADDRESS SD5P WH, WD131 "tAS" XX>K 'ads - xiXXXX xxxxx DATA OUT ÃE -tcSH - -tCL" ¿EXXZZE
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OCR Scan
CY7C1331 CY7C1332 tcl 2272 zl9j 80486 microprocessor block diagram and pin diagram 66-MH

tcl 2272

Abstract: 91H90 MHz) 3.75 × (fCLOCK/20 MHz) 16.25 × (fCLOCK/20 MHz) 1.61 × (fCLOCK/20 MHz) 2.272 × (fCLOCK/20 MHz , load of I OL = 1.6 mA. Specifications subject to change without notice. S1 ANALOG INPUT S2 tC tCL , noted) Symbol tC tDAV tDI tDS tCH tCL tH tRES­DAV tCLK­DAV tOD tOE AD9260 50 tC × Mode 40% tDAV tDAV
Analog Devices
Original
91H90 12-BIT 16-BIT BIT16 AD9260AS AD9260EB

samsung GDDR5

Abstract: K4D263238K-VC40 tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH -40 Min , ns ns ns ns Note Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 CK, CK CS 1 2 3 , defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for , -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 -32.8 -25.32 -36.48 -27.64 -40.08
Samsung Electronics
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K4D263238K 170FBGA samsung GDDR5 K4D263238K-VC40 GDDR5 application note samsung K4D263238K-VC50 GDDR GDDR2 GDDR3 GDDR4 GDDR5 84FBGA 100FBGA 96FBGA 136FBGA

K4D263238K

Abstract: K4D263238K-VC40 hold time to DQS tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST , ns - ns Simplified Timing @ BL=2, CL=3 tCH 0 1 tCL tCK 2 3 4 6 5 , for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent , -2.68 -2.92 -7.4 -6.56 -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72
Samsung Electronics
Original
Abstract: to DQS Clock half period Data output hold time from DQS Symbol tCK tCH tCL tDQSCK tAC tDQSQ tRPRE , Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 CK, CK CS 1 2 3 4 5 6 7 8 , clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing , -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 -32.8 -25.32 -36.48 -27.64 -40.08 Samsung Electronics
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K4D261638K-LC40

Abstract: BT 4840 amp 0.45 0.55 tCK CK low level width tCL 0.45 0.55 0.45 0.55 tCK tDQSCK , is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance , 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64
Samsung Electronics
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K4D261638K-LC40 BT 4840 amp k4d261638k K4D261638K-LC50 3620* IBIS DIN 3968 K4D261638K 65TYP 20MAX 25TYP

28548

Abstract: Data output hold time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS , defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for , ) Minimum 0 -1.08 -4.212 -2.272 -10.152 -12.96 -15.48 -17.856 -20.052 -21.996 -23.832 -25.308 -26.64 -27.684
Samsung Electronics
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28548 K4D261638I

K4D261638F-LC50

Abstract: Samsung 9724 to DQS Clock half period Data output hold time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC , for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent , Pulldown Current (mA) Pullup Current (mA) Minimum 0 -1.08 -4.212 -2.272 -10.152 -12.96 -15.48 -17.856
Samsung Electronics
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K4D261638F-LC50 Samsung 9724 K4D261638I-LC50

BT 4840 amp

Abstract: 3620* IBIS to DQS Clock half period Data output hold time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC , for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent , 9.04 10.68 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64
Samsung Electronics
Original
cs 2648
Abstract: processor using four CY7C1331 cache RAMs. 2-272 0 0 1 4 ^ 7 1 01 00 11 10 The CY7C1332 , 5 6 8 ns 5 6 15 tCL Clock LOW 8 ns tAS Address Set-Up Before CLK , ) < Single Write Timing: Write Initiated by ADSP *CH - -tCL â  X CLK -*css - -Us- C5 -
OCR Scan
CY7C1332-

28548

Abstract: to DQS Clock half period Data output hold time from DQS CL=2 CL=3 Symbol tCK tCK tCH tCL tDQSCK tAC , for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent , Current (mA) Pullup Current (mA) Minimum 0 -1.08 -4.212 -2.272 -10.152 -12.96 -15.48 -17.856 -20.052
Samsung Electronics
Original

makefile for at91sam9260

Abstract: PIT DEMO KIT the application starts. 2.2.7.2 Initialization As the Debug Unit is part of the System
Atmel
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AT91SAM makefile for at91sam9260 PIT DEMO KIT AT91SAM7X256 example project 3 pins LDR at91sam7s ek

K4H641638N

Abstract: K4H641638 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL , VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock , limits for tCL and tCH).For example, tCL and tCH are = 50% of the period, less the half period , cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration , 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 24.24 34.20
Samsung Electronics
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K4H641638N K4H641638 tsop 4036 k4h641638n-lc ap 6928 7472 truth table

EP600

Abstract: EP600 eprom 55 + 25 ns tCH CLK High Time 17.5 21.5 ns tCL CLK Low Time 17.5 21.5 ns ASYNCHRONOUS , 2-272 intel SWITCHING WAVEFORMS (Continued) ASYNCHRONOUS CLOCK MODE ASYN. CLOCK INPUT X )( X X
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OCR Scan
EP600 N5C060 5C060-45 EP600 eprom 5c060 P5C060-45 16-MACROCELL EP6003 5C060

Multiplexers

Abstract: 5C060-55 Inputâ'"Internal Path 45 55 + 25 ns tch CLK High Time 17.5 21.5 ns tCL CLK Low Time 17.5 21.5 ns , -STATE VALID OUTPUT ASYNCHRONOUSLY CLEAR OUTPUT 290194-15 SYNCHRONOUS CLOCK MODE 2-272 Powered by ICminer.com
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OCR Scan
Multiplexers 5C060-55 EP600 programming intel PLD P5C060-55

Hitachi DSA0087

Abstract: 2272 t4 tCH tCL tHP tCK Max. Min. Max. ­0.7 +0.7 ­0.6 +0.6 ns 2)3)4)5) ­0.6 , 0.45 0.55 tCK tCK ns 2)3)4)5) min. (tCL, tCH) 6 12 min. (tCL, tCH) 5 12 ns , 1st DQS latching tDQSS 1) Max. tCL tHP tCK3 tCK2.5 tCK2 tDH tDS tIPW Unit Note , width (each input) tCK 2)3)4)5) min. (tCL, tCH) min. (tCL, tCH) ns 2)3)4)5) 7 12 7 , ) 1960 2360 2205 2655 2272 2736 2556 3078 mA 3) 24 47 27 53 48
Elpida Memory
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HM5425161B HM5425801B HM5425401B Hitachi DSA0087 2272 t4 HM5425161BTT-10 HM5425161BTT-75A HM5425161BTT-75B E0086H10 ADE-203-1077C

PC3200U-30330-A0

Abstract: tcl 2272 3 - 3.S - ns 6 tcl CLK low pulse width 3 - 3.5 - ns 6 tAS Add setup time 2 - 3 - ns 6 cah Add , A, 0.05 A2 0.95 1.05 b 0.25 0.45 c 0.10 0.25 d 22.22 22.72 e 10.06 10.26 "e 0.80 (typical) E
Infineon Technologies
Original
PC3200U-30330-A0 PC3200U-30330-B0 HYS72D64300HU-5-B PC2700U-25330-a0 DDR400B PC3200 L-DIM-184-30 HYS72D64300HU- L-DIM-184-33 HYS64D128320HU- L-DIM-184-31 HYS72D128320HU-

HM5425161B

Abstract: HM5425161BTT-10 MHz) dB max dB min MHz min MHz max MHz min MHz max 1.61 × (fCLOCK/20 MHz) 2.272 à , . S2 S1 tC ANALOG INPUT tCL tCH INPUT CLOCK tDI tDS DATA OUTPUT tOE tH , tDI tDS tCH tCL tH tRESâ'"DAV tCLKâ'"DAV tOD tOE Rev. C | Page 10 of 44 AD9260 50 tC
Hitachi Semiconductor
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HM5425801BTT-75A HM5425801BTT-75B Hitachi DSA0027990. Hitachi DSA00279 ADE-203-1077 D-85622
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