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stm-16 Payload Processor

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: PM5369 PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s Released Product Brief , , multi-channel payload processor for aligning · Supports independent transport, high-order payload and · · , Tributary Unit Payload Processor for 9953 Mbit/s Applications Package · Implemented in a 1.2 V core , (VTs) or SDH tributary units (TUs) in an STS-192/STM-64 STS-192/STM-64 or STS-48/STM-16 data stream Supports High Order (STS/AU) pointer processing, payload processing, and path termination/monitoring Supports Low ... PMC-Sierra
Original
datasheet

2 pages,
192.05 Kb

TUG-3 STM16 PMC-2020003 PM5370 PM5369 PM5329 PM5324 extended sonet serial interface ADM processor TEXT
datasheet frame
Abstract: PM5369 PM5369 TUPP 9953 Preliminary Tributary Unit Payload Processor for 9953 Mbit/s FEATURES · Configurable, multi-channel payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-192/STM-64 STS-192/STM-64 or STS-48/STM-16 data stream. · Supports High Order (STS/AU) pointer processing, payload processing, and path termination/monitoring. · Supports Low Order (VT/TU) pointer , Tributary Unit Payload Processor for 9953 Mbit/s APPLICATIONS · Power when full bandwidth is used (OC ... PMC-Sierra
Original
datasheet

2 pages,
53.57 Kb

PM5377 PM5370 PM5369 PM5326 extended sonet serial interface SDH ADM PM5324 TEXT
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Abstract: PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 PM5363 TUPP+622 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR , SHEET PMC-981421 PMC-981421 ISSUE 3 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES , TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES CONTENTS 1 2 3 4 5 FEATURES , . 110 TRIBUTARY PAYLOAD PROCESSOR (VTPP) .111 10.3.1 CLOCK GENERATOR , PRELIMINARY PM5363 PM5363 TUPP+622 DATA SHEET PMC-981421 PMC-981421 ISSUE 3 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR ... PMC-Sierra
Original
datasheet

456 pages,
2940.42 Kb

TUPP-622 GR-1400 PM5363 PMC-981421 TEXT
datasheet frame
Abstract: PM5369 PM5369 TUPP 9953 Released Tributary Unit Payload Processor for 9953 Mbit/s FEATURES · Configurable, multi-channel payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-192/STM-64 STS-192/STM-64 or STS-48/STM-16 data stream. · Supports High Order (STS/AU) pointer processing, payload processing, and path termination/monitoring. · Supports Low Order (VT/TU) pointer , Tributary Unit Payload Processor for 9953 Mbit/s APPLICATIONS · Power when full bandwidth is used (OC ... PMC-Sierra
Original
datasheet

2 pages,
54.53 Kb

PMC202 PMC-2020003 PM5377 PM5370 PM5369 TUPP 9953 PM5369 PM5326 PM5324 TEXT
datasheet frame
Abstract: -4-64c payload or a STS-192/AU-4-64 STS-192/AU-4-64 payload, the S19223 S19223 can demultiplex the signal to 4 STS-48/STM-16 , MEKONGAC Product Brief SONET/SDH STS-192/STM-64 STS-192/STM-64 MUX/DEMUX with Pointer Processor Part , -48/STM-16s. · Multiplexes 4 STS-48/STM-16 tributaries into an STS-192/ STS-192/ STM-64 STM-64 or bypass for STS-192/STM-64-to-STS-192/STM-64 connections. · Pointer Processors support standard SONET/SDH payload types as well as STS-6c/9c/24c and AU-4-2c/3c/8c payload types. · Selector for choosing high or ... Applied Micro Circuits
Original
datasheet

3 pages,
88.29 Kb

xcvr FR192 GR-253 S19223CBI11 s19235 STM-16 STS-192 64 to 4 Mux STM-64 6 to 64 demux STS-192/STM-64 TEXT
datasheet frame
Abstract: PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 PM5363 TUPP+622 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR , -1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES REVISION HISTORY , SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES CONTENTS 1 FEATURES , -1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES 10.3.3 INCOMING , +622 DATASHEET PMC-1981421 PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES ... PMC-Sierra
Original
datasheet

459 pages,
3410.67 Kb

TUPP-622 18AF 1a7h 1ebh 3310h 3310H transistor 3A0F STS-48 STM-16 SDH 209 PM5363 1803 dfh bridge marking Z6 446H IR 1836 3v PMC-1981421 TEXT
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Abstract: -bit TelecomBus) ti STS-1 Switch ez za Serial High Order Path Processor Low Order Path Processor Memory (Time) Switch Working Protect STS-1 Switch Memory (Time) Switch by Serial 04 an u ar · on · Configurable, multi-channel, payload processor for aligning , Payload Processor for 2488.32 Mbit/s oa d ed Protect Crossbar (Space) Switch wn l , Tributary Unit Payload Processor for 2488.32 Mbit/s APPLICATIONS 12 :0 4: 59 AM · SONET ... PMC-Sierra
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datasheet

2 pages,
50.33 Kb

TU12 PM5364 PM5332 EZ 531 TEXT
datasheet frame
Abstract: PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 PM5363 TUPP+622 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR , TUPP+622 DATA SHEET PMC-981421 PMC-981421 ISSUE 2 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S , SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES CONTENTS 1 2 3 4 5 FEATURES , . 107 TRIBUTARY PAYLOAD PROCESSOR (VTPP) . 108 10.3.1 CLOCK GENERATOR , TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES 10.3.4 POINTER INTERPRETER ... PMC-Sierra
Original
datasheet

433 pages,
3992.21 Kb

G708 347H PM5363 PMC-981421 TEXT
datasheet frame
Abstract: Tributary Unit Payload Processor for 2488.32 Mbit/s · Supports 16-byte or 64-byte format tributary path , PM5364 PM5364 TUPP 2488 Released SONET/SDH Tributary Unit Payload Processor for 2488.32 Mbit/s FEATURES Payload Processing Only Configuration. On the line side, provides a 4 x 8-bit or 32 , off-line link verification. · · Configurable, multi-channel, payload processor for aligning SONET , interfaces. · 4 x STS-12/STM-4 STS-12/STM-4 777.6 Mbit/s 8B/10B 8B/10B encoded TelecomBus interfaces. · 1 x STS-48/STM-16 ... PMC-Sierra
Original
datasheet

2 pages,
49.17 Kb

TU12 SDH ADM PM5364 concatenated and OC-3 and STM-1 AU4-16C TEXT
datasheet frame
Abstract: PM5369 PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s 5: 49 AM Released , /STM-64 /STM-64 or STS-48/STM-16 data stream Supports High Order (STS/AU) pointer processing, payload , , multi-channel payload processor for aligning SONET Transmit ESSI Interface Do wn lo Shared , Tributary Unit Payload Processor for 9953 Mbit/s 49 5: 2 • SONET/SDH Add-Drop Multiplexer , Highlights • io fI Block Diagram • • 01 2 01 Low Order Processor (LOPP) Perf ... PMC-Sierra
Original
datasheet

2 pages,
355.23 Kb

PM5369 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
Processor (AD) Added computing platform to a Central Office Switch for additional service 16 kbps up to 384 kbps. The ECSA subworking group T1E1.4 is recommending Discrete Multi-Tone (DMT , connection-oriented switching and multiplexing technology that uses 53-byte cells (5-byte header, 48-byte payload) to , 48-byte payload) to transmit different types of simultaneous traffic, including voice, video, and data. and format that can be contained in the payload of an ATM cell. User traffic is returned to its
/datasheets/files/motorola/design-n/solution/wired/glossary/glossary.htm
Motorola 25/11/1996 32.85 Kb HTM glossary.htm
TNETA1600 TNETA1600 - 155/622Mbps SONET/SDH Frame & Cell Processor TNETA1610 TNETA1610 - 622MHz SONET/SDH ATM into/from a STS-3c/STM-1 Synchronous Payload Envelope (SPE). When the TNETA1500 TNETA1500 is used TNETA1600 TNETA1600 - 155/622Mbps SONET/SDH Frame & Cell Processor The 1600 is capable of operating
/datasheets/files/texas-instruments/sc/docs/network/tcell/tcell.htm
Texas Instruments 12/02/1997 12.47 Kb HTM tcell.htm
SPACING n DEDICATED SOFTWARE DRIVER AVAILABLE n PROCESSOR INDEPENDENT C+ SOURCE COMPILATION n UTOPIA INTERFACE (LEVEL 1 OR 2) n MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA end. The modem control software can be compiled as C+ code, independently on the processor used. can be used: from 8 to 31 for upsteam signals and from 32 to 255 for downstream signals. Numbers 16 processor and is seen as a memory mapped device. MODEM Functions The modem part of the chip
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7162-v1.htm
STMicroelectronics 03/10/2000 15.85 Kb HTM 7162-v1.htm
DSP (Digital Signal Processor) - A processor which is optimized to efficiently compute mathematical Kbps each and a D (data) channel at 16 Kbps. Primary Rate Access (PRA) provides 23 (U.S.) or 30 (Europe transmitted at 1.544 Mbps. The unframed version, or payload, is 192 bits at a rate of 1.536 Mbps. VDSL
/datasheets/files/motorola/design-n/sps/mctg/mdad/adsl_glo.htm
Motorola 25/11/1996 6.44 Kb HTM adsl_glo.htm
) 255 CARRIERS WITH 4.3125KHz SPACING DEDICATED SOFTWARE DRIVER AVAIL - ABLE PROCESSOR INDEPENDENT C+ (LEVEL 1 OR 2) MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY software can be compiled as C+ code, independently on the processor used. The driver can be interfaced to for downstream signals. Numbers 16 and 64 are dedicated to pilot tones which are employed for programmed by an ex - ternal processor and is seen as a memory mapped device. MODEM Functions The modem part
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6314-v1.htm
STMicroelectronics 02/04/1999 14.8 Kb HTM 6314-v1.htm
AVAILABLE n PROCESSOR INDEPENDENT C+ SOURCE COMPILATION n FREQUENCY DIVISION MULTIPLEXING (FDM) FOR HIGH CONNECTION TO ATM SYSTEMS VIA UTOPIA INTERFACE (LEVEL 1 OR 2) n MICROCONTROLLER INTERFACE WITH 16 BITS software can be compiled as C+ code, independently on the processor used. The driver can be interfaced to signals and from 32 to 255 for downstream signals. Numbers 16 and 64 (96 for ADSL over ISDN) are ATM framing. The chip is controlled and programmed by an external processor and is seen
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7162.htm
STMicroelectronics 20/10/2000 16.34 Kb HTM 7162.htm
) 255 CARRIERS WITH 4.3125KHz SPACING DEDICATED SOFTWARE DRIVER AVAIL - ABLE PROCESSOR INDEPENDENT C+ (LEVEL 1 OR 2) MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY software can be compiled as C+ code, independently on the processor used. The driver can be interfaced to for downstream signals. Numbers 16 and 64 are dedicated to pilot tones which are employed for programmed by an ex - ternal processor and is seen as a memory mapped device. MODEM Functions The modem part
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6314-v2.htm
STMicroelectronics 14/06/1999 14.77 Kb HTM 6314-v2.htm
SOFTWARE DRIVER AVAIL - ABLE PROCESSOR INDEPENDENT C+ SOURCE COMPILATION FREQUENCY DIVISION MULTIPLEXING WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY: 1.3w TOTAL SINGLE 3.3V POWER SUPPLY -40 compiled as C+ code, independently on the processor used. The driver can be interfaced to any external Numbers 16 and 64 are dedicated to pilot tones which are employed for synchronisation purposes between programmed by an ex - ternal processor and is seen as a memory mapped device. MODEM Functions The modem part
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6314.htm
STMicroelectronics 20/10/2000 17.17 Kb HTM 6314.htm
SOFTWARE DRIVER AVAIL - ABLE PROCESSOR INDEPENDENT C+ SOURCE COMPILATION FREQUENCY DIVISION ) MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY: 1.3w TOTAL SINGLE C+ code, independently on the processor used. The driver can be interfaced to any external real downstream signals. Numbers 16 and 64 are dedicated to pilot tones which are employed for synchronisation programmed by an ex - ternal processor and is seen as a memory mapped device. MODEM Functions The modem
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6314-v3.htm
STMicroelectronics 25/05/2000 16.6 Kb HTM 6314-v3.htm
and supports 8 and 16 bit operation at 25, 33 and 50 MHz. It includes separate transmit and receive stream of the Transmission Convergence sub-layer of an ATM Physical Layer processor. The input is a byte-aligned cell stream containing 53-byte cells with 5 bytes of header and 48 bytes of payload. CC-200f delineates cells as prescribed in ITU specification I.432 and gives out header and payload. Cell the Transmission Convergence sub-layer of an ATM Physical Layer processor. The input is a byte-aligned
/datasheets/files/xilinx/docs/wcd00031/wcd0318e.htm
Xilinx 17/07/1998 8.31 Kb HTM wcd0318e.htm