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Part Manufacturer Description Datasheet BUY
PIM400K6Z GE Critical Power PIM400 Series; ATCA Board Power Input Module, -36 to -75 Vdc; 400W/10A, I2C Digital Interface & Short pins (3.68mm) visit GE Critical Power
AXA016A0X3-SR12 GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
AXA016A0X3-SR12Z GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
SN74AUP1G79DCKTE4 Texas Instruments AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO5, GREEN, PLASTIC, SC-70, 5 PIN visit Texas Instruments
SN74AUP1G80DCKTE4 Texas Instruments AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, GREEN, PLASTIC, SC-70, 5 PIN visit Texas Instruments
SN74AUP1G79DCKRG4 Texas Instruments AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO5, GREEN, PLASTIC, SC-70, 5 PIN visit Texas Instruments

sr flip flop pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

1LB553

Abstract: Rauland ETS-003 , ALPHA-NUMERIC LISTING OF A L L DEVICES PINK 4 NOT INCLUDED IN THIS EDITION 5 DRAWINGS PIN OUT
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S-R flip flop clock

Abstract: sr flip flop PIN DIAGRAM exception of Syn chronous Reset. Parallel load inputs and flip -flo p outputs are m ultiplexed to m inim ize pin count. Separate inputs and outputs are provided fo r flip -flop s Qo and Q7 to allow easy , LOADING/FAN-OUT: See Section 3 fo r U.L. definitions PIN NAMES CP Dso DS7 So, Si SR OE 1 , OE2 l/O o - I , D-type flip -flop s and the interstage logic necessary to perform synchronous reset, shift left, shift , 323 ^ 54LS/74LS323 Olb / -1 4 ° CO NNECTIO N DIAGRAM PINOUT A 8-BIT UNIVERSAL SHIFT
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S-R flip flop clock sr flip flop PIN DIAGRAM JI/01 74LS323PC 74LS323DC 74LS323FC 54LS323DM 54LS323FM

sr flip flop pin diagram

Abstract: latching flip flop request flip flop low (SR = 0) and latches data. When the CS1 and CS2 signais are enabled, the data (DOO-DO 7) is read onto the microprocessor bus. The signal SR is then reset (SR = 1) on the negative , and resets the SR flip f lop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0} while latching data on its negative transition. Output , the port's register (DO O-DO 7) and service request flip flop. The 1852 operates over a 4â'"10.5
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latching flip flop Hughes newport sr flip flop 1852C D00-D0

siemens master drive circuit diagram

Abstract: SR flip flop IC Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , provide Siemens with a block diagram or logic diagram plus test vectors but no EWS captured schematic or , diagram using Siemens macros. 3. Or, the customer may interface with Siemens after completing schematic
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TC110G siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 M33S004

M54811

Abstract: S o -G ] Eâ'" GND The M54811P consits of an internal-control flip flop, twodigit decimal , applications. The control flip flop is used to control the count ; thé count is enabled when the flip flop is set by input Sy, and dis­ abled when the flip flop is reset by input SP The â'1â' output . state of this flip flop is indicated by the high CL output. While the count is enabled, the count is , control flip flop is se t and count e nable w hen St is set high. St Function Sp Stop Input
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M54811 001S255
Abstract: negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 , buffer register and resets the SR flip flop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0) while latching data on its negative , request flip flop. The 1852 operates over a 4â'"10.5 voltage range while the 1852C operates over a , Supply Low Quiescent and Operating Power PIN CONFIGURATION FUNCTIONAL DIAGRAM DO 0 DO 1 DO 2 -
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H1852 H1852C

SR flip flop IC

Abstract: AN7001 . 14) Flip Flop VCO (i 76kHz x-mm L X à '), f 7 â'" fw ift ') T i Lr-^Sif 38kHz iOtrtCOFlip Flop t, PLL ^ - rjp: jf A- U T £ t T 19 kHz , ±50â'"90 kHz y'o "J ^m/Block Diagram FM QUAD. PET. TUNING METER DRIVE FM IF LIMITER 2 AM RF AMP. 53. FM , Signal : L = 90 %, L + R= 90%, Pilt >t = 10? i) s y-i-lhd) V23-15U) 1 Vi =35 dB, Pin @DC 400 mV s
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AN7001 SR flip flop IC pin diagram 7001 application pll panasonic FM tuner 90mtc 19KHZ

sr flip flop IC

Abstract: Hi-Z Flip-Flop outputs app ear on I/O lines A syn chro nous reset fo r all flip -flop s S ynchro nous reset for all flip -flop s Parallel load all flip -flop s Hold Hold (TC held high) C ount up C o unt dow , 100 mA Typ Fully Synchronous Operation U/D Pin to Control Direction of Counting Separate Pins for M , 24-Pin Separate I/O Port Version See F779 for 16-Pin Version ESD Protection > 4000 Volts PIN ASSIGNMENT MR SR CEP CET Vc c TC U/D PE CS 0E 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) FASTTM
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MC74F579

AN7001

Abstract: SR flip flop IC Mftnmm'C ttL-CA 0 , 15 kHz ÃTW AF tf^-C^uâ'"-rjb'D y ? JilSiJrlii)1) 14) Flip Flop VCO (i 76kHz X-mtä L T à '), f 7 â'" fw ift 'I T £ Lr-^i: 38 kHz CD fz thin Flip Flop £, PLL >v - rjp: Jf A- U T £ t X -yMti 19 kHz , amplifier : gain 45dB ⺠Band muting width designed at ±50â'"90 kHz y'o "J ^m/Block Diagram FM QUAD
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U06E fm mpx demodulator AM IF amplifier 3T11-

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer BC Logical Function 4-Input 4-Wide OR-AND 1 Bit Carry S-R Type Latch D-Type Latch with Reset D-Type Flip Flop with Reset D-Type Flip Flop with Set/Reset J-K Flip Flop with Reset J-K Flip Flop with Set/R eset Toggle Flip Flop with Reset Dual Inverter Dual 2-Input NAND Dual 3-Input NAND Dual 4-Input NAND Dual 2-Input NOR Dual 3-Input NOR Dual 4-Input NOR Dual S-R Type Latch Dual D-Type Flip Flop with Reset , individual resources. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
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74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 MSM60300 MSM60700 MSM61000

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER -lnput NOR 2 3 53 LT2 Dual S-R Type Latch 3 8 54 DFR2 Dual D-Type Flip Flop with Reset 8 8 55 2AD2 Dual 2 , -lnput 4-Wide OR-AND 5 3 38 1CRY 1 Bit Carry 2 10 39 LT S-R Type Latch 2 8 40 DLT D-Type Latch with Reset 2 8 41 DFR D-Type Flip Flop with Reset 4 8 42 DF D-Type Flip Flop with Set/Reset 5 8 43 JKFR J-K Flip Flop with Reset 6 8 44 JKF J-K Rip Flop with Set/Reset 7 8 45 TFR Toggle Flip Flop with , 's BINALY Logic Simulation. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
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bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 74181 74175 clock 74165 block diagram 74151 demultiplexer 74169 binary counter MSMC0300

SR flip flop IC

Abstract: fü HARRIS S E M I C O N D U C T O R ACTS74MS Radiation Hardened Dual D Flip Flop with Set and Reset Pinouts 14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW , 01 [ ? GND ^ ¡3 S2 9 ] Q2 8 ] Q2 14 PIN CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW Description The Harris ACTS74MS is a Radiation Hardened Dual D Flip Flop , /Sam ple AC TS74HM SR TEMPERATURE RANGE -55°C to +125°C -55°C to +125°C 25°C 25°C 25°C SCREENING
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MIL-PRFF-38535 IL-PRF-38535

ATF1500ABV

Abstract: ATF1500ABV-12AC addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In , either the global CLK pin or an individual product term. The flip flop changes state on the clock , , all clock edges are ignored. The flip flop's asynchronous reset signal (AR) can be either the pin , Manufacturer iiimEL Functional Logic Diagram (1) PIN # (PLCC, TQFP) Vcc: (3,41) (15, 9) (23, 17) (35, 29 , ; a flip flop; output select and enable; and logic array inputs. Product Terms and Select Mux Each
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ATF1500ABVL ATF1500ABV ATF1500ABV-12AC ATF1500ABV-12JC ATF1500ABV-15AC ATF1500ABV-15AI ATF1500ABV-15JC 0723D 6/98/XM ATF1500ABV/L

ATF1500ABV

Abstract: ATF1500ABV-12AC ignored. The flip flop's asynchronous reset signal (AR) can be either the pin global clear (GCLR), a , /CASCADE logic; a flip flop; output select and enable; and logic array inputs. Product Terms and Select , . The XOR gate is also used to emulate JK type flip flops. Flip Flop The ATF1500ABV's flip flop has , flip flop can also be configured as a flow-through latch. In this mode, data passes through when the , or an individual product term. The flip flop changes state on the clock's rising edge. When the CLK
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0723C 4/98/XM

ATF1500L

Abstract: internal circuitry for sr flip flop a combinatorial output macrocell. In addition to D, T, JK and SR operation, the flip flop can also , individual product term. The flip flop changes state on the clock's rising edge. When the CLK pin is used as , flip flop's asynchronous reset signal (AR) can be either the pin global clear (GCLR), a product term , terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable , ATF1500/L ATF1500/L ATF1500 Macrocell (Continued) Flip Flop The ATF1500's flip flop has very
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ATF1500L ATF1500-7AC ATF1500-7JC ATF1500-10AC ATF1500-10JC ATF1500-10JI internal circuitry for sr flip flop

ATF1500A

Abstract: ATF1500A-10AC addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In , clock itself can be either the global CLK pin or an individual product term. The flip flop changes state , (Continued) Flip Flop The ATF1500A's flip flop has very flexible data and control functions. The data , (product term) is low, all clock edges are ignored. The flip flop's asynchronous reset signal (AR) can be , the register output if the separate product term is chosen as the flip flop input. The output enable
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ATF1500AL ATF1500A-7AC ATF1500A-7JC ATF1500A-10AC ATF1500A-10JC ATF1500A-10AI ATF1500A/AL
Abstract: , JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode , be either the global CLK pin or an in­ dividual product term. The flip flop changes state on the , view lim isi 1Q7M177 0 0 11 4 5 3 036 0723A 1-183 Functional Logic Diagram (1 ) PIN , multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs. Product , /ABVL â  â  â  id?417? Doimat A4? â  ATF1500ABV/ABVL ATF1500ABV Macrocell (Continued) Flip Flop -
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ATF1500AB ATF1500ABV-15JI ATF1500ABVL-25AC ATF1500ABVL-25JC

ATF1500A

Abstract: ATF1500A-10AC . (continued) ATF1500A/AL In addition to D, T, JK and SR operation, the flip flop can also be configured , . The flip flop changes state on the clock's rising edge. When the CLK pin is used as the clock, one , : product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and , flip flops. Flip Flop The ATF1500A's flip flop has very flexible data and control functions. The , active and the enable signal (product term) is low, all clock edges are ignored. The flip flop
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0759C 04/98/5M

ATF1500A

Abstract: ATF1500A-10AC . (continued) ATF1500A/AL In addition to D, T, JK and SR operation, the flip flop can also be configured , . The flip flop changes state on the clock's rising edge. When the CLK pin is used as the clock, one , : product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and , flip flops. Flip Flop The ATF1500A's flip flop has very flexible data and control functions. The , active and the enable signal (product term) is low, all clock edges are ignored. The flip flop
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ATF1500A-12AC ATF1500A-12JC ATF1500A-15AC ATF1500A-15JC ATF1500AL-20AC ATF1500AL-20JC

ATF1500ABV

Abstract: ATF1500ABV-12AC macrocell. In addition to D, T, JK and SR operation, the flip flop can also be configured as a , low. The clock itself can be either the global CLK pin or an individual product term. The flip flop , logic; a flip flop; output select and enable; and logic array inputs. Product Terms and Select Mux , ATF1500ABV Macrocell (Continued) Flip Flop The ATF1500ABV's flip flop has very flexible data and control , signal (product term) is low, all clock edges are ignored. The flip flop's asynchronous reset signal
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