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Part Manufacturer Description Datasheet BUY
SN7404NE4 Texas Instruments Hex inverters 14-PDIP 0 to 70 visit Texas Instruments
SN7404N8 Texas Instruments TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14 visit Texas Instruments
SN7404J-00 Texas Instruments TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, CDIP14 visit Texas Instruments
SN7404J Texas Instruments TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, CDIP14 visit Texas Instruments
SN7404NSR Texas Instruments TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, SOP-14 visit Texas Instruments
SN7404N-10 Texas Instruments TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, PDIP14 visit Texas Instruments

sn 7404 n ic diagram

Catalog Datasheet MFG & Type PDF Document Tags

14 pin ic 7404

Abstract: sn 7404 n ic diagram IC l IC 2. 5.6 IC 3 IC4 IC 7. 8.9 SN 74132 SN 74107 SN 7404 SN 7474 SN 74161 OS Vss NC NC Vss , Example ?5f2 -t> °IC j ik n -y & - R l Rl r^ 3 n H h i : ] x0 -1 " + 12V ! ! » - r> o , Inspection machines 8. 22 pin dual-in-line package (CERDIP) Block Diagram SHARP 452 CCD Linear , w er dissipation Dark signal output Saturation exposure Saturation output voltage P hoto resp o n se , Linear Image Sensor LZ2019 Timing Diagram Ü U_ _ T L 3 4 5 6 7 i s ^ i9 u 10 11 12 13 ló 14 m
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14 pin ic 7404 sn 7404 n ic diagram pin DIAGRAM OF IC 7474 7474 ic pin configuration pin configuration of ic 7404 7404 ic diagram

14 pin ic 7404

Abstract: pin DIAGRAM OF IC 7474 ) ABC D L ABC D L 71rOl ABC E j-UJ ^w^U] ICi IC2, 5,6 IC3 IC4 IC7,8,9 SN 74132 SN 74107 SN 7404 SN 7474 SN 74161 CK Q Q CLR 1 CK Q Q CLR IC9 CIC Q Q CLR zir- cK RC E(P,T) ABCD L r IC, a CK Q D Q C1 DS , MAX 3. 2048 photoelements on a single chip ; Photo element size 14 m X14 n m 4. Integrated output , package (CERDIP) â  Block Diagram LZ2019 Pin Connections 452 SHARP» SHARP ELEK/ MELEC DIV 1SE 0 I , 0001577 t, | LZ2019 Timing Diagram T-41-55 r_ Jr I 1 i 2 3 4 s o I s » JILÃÃJiiia«!â"¢ Uff _ _ _, ._
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CI 7474 IC 7474 ic 74132 pin DIAGRAM OF IC 7404 ic 7474 pin diagram CI 74107 L12-1-2

sn 7404 n ic diagram

Abstract: IC 7404 INVERTER , SN54LS04, SN 54S 04. J PACKAGE S N 7404. N PACKAGE SN74LS04, SN 74S 04. D OR N PACKAGE (TOP VIEW) C 1 , Package Options Include Standard Plastic · (N) and C eram ic ( J ) 300-mil D ual-ln-Line P a c k a g e s , perature range: S N b 4 ' . SN 74' . 1 , ria te va lu e sp e c ifie d un d er reco m m ended o p era tin g c o n d itio n s. ? A ll ty p ic a l , lu e sp e cifie d un der reco m m en d ed o p era tin g c o n d itio n s, t A ll ty p ic a l valu es
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IC 7404 INVERTER 7404 n ic diagram IC 7404 hex inverter SN6404 logic diagram of ic 7404 SN7404 SN74S04 SN5404 SN54S04 54LS04 54S04

N74S04

Abstract: 54L04 V V 1 = 0-4 V - 20 !o h = SN54Q4 TYP* MAX - 1.5 M IN SN 7404 U N IT TYP* MAX - 1.5 2 .4 0.4 1 40 - , , S N 5 4 S 0 4 . . . FK P AC KAG E logic diagram (each inverter) S N 7 4 L S 0 4 , S N 7 4 S 0 , para m eters Te x a s v In s t r u m e n t s POST O F F IC E BO X 2250 12 · D A L L A S . T E X A S , r o u n d t e r m in a l. . ,n , Te x a s ^ In s t r u m e n t s POST O F F IC E BO X 2 2 50 , free-air tem pe ra ture -5 5 4 .5 2 0.8 - 0.4 16 125 0 NOM 5 MAX 5.5 M IN 4 .7 5 2 0.8 -0 .4 16 70 S N 7404
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N74S04 54L04 SN74S SN54H04 SN54L04 SN74H04
Abstract: Carriers in Addition to Plastic and Ceramic DIPs SN 5404, SN 54H04. S N 5 4 L 0 4 _ I PACKAGE SN 54LS04. S N 5 4 S 0 4 _ I OR W PACKAGE SN 7404. SN 74H04 . . . J OR N PACKAGE SKI74LS04, S N 7 4 S 0 , SN 74LS04, S N 74S 04 . . . FN PACKAGE (TOP VIEW) > A < u 3 O o < z > to V positive logic Y =A TTL DEVICES logic diagram (each inverter) N C - No internal connection , conditions SN 54L04 U N IT M IN S u p p ly vo lta g e V IH H ig h -le v e l in p u t vo lta g e -
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SN54L

sn 74373

Abstract: SN 74114 V ie w log ic V iew sim chip- and board-level sim ulators or with Logic A u to m a tio n 's S m artM , , Valid L ogic and V iew logic library 9 Figure 1. PLS-WS/SN Block Diagram Valid Logic/Viewlogic , schem atics are converted into F D IF 2 0 0 netlist files with V ie w lo g ic 's E D IF N E T O netlist , IF file with V ie w log ic's ED IF reader (E D IF N E T I) for chip- and board-level sim ulation in , (graphics editor) version 3.25 or higher V ie w log ic E D IF N E T O (ED IF netlist writer) version 4.0 or
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC QIC-24

IC AND GATE 7408 specification sheet

Abstract: 74LS96 file. For each C N F , a Ffierarchy Inte rconnect File (.HIF) and a G raph ic Design File (.GDF) are , Sheet Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E , M A X + P L U S for com pilation; com piled designs can b e retu rned to the w o rk s ta tio n for d , X + P L U S . Altera-provided Library M ap ping Files convert basic gate and many co m m o n T T L , functions. Altera EDIF netlist w'riter produ ces post-synthesis logic and delay in fo rm a tio n used d u
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192

IC TTL 7432

Abstract: ic 74138 x4 X1, X3, X5, X7 x2 O0, O2 x2 x2 x2 Figure 1. PLHS501 Logic Diagram April 1989 , Q 0 E Q Q 1 1 Q Q DATA ENABLED E Q 1 0 1 X 1 0 n­1 D Q 0 0 n­1 NOTE: 1. Spikes can occur on Q during the propagation delay of E to Q. NOTES: 1 , LATCHED D E tPD1 HOLD TIME NAND Gate Diagram OPERATING MODE 21 E tPD0 SETUP , Gate Diagram ns MIN 21 Timing Waveforms: CL G3 G4 G5 CLOCK WIDTH SETUP HOLD
Philips Semiconductors
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IC TTL 7432 ic 74138 IC 7400 TTL S20 IC 7400 truth table 74521 comparator free 74ls74 pin configurations ODAT15

14 pin ic 7404 datasheet

Abstract: 4060 4081 4024 50 Hz Crystal oscillator . 3 Block Diagram , sections. 2. Added Green Product Information. 2006/10/20 3. Modified the Functional Block Diagram , change without further notice) EM78F651N 8-Bit Microcontroller 5 Block Diagram Flash ROM , INT Fig. 5-1 Functional Block Diagram Product Specification (V1.1) 10.20.2006 (This , will be cleared by the "WDTC" and "SLEP" instructions. Fig 6-3 depicts the circuit diagram of TCC/WDT
ELAN Microelectronics
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14 pin ic 7404 datasheet 4060 4081 4024 50 Hz Crystal oscillator 7404 pin configuration CIRCUIT DIAGRAM ic 7404 ic 7404 datasheet t 3866 SS-00259 EM78F651 P60/INT P77/TCC P54/OSCO P55/OSCI

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram ) 7404 EL 1 2 SET G1 DFFS GND PN D CLBMZ DFFS Q QN RN SN DN CK FF1 Q0 , generated at the input receivers. Hence, this diagram could be trimmed by six gates, down to eight to , * * A2 A3 A4 A5 A6 A7 L4 L5 L6 L7 C O S S S M H H H P P I I I L I F F F M N A A T T , DECODERS RW R7 ­ R0 DCDREN Figure 15. 12-Bit Comparator with Dual 1 ­ 8 Decoders Block Diagram , is a block diagram showing the individual components needed for each bit. A carry input (C0) is
Philips Semiconductors
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full 18*16 barrel shifter design IC 3-8 decoder 74138 pin diagram full adder using ic 74138 TTL SN 7404 pn sequence generator using d flip flop 12 bit comparator AN049

6821 pia

Abstract: PIA 8255 E H i J K L M N P R 5 T U 1 / W X Y z r \ J / \ _ _ -A D V A N C E D S E M IC O N D U C T O R D E V IC E S (P T Y ) L TD . P .O . B O X 2 944 J O H A N N E S B U R G 2 000 T E L . , ' 3 0 = LO G IC " 0 " 1 = L O G IC " 1 " X = D O N 'T C A R E C E t C E 2 CLR CUE CU W R A, A0 , X = D O N 'T C ARE 0 = L O G IC "O '' 1 = L O G IC " 1 " X = D O N 'T C A R E Figure 8. Logic , 1 = L O G IC " 1 " 0 = L O G IC " 0 " X = D O N 'T C A R E Figure 10a. Design Example - Logic
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HPDL-2416 6821 pia PIA 8255 hdpl2416 HPDL-2614 truth table for ic 7404 8085 microprocessor program H100-1650 R6510

16CUDSLR

Abstract: 7474 D flip flop free PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , G rap h ic and T ext E d ito rs w ith the d elay p red ictio n featu re. A fter the so u rce and d , e lo p m e n t P ro d u c ts Graphic & Symbol Editors T h e M A X + P L U S G rap h ic E d itor , the au tom atically g en erated log ic functions. S tan d ard B o o lea n fu n ctio n s, e.g ., AND , lo p m e n t P ro d u c ts SSI Gate CBUF, INHB, 7400, 7402, 7404, 7408, 7410, 7411, 7420, 7421
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16CUDSLR 7474 D flip flop free alu 74382 pin diagram of ic 74190 counter schematic diagram 74161 ALU IC 74381
Abstract: . 5 5 Block Diagram , /10/20 3. Modified the Functional Block Diagram. 1. Added Quality Assurance and Reliability. 2 , Block Diagram Flash ROM PC Instruction Register 5-levelstack (13 bi t) Crystal Int , Circuit EEPROM Ext INT Figure 5 Functional Block Diagram 6â'¢ Product Specification (V1 , â'WDTCâ' and â'SLEPâ' instructions. Figure 6-3 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an ELAN Microelectronics
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EM78F651N-R 0810R EM78F651N-U 0810U
Abstract: EM78F651ND18/SO18 EM78F651ND20/SS20 7 7 7 7 7 Block Diagram , information. 3. Modified the Functional Block Diagram. 2006/10/20 1.2 1. Added Quality Assurance and , Block Diagram Flash ROM PC Instruction Register 5-level stack (13 bi t) Crystal Int , Circuit EEPROM Ext INT Figure. 5 Functional Block Diagram 6â'¢ Product Specification (V1 , â'WDTCâ' and â'SLEPâ' instructions. Figure. 6-3 depicts the circuit diagram of TCC/WDT. R1 (TCC) is ELAN Microelectronics
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A/20V

JRC 45600

Abstract: YD 803 SGS Substitution Guide U D C 621.382.3 Diagram s THE S E M IC O N INTERNATIONAL INDEXES Volume 1 - , : S E M IC O N INDEXES O Box 470, London, SE1 2 8AF United Kingdom 'el/fax:+ 44(0)1 81 -8 5 2 -2 3 , Anschluflzeichnungen DIE S E M IC O N INTERNATIONALEN INDEXE Band 1: T RAN SISTO REN - Ausgabe 22 Weichgebunden , Bezeichnungen. Herausgegeben von: S E M IC O N INDEXES P.O. Box 470, London, SE12 8AF GroBbritannien , MANUFACTURER S E M IC O N HERSTELLER - CONSTRUCTEUR CODE A A BB DRIVES AB A BB H A F O AB A B B
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JRC 45600 YD 803 SGS 45600 JRC TDA 7277 krp power source sps 6360 TDA 5072 ZOP020 ZOP021 ZOP023 ZOP022 ZOP024 ZOP025

EM78F651ND18J

Abstract: 1e9k . 5 Block Diagram , . Modified the Functional Block Diagram. 1. Added Quality Assurance and Reliability. 2. Modified the DC , EM78F651N 8-Bit Microcontroller 5 Block Diagram Flash ROM PC Instruction Register 5 , P55 P56 P57 Interrupt Circuit EEPROM Ext INT Figure 5-1 Functional Block Diagram 6 , cleared by the "WDTC" and "SLEP" instructions. Figure 6-3 depicts the circuit diagram of TCC/WDT. R1
ELAN Microelectronics
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EM78F651ND18J 1e9k prescaler sp 4653 EM78F651ND EM78F651NSO18J EM78F651N-10

NEC 421000

Abstract: TTL 7404 J V f« L Z NEC Electronics Inc. APPLICA TIO N NOTE 5 3 //P D 4 2 10 00 /y u P D 421 00 1/yu P D 4 21 002 1 - m e g a b it d y n a m ic r a m s Description NEC's uPD421000, uPD421001, and , AS [o r CS] 23 Z I N C M em ory C ell Stru ctu re D yn am ic RAM s g e n e ra lly fe a tu re o n , ritten to m em ory cells C sn , CS21 Csni S w itch Y-i is then selected by the colum n address, and the , . N ibble-M ode B lo ck Diagram and Exam ple o f Access Sequence S tq u in w _ B it_ A g A g
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PD71088 LS112 NEC 421000 TTL 7404 421000 60 7404 421000 70 PD421000 PD421001 PD421002 26/20-P

14 pin ic 7404 datasheet

Abstract: P56. smd . 3 Block Diagram , Diagram. 2006/10/20 1.2 1. Added Quality Assurance and Reliability 2. Modified the DC Electrical , subject to change without further notice) EM78F651N 8-Bit Microcontroller 5 Block Diagram , INT Fig. 5 Functional Block Diagram Product Specification (V1.2) 10.22.2007 (This specification , depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can
ELAN Microelectronics
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P56. smd WORKING OF IC 7404 EM78F651NAM

74L42

Abstract: ic : 2C y = K5Z schematic (each gate) SN 54S20, SN 74S20 D U A L 4 - IN P U T N A N D G A , ic : 1D 1Y GND Y = ABCD recommended operating conditions S N 54S00, SN 54S04, S N , in the following example. EXAMPLE: SN 54H72 N -0 0 Q . Prefix > MUST CONTAIN TWO OR THREE LETTERS , ig n a tio n f o r an ir o n - n ic k e l- c o b a lt a llo y c o n ta in in g n o m in a lly 5 3 % ir o n , 2 9 % n ic k e i, a n d 17 % c o b a lt. 1-3 INTEGRATED CIRCUITS MECHANICAL DATA H
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74L42 SN15302 SN15303 SN15321 SN15324 SN15301 SN15312

SN7441

Abstract: 74L78 s t r u m e n t s IN C O R P O R A T E D P O S T O F F IC E B O X 5 0 1 2 â'¢ D ALLAS , st co m p le te 1C logic A n o th e r fa m ily w ith a c h o ic e o f over 9 0 d is tin c t fu , o rta n t fea tu re w h ic h reduces overall three co m p a tib le p e rfo rm a n ce , ris o n o f ty p ic a l saturated d ig ita l lo g ic fa m ily are co m m o n between the three fam , advantages o f saturated lo g ic c irc u itry and m o n o lith ic s e m ic o n d u c to r te c h n o lo g y
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SN7441 74L78 Sw 7441Aj u6a9601 74l95 N8490 54H/74H 54L/74L
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