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sirf 1v

Catalog Datasheet MFG & Type PDF Document Tags

sirf atlas v

Abstract: SiRF prima ACT8935 Rev 4, 17-Sep-13 Advanced PMU for SiRF PrimaTM and Atlas IVTM FEATURES GENERAL , control requirements of the SiRF PrimaTM and Atlas IVTM processors. Optimized for SiRF PrimaTM/Atlas , ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. SiRF PrimaTM and Atlas IVTM are trademarks of SiRF Technology, Inc. -1- www.active-semi.com Copyright © 2013 , . p. 27 Interfacing with the SiRF PrimaTM/Atlas IVTM
Active-Semi
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sirf atlas v SiRF prima sirf atlas 5 sirf Atlas IV TQFN55-40

RA45H7687M1

Abstract: mitsubishi rf MITSUBISHI RF POWER SEMICONDUCTORS APPLICATION NOTE Document NO. AN-900-026 Date : 21st Feb. 2007 Prepared : K. Mori Confirmed : S. Kametani (Taking charge of SiRF by Miyoshi Electronics) SUBJECT: Recommendation of the output power control for RA45H7687M1 GENERAL: Figure 1 shows recommended output power control of RA45H7687M1, which can be controlled by VGG2 and Pin adjusters. RF , =3.4V, VGG2=5V, Pin=17dBm Pout2 Output Power 2 TYP VDD=15.2V, VGG1=3.4V, VGG2=1V, Pin=2dBm MAX
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mitsubishi rf sirf 1v GG13 764MH 785MH 806MH 835MH 870MH

SiRF prima

Abstract: TPS650721RSL for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , drops below 1V. EN_wLED 47 I TPS650701, TPS650702, TPS650721, TPS65072, : This pin is the , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , ) delay + Vref =1V AGND 16 Submit Documentation Feedback
Texas Instruments
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TPS650721RSL sirf atlas VI TPS65070 TPS65073 TPS650731 TPS650732 SLVS950F A/500

sirf Atlas III

Abstract: SiRF prima < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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sirf Atlas III Atlas SIRF 5 450 B2 OpAmp DIL SLVS950E A/1300 TPS6507 ISO/TS16949

sirf atlas 4

Abstract: advanced thermal products thermistor ntc 50k < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS65070 , :Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS65072, : This pin , SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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sirf atlas 4 advanced thermal products thermistor ntc 50k thermistor ntc 10k characteristic SLVS950D

SiRF prima

Abstract: sirf atlas 4 for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD) Copyright
Texas Instruments
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TPS65070RSL sirf atlas iv datasheet SiRF Atlas Atlas SIRF 4 omap3530 EVM iac100 SLVS950B

RT9941

Abstract: SiRF Titan the VSYS Voltage and the internal reference voltage is 1V Ground. The exposed pad must be soldered to , VOUT3 VOUT4 VIN2 VOUT5 PWR_HOLD nLBO 1V LDO4 LDO5 LBI nINT DATA CLK GND , , VLDO2 Power On VPWR_EN, VLDO2, VLDO4, VLDO5 VLDO3 (1V/Div) VBuck2 (1V/Div) VLDO1 (500mV/Div , ) Normal to Sleep Mode VPWR_EN (1V/Div) VBuck2 (1V/Div) VLDO2 (1V/Div) VBATT = 4V VBATT = 4V Time , voltages for SiRF TitanII and A4 platform are listed in Table 4 as following : Table 4. The RT9941 for
RichTek Technology
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SiRF Titan WQFN-40L sirf a5 RT99 DS9941-01

SiRF prima

Abstract: SiRF Atlas < 1 mA ; Vo < 1V RDIS VOUT ramp up time (1) 8 1% 2.5% 400 Time to ramp from 5% to , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS65072 , Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ[2.0] = 111. EN_EXTLDO , THRESHOLD PGND4/PAD (EN_wLED) Reset - (EN_EXTLDO ) delay + Vref =1V AGND 16
Texas Instruments
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sirf iv OMAP3505 Atlas IV schematic diagram converter input 12v to 24v 4a OMAP35xx SiRF SLVS950A

sirf iii c

Abstract: sirf atlas v < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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sirf iii c

TPS650702

Abstract: sirf atlas v IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO
Texas Instruments
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SIRF III sirf IV atlas

SiRF prima

Abstract: SN74LVC1G06DCK 0.5 V (min. 2.8 V) to 6.5 V, ILDO1 = 100 mA; ILDO2 = 100 mA IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V , below 1V. TPS65072: This pin is the actively high enable input for the wLED driver. The wLED converter , pulled internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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SN74LVC1G06DCK t890 1300MA tps65731

SiRF Atlas

Abstract: SiRF prima < 1 mA ; Vo < 1V RDIS VOUT ramp up time (1) 8 1% 2.5% 400 Time to ramp from 5% to , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS65072 , Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ[2.0] = 111. EN_EXTLDO , THRESHOLD PGND4/PAD (EN_wLED) Reset - (EN_EXTLDO ) delay + Vref =1V AGND 16
Texas Instruments
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10bit dac i2c express card T0 USB ntc 50-15 texas instruments pressure switch SLVS950

SiRF prima

Abstract: 0.5 V (min. 2.8 V) to 6.5 V, ILDO1 = 100 mA; ILDO2 = 100 mA IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V , below 1V. TPS65072: This pin is the actively high enable input for the wLED driver. The wLED converter , pulled internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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TPS650702RSL

Abstract: t890 < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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TPS650702RSL

sirf iii c

Abstract: < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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TPS650702

Abstract: , LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS VOUT , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS650701 , internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or , - (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD
Texas Instruments
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SLVS950G

sirf atlas 3

Abstract: < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS65070 , :Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS65072, : This pin , SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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sirf atlas 3

TPS650702

Abstract: sirf iii c IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO
Texas Instruments
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Abstract: IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO Texas Instruments
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SiRF prima

Abstract: sirf atlas 4 for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD) Copyright
Texas Instruments
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atlas 4 DC-DC21 L442
Abstract: for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD) Copyright  Texas Instruments
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sirf atlas VI

Abstract: SiRF prima < 1V ­1% ­1% ­1% ­2.5% 400 250 1.8 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5% 1% 1% 2.5% µs mA mA mA , comparator. RESET will be LOW if this voltage drops below 1V. TPS65072: This pin is the actively high enable , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16
Texas Instruments
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cccv 0B4b1

sirf atlas VI

Abstract: < 1V ­1% ­1% ­1% ­2.5% 400 250 1.8 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5% 1% 1% 2.5% µs mA mA mA , :Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS65072: This pin is , voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 processors with , ) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation
Texas Instruments
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titan b3

Abstract: DPM 24 40000 mf to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5 , below 1V. Open drain active low reset output, reset delay time. The status depends on the voltage , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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titan b3 DPM 24 40000 mf TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1
Abstract: to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5 , below 1V. Open drain active low reset output, reset delay time. The status depends on the voltage , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright Texas Instruments
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MARKING 2L qfn led

Abstract: Atlas SIRF 5 to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5 , below 1V. Open drain active low reset output, reset delay time. The status depends on the voltage , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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MARKING 2L qfn led

DIODE MARKING 226V

Abstract: sirf iii c to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5 , below 1V. Open drain active low reset output, reset delay time. The status depends on the voltage , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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DIODE MARKING 226V
Abstract: < 1 mA ; Vo < 1V RDIS VOUT ramp up time 1% 2.5% 400 (1) 8 Time to ramp from 5% to , reset comparator. RESET will be LOW if this voltage drops below 1V. RESET 39 O Open drain , PGND4/PAD (EN_wLED) Reset - (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Texas Instruments
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Abstract: to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 1.2 1.8 1.2 1.2 1.8 200 400 400 150 150 1.5 , below 1V. Open drain active low reset output, reset delay time. The status depends on the voltage , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright Texas Instruments
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Sirf Atlas IV

Abstract: /OFF Control with System Reset Dual 150mA Current Limited LDOs Start-Up Timing Compatible with SiRF , sequencing designed to support the SiRF Atlas IV processor. The LTC3677-3 is available in a low profile , Input High Voltage ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V , OVP Connection Waveform VOUT1 100mV/DIV (AC) 2V VBUS 5V/DIV VOUT3 1V 0V OVGATE 5V , UVLO circuit on the DVCC pin forces all registers to all 0s whenever DVCC is
Linear Technology
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LTC3556 QFN28 LTC3557/ LTC3557-1 LTC3577/ LTC3577-1

sirf Atlas IV

Abstract: SiRF Atlas Dual 150mA Current Limited LDOs n Start-Up Timing Compatible with SiRF Atlas IV Processor n Small , and system reset. The LTC3677-3 has pushbutton timing and sequencing designed to support the SiRF , ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V VCHRG CHRG Pin Output , VBUS 5V/DIV VOUT3 1V 0V OVGATE 5V/DIV 400mA IL3 200mA 0mA VOUT1 = 1.8V IOUT1 = 100mA , registers to all 0s whenever DVCC is
Linear Technology
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zener 3.7v 1000mA si2323 PMOS ltc3577 LTC3677EUFF-3 Si2333DS Si2323 10-LED QFN44
Abstract: Start-Up Timing Compatible with SiRF Atlas IV Processor Small 4mm × 7mm 44-Pin QFN Package , designed to support the SiRF Atlas IV processor and has pushbutton timing and sequencing different from , Input High Voltage ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V , VBUS 5V/DIV VOUT3 1V OVGATE 5V/DIV 0V OVGATE 5V/DIV 400mA IL3 200mA 0mA VOUT1 = 1.8V , to all 0s whenever DVCC is Linear Technology
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LTC3577-3/LTC3577-4 LTC3577-3 LTC3577-4 3577-3/LTC3577-4 DFN14 LTC4088-1

668I

Abstract: Compatible with SiRF Atlas IV Processor Small 4mm × 7mm 44-pin QFN package APPLICATIONS n n n , dimming via the I2C input. The LTC3577-3/LTC3577-4 are designed to support the SiRF Atlas IV processor , Pull-Down Current ILIM0, ILIM1; VPIN = 1V VCHRG CHRG Pin Output Low Voltage ICHRG = 10mA , Waveform VBUS 5V/DIV VBUS 5V/DIV VOUT3 1V OVGATE 5V/DIV 0V OVGATE 5V/DIV 400mA IL3 , pin forces all registers to all 0s whenever DVCC is
Linear Technology
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668I LTC4088-2 LTC4098 QFN20

sirf atlas v

Abstract: sirf Atlas IV Limited LDOs Start-Up Timing Compatible with SiRF Atlas IV Processor Small 4mm × 7mm 44-pin QFN package , LTC3577-3 is designed to support the SiRF Atlas IV processor and has pushbutton timing and sequencing , Pull-Down Current ILIM0, ILIM1; VPIN = 1V VCHRG CHRG Pin Output Low Voltage ICHRG = 10mA , ) FEEDBACK (V) 0.85 0.80 PULSE SKIP VOUT3 1V Burst Mode OPERATION 0.81 0.80 0V 400mA , whenever DVCC is
Linear Technology
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transistor 107A equivalent express card DVB FOR Thermistor NTC 278A LTC3577EUFF3 35773

sirf Atlas IV

Abstract: sirf atlas v Start-Up Timing Compatible with SiRF Atlas IV Processor Small 4mm × 7mm 44-Pin QFN Package , SiRF Atlas IV processor and has pushbutton timing and sequencing different from other LTC3577 versions , Input High Voltage ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V , VBUS 5V/DIV VBUS 5V/DIV VOUT3 1V OVGATE 5V/DIV 0V OVGATE 5V/DIV 400mA IL3 200mA , DVCC is
Linear Technology
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marking g06 Si2306BDS

pxa168

Abstract: Marvell Armada VSOC 0.625V TO 1.25V AT 1A I/O WAKE (1V/DIV) VSRAM 0.5V/DIV ANALOG VSOC MEMORY 2.7µH , 1V/DIV VOUT VOUT 1V/DIV VOUT 50mV/DIV PGOOD 5V/DIV 500mA/DIV IL 100µs/DIV , 150 TEMPERATURE (°C) 0 0 50 100 3589 G28 1V/DIV 400 350 300 250 200 ­50 ­25 , reference level of SCL and SDA I2C pins. DVDD resets I2C registers to power on state when driven to
Linear Technology
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LTC3589 pxa168 Marvell Armada marvell armada datasheet pxa3xx Marvell PXA Marvell PXA168 LTC3101 QFN-28 LTC3577-1/ LTC3577-3/ QFN-44

sirf Atlas IV

Abstract: VCORE 0.6V TO 1.2V AT 1.6A VSRAM 0.9V TO 1.8V AT 1A VSOC 0.625V TO 1.25V AT 1A 0.5V/DIV WAKE (1V/DIV , Soft-Start VOUT 1V/DIV 5V/DIV 500mA/DIV IL 5V/DIV VSTB 1A/DIV 200µs/DIV VRRCR = 1.75mV/µs 3589 G20 VIN = , VOUT Dynamic Voltage Slew 1V/DIV VOUT PGOOD 50mV/DIV ILOAD 100µs/DIV 3589 G19 40µs/DIV , LDO1 Load Step Response 1.2V 1V/DIV 220mA VEN_LDO2,VEN_LDO34 ILDO 100mA/DIV 10mA 100µs/DIV 3589 , to power on state when driven to
Linear Technology
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ZXMP10A18G LTC3586/ LTC3586-1 QFN-38

pxa168

Abstract: Marvell Armada 1.2V AT 1.6A SW1 LDO3 SW3 1F 22F 3 7 WAKE (1V/DIV) VSRAM 0.5V/DIV ANALOG , Step-Down Switching Regulator 1 Load Step Dynamic Voltage Slew PULSE-SKIPPING MODE 1V/DIV VOUT 3589 G18 200s/DIV 0.5 VOUT 1V/DIV VOUT 50mV/DIV PGOOD 5V/DIV 500mA/DIV ILOAD , Response LDO1 Load Step Response VLDO4 =2.8V VLDO3 =1.8V 1V/DIV VLDO 50mV/DIV VLDO1 50mV , on state when driven to
Linear Technology
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Marvell PXA168 Application Processor MARVELL g31 Marvell PXA3xx LD34 LTC3589EUJ LTC3589HUJ

LDO16

Abstract: sirf atlas iv VCORE SW4CD ENABLES FROM PROCESSOR VSOC 0.625V TO 1.25V AT 1A SW3 LDO4 3 WAKE (1V , Soft-Start Step-Down Switching Regulator 1 Load Step Dynamic Voltage Slew VOUT VOUT 1V/DIV , Response VLDO4 =2.8V VLDO3 =1.8V 1V/DIV VLDO 50mV/DIV 1.8V VLDO1 50mV/DIV 1.2V VLDO2 , . DVDD resets I2C registers to power on state when driven to
Linear Technology
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LDO16 LTC3589IUJ A/400

sirf atlas iv datasheet

Abstract: sirf atlas v OUTPUT 0.5V/DIV 0.810 0.805 0V 0.800 LDO OUTPUT 1V/DIV 0.795 0V 0.790 0.785 0.2 , ) HIGH STBY LOW BUCK OUTPUT 0.5V/DIV 140 0V 120 100 LDO OUTPUT 1V/DIV 80 60 0V , sufficient input power is available in constant-current mode, this pin servos to 1V. The voltage on this pin
Linear Technology
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LTC3553 sirf atlas v frequency LTC3554 thermistor TD04 005 1117AS regulator 317K sirf atlas v datasheet LTC4080 DFN-10

summing amplifier DAC

Abstract: led constant current driver 350mA TA01a Start-Up Sequence 1µH SW1 22µF 0.5V TO VIN AT 1.6A 0.5V TO VIN AT 1A 0.5V/DIV WAKE (1V/DIV , Soft-Start VOUT 1V/DIV 5V/DIV 500mA/DIV IL 5V/DIV VSTB 1A/DIV 200µs/DIV VRRCR = 1.75mV/µs 3589 G20 VIN = , VOUT Dynamic Voltage Slew 1V/DIV VOUT PGOOD 50mV/DIV ILOAD 100µs/DIV 3589 G19 40µs/DIV , VLDO1 50mV/DIV LDO1 Load Step Response 1.2V 1V/DIV 220mA VEN_LDO2,VEN_LDO34 ILDO 100mA/DIV , reference level of SCL and SDA I2C pins. DVDD resets I2C registers to power on state when driven to
Linear Technology
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summing amplifier DAC led constant current driver 350mA imx53 LTC3589/LTC3589-1 3589/LTC3589-1 LTC3589-1 MX53/51

LTC3589UJ-2

Abstract: LTC3589UJ TO VIN AT 1.6A WAKE (1V/DIV) SW2 0.5V/DIV 0.5V TO VIN AT 1A LDO3 SW3 LDO2 SW1 500s/DIV 1.8V TO 5V 4 , PERFORMANCE CHARACTERISTICS Buck-Boost Switching Regulator Soft-Start VOUT 1V/DIV 5V/DIV 500mA/DIV IL 5V/DIV , . Step-Down Switching Regulator 1 Load Step PULSE-SKIPPING MODE VOUT Dynamic Voltage Slew 1V/DIV VOUT , =1.8V 1V/DIV VLDO2 =1.2V VLDO 50mV/DIV LDO2, LDO3, LDO4 Load Step Response LDO1 Load Step Response , to power on state when driven to
Linear Technology
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LTC3589UJ-2 LTC3589UJ iMX536 LTC3589/LTC3589-1/ LTC3589-2 ZXMN10A08E6

Marvell Armada

Abstract: AT 1A 0.5V/DIV WAKE (1V/DIV) SW2 LDO3 SW3 LDO2 SW1 500µs/DIV 1.8V TO 5V 4 22µF 3589 TA01b BB_OUT , Performance Characteristics Buck-Boost Switching Regulator Soft-Start VOUT 1V/DIV 5V/DIV 500mA/DIV IL 5V/DIV , . Step-Down Switching Regulator 1 Load Step PULSE-SKIPPING MODE VOUT Dynamic Voltage Slew 1V/DIV VOUT , 1.8V VLDO1 50mV/DIV LDO1 Load Step Response 1.2V 1V/DIV 220mA VEN_LDO2,VEN_LDO34 ILDO 100mA , state when driven to
Linear Technology
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sirf atlas v

Abstract: LTC3589UJ-1 BB_OUT WAKE (1V/DIV) 0.5V/DIV 1.5H 1.8V AT 250mA 2.8V AT 250mA SW2 LDO2 0.5V TO , . Step-Down Switching Regulator 1 Load Step Dynamic Voltage Slew PULSE-SKIPPING MODE 1V/DIV VOUT VOUT 1V/DIV VOUT 50mV/DIV PGOOD 5V/DIV 500mA/DIV ILOAD VSTB IL 100s/DIV 5V , VLDO4 =2.8V VLDO3 =1.8V 1V/DIV VLDO 50mV/DIV VLDO1 50mV/DIV 1.8V 1.2V VLDO2 =1.2V , level of SCL and SDA I2C pins. DVDD resets I2C registers to power on state when driven to
Linear Technology
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LTC3589UJ-1 LTC3589IUJ-1 3589 LTC3589EUJ-1#PBF LTC3589H
Abstract: SW3 1µF BB_OUT WAKE (1V/DIV) 0.5V/DIV 1.5µH 1.8V AT 250mA 2.8V AT 250mA SW2 , Dynamic Voltage Slew PULSE-SKIPPING MODE 1V/DIV VOUT VOUT 1V/DIV VOUT 50mV/DIV PGOOD , Response VLDO4 =2.8V VLDO3 =1.8V 1V/DIV VLDO 50mV/DIV VLDO1 50mV/DIV 1.8V 1.2V VLDO2 , level of SCL and SDA I2C pins. DVDD resets I2C registers to power on state when driven to Linear Technology
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sirf Atlas IV

Abstract: 3675f 1V/DIV INDUCTOR CURRENT 500mA/DIV EN6 2V/DIV 100s/DIV 3675 G38 300 250 200 150 100
Linear Technology
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LTC3675 3675f LTC3675EUFF fb4 lt 405 810 mlps3015-2r2 LTF5022-2R2 LPS3015-222 LTC3569

sirf atlas iv

Abstract: C3675 3 3.3 3.6 VIN (V) 3.9 4.2 3675 G39 VOUT6 1V/DIV INDUCTOR CURRENT 500mA/DIV EN6 2V/DIV 100s/DIV
Linear Technology
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C3675 IHLP2020BZER-10RM01

sirf Atlas IV

Abstract: VOUT6 = 3.3V 300 250 200 150 100 50 0 2.7 3 3.3 3.6 VIN (V) 3.9 4.2 36751 G39 VOUT6 1V/DIV INDUCTOR
Linear Technology
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LTC3675/LTC3675-1 0001001X LTC3675-1 0110100X 3675/LTC3675-1
Abstract: VOUT6 = 3.3V 300 250 200 150 100 50 0 2.7 3 3.3 3.6 VIN (V) 3.9 4.2 36751 G39 VOUT6 1V/DIV INDUCTOR Linear Technology
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Abstract: Deliverability 400 PWM MODE 350 VOUT6 = 3.3V REDUCTION BELOW 1A (mA) VIN = 3.6V VOUT6 1V/DIV Linear Technology
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