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sirf 1v

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sirf atlas v

Abstract: SiRF prima ACT8935 Rev 4, 17-Sep-13 Advanced PMU for SiRF PrimaTM and Atlas IVTM FEATURES GENERAL , control requirements of the SiRF PrimaTM and Atlas IVTM processors. Optimized for SiRF PrimaTM/Atlas , ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. SiRF PrimaTM and Atlas IVTM are trademarks of SiRF Technology, Inc. -1- www.active-semi.com Copyright © 2013 , . p. 27 Interfacing with the SiRF PrimaTM/Atlas IVTM
Active-Semi
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sirf atlas v SiRF prima sirf atlas 5 sirf Atlas IV TQFN55-40

RA45H7687M1

Abstract: mitsubishi rf MITSUBISHI RF POWER SEMICONDUCTORS APPLICATION NOTE Document NO. AN-900-026 Date : 21st Feb. 2007 Prepared : K. Mori Confirmed : S. Kametani (Taking charge of SiRF by Miyoshi Electronics) SUBJECT: Recommendation of the output power control for RA45H7687M1 GENERAL: Figure 1 shows recommended output power control of RA45H7687M1, which can be controlled by VGG2 and Pin adjusters. RF , =3.4V, VGG2=5V, Pin=17dBm Pout2 Output Power 2 TYP VDD=15.2V, VGG1=3.4V, VGG2=1V, Pin=2dBm MAX
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mitsubishi rf sirf 1v GG13 764MH 785MH 806MH 835MH 870MH

SiRF prima

Abstract: TPS650721RSL for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , drops below 1V. EN_wLED 47 I TPS650701, TPS650702, TPS650721, TPS65072, : This pin is the , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , ) delay + Vref =1V AGND 16 Submit Documentation Feedback
Texas Instruments
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TPS650721RSL sirf atlas VI TPS65070 TPS65073 TPS650731 TPS650732 SLVS950F A/500

sirf Atlas III

Abstract: SiRF prima < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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sirf Atlas III Atlas SIRF 5 450 B2 OpAmp DIL SLVS950E A/1300 TPS6507 ISO/TS16949

sirf atlas 4

Abstract: advanced thermal products thermistor ntc 50k < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS65070 , :Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS65072, : This pin , SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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sirf atlas 4 advanced thermal products thermistor ntc 50k thermistor ntc 10k characteristic SLVS950D

SiRF prima

Abstract: sirf atlas 4 for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD) Copyright
Texas Instruments
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TPS65070RSL sirf atlas iv datasheet SiRF Atlas Atlas SIRF 4 omap3530 EVM iac100 SLVS950B

RT9941

Abstract: SiRF Titan the VSYS Voltage and the internal reference voltage is 1V Ground. The exposed pad must be soldered to , VOUT3 VOUT4 VIN2 VOUT5 PWR_HOLD nLBO 1V LDO4 LDO5 LBI nINT DATA CLK GND , , VLDO2 Power On VPWR_EN, VLDO2, VLDO4, VLDO5 VLDO3 (1V/Div) VBuck2 (1V/Div) VLDO1 (500mV/Div , ) Normal to Sleep Mode VPWR_EN (1V/Div) VBuck2 (1V/Div) VLDO2 (1V/Div) VBATT = 4V VBATT = 4V Time , voltages for SiRF TitanII and A4 platform are listed in Table 4 as following : Table 4. The RT9941 for
RichTek Technology
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SiRF Titan WQFN-40L sirf a5 RT99 DS9941-01

SiRF prima

Abstract: SiRF Atlas < 1 mA ; Vo < 1V RDIS VOUT ramp up time (1) 8 1% 2.5% 400 Time to ramp from 5% to , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS65072 , Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ[2.0] = 111. EN_EXTLDO , THRESHOLD PGND4/PAD (EN_wLED) Reset - (EN_EXTLDO ) delay + Vref =1V AGND 16
Texas Instruments
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sirf iv OMAP3505 Atlas IV schematic diagram converter input 12v to 24v 4a OMAP35xx SiRF SLVS950A

sirf iii c

Abstract: sirf atlas v < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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sirf iii c

TPS650702

Abstract: sirf atlas v IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO
Texas Instruments
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SIRF III sirf IV atlas

SiRF prima

Abstract: SN74LVC1G06DCK 0.5 V (min. 2.8 V) to 6.5 V, ILDO1 = 100 mA; ILDO2 = 100 mA IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V , below 1V. TPS65072: This pin is the actively high enable input for the wLED driver. The wLED converter , pulled internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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SN74LVC1G06DCK t890 1300MA tps65731

SiRF Atlas

Abstract: SiRF prima < 1 mA ; Vo < 1V RDIS VOUT ramp up time (1) 8 1% 2.5% 400 Time to ramp from 5% to , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS65072 , Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ[2.0] = 111. EN_EXTLDO , THRESHOLD PGND4/PAD (EN_wLED) Reset - (EN_EXTLDO ) delay + Vref =1V AGND 16
Texas Instruments
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10bit dac i2c express card T0 USB ntc 50-15 texas instruments pressure switch SLVS950

SiRF prima

Abstract: 0.5 V (min. 2.8 V) to 6.5 V, ILDO1 = 100 mA; ILDO2 = 100 mA IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V , below 1V. TPS65072: This pin is the actively high enable input for the wLED driver. The wLED converter , pulled internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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TPS650702RSL

Abstract: t890 < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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TPS650702RSL

sirf iii c

Abstract: < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS650702 , if this voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for , used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or DCDC_SQ , =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback Copyright
Texas Instruments
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TPS650702

Abstract: , LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS VOUT , reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED 47 I TPS650701 , internally to the SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or , - (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD
Texas Instruments
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SLVS950G
Abstract: IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO Texas Instruments
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sirf atlas 3

Abstract: < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073, TPS650731, TPS650732 For TPS65070 , :Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS65072, : This pin , SYS voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 , delay + Vref =1V Reset (EN_EXTLDO ) AGND PGND(PAD) 16 Submit Documentation Feedback
Texas Instruments
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sirf atlas 3

TPS650702

Abstract: sirf iii c IO = 1 mA to 200 mA IO < 1 mA ; Vo < 1V ­1% ­1% ­1% ­2.5% 400 250 For TPS65072 For TPS65070, TPS65073 , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. TPS650701 , output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 , 1 mF Isink1 Isink2 THRESHOLD (EN_wLED) PGND4/PAD delay + Vref =1V Reset (EN_EXTLDO
Texas Instruments
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SiRF prima

Abstract: sirf atlas 4 for LDO1, LDO2 IO = 1 mA to 200 mA Load regulation for LDO1, LDO2 IO < 1 mA ; Vo < 1V RDIS , , TPS650732:Input for the reset comparator. RESET will be LOW if this voltage drops below 1V. EN_wLED , only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2.0] = 100 or , (EN_EXTLDO ) delay + Vref =1V AGND 16 Submit Documentation Feedback PGND(PAD) Copyright
Texas Instruments
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atlas 4 DC-DC21 L442
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