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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 33120A function/arbitrary waveform generator uses direct digital-synthesis techniques to create a , phase lock/TCXO timebase gives you the ability to generate synchronized phaseoffset signals. An external clock input/output lets you synchronize with up to three other HP 33120As or with an external , MHz 1 ms to 500 s ± 0.1% Single, External, or Internal Flatness (sinewave relative to 1 kHz , harmonic distortion DC to 20 kHz Phase noise 16,000 points 8 sec 8,192 points 4 sec 4,096 points 2.5 ... | Original |
4 pages, |
"waveform generator" AM MODULATion EN50082-1 1 uHz Sine Wave Generator hp function generator 34161A 5062-3972 squarewave generator MIL-461C pulse width modulation with ramp input HP 2400 heartbeat transducer datasheet abstract |
| Abstract: drive a three phase stepper This application note describes how to program the TMC453 TMC453 to output 3 , phase motors is not shown in the schematic, but it should be implemented to save energy and to reduce , phase motor directly drive the encoder inputs (CHA and CHB). This allows the encoder counter to count , velocity has to be reduced by the same factor. The target position is still driven by the ramp generator. AN453 AN453_5: Driving a 5 Phase Stepper motor with the TMC453 TMC453 This application note describes how to drive a 5 ... | Original |
8 pages, |
PID controller using OPAMP eprom 27c512 linear velocity formula ramp generator encoder 64 PIN PROCESSOR IC USING MOTOR DRIVE ramp generator quadrature encoder stepper motor pid disadvantages of microcontroller 8051 8051 stepper motor interfacing stepper motor and 8051 5-phase drive STEPPER MOTOR TMC453 AN453 TMC453 abstract |
| Abstract: also gives you fast rise- and fall-time square wave, and linear ramp waveforms down to 100 uHz. , capability The Option 001 phase lock/TCXO timebase gives you the ability to generate synchronized phase-offset signals. An external clock input/output lets you synchronize with up to three other 33120As or , 10 mHz - 15 MHz 1 ms to 500 s ± 0.1% ± 1% (0.1 dB) Trigger Single, External, or Internal , 12 bits (including sign) Non-volatile memory Direction 100 kHz to 1 MHz 8 to 16,000 ... | Original |
4 pages, |
UL1244 EN50082-1 33120A RS-232 RS-232 abstract |
| Abstract: functions with a single key press or two, then use a simple knob to adjust frequency, amplitude and , Optional phase-lock capability The Option 001 phase lock/TCXO timebase gives you the ability to generate synchronized phase-offset signals. An external clock input/output lets you synchronize with up to three , /octave Total harmonic distortion DC to 20 kHz , Speed Trigger Linear or Logarithmic Up or Down 10 mHz - 15 MHz 1 ms to 500 s ± 0.1% Single ... | Original |
4 pages, |
MIL-461C L4W 66 EN50082-1 33120A hp 33120a datasheet abstract |
| Abstract: using a single or dual external op amp. The device achieves bipolar operation using three additional , Unipolar 0V to 10V Outputs with a Single Op Amp Figure 3 shows the circuit for a 0V to 10V output range. , VREF. When the sign bit changes, the analog switch changes the reference input polarity to , bipolar zero error of 16 94dB SFDR Digital Sine Wave Generator Figure 9 shows the circuit diagram , unipolar mode with the reference bit inverted (ç'™REF) for the output range 0V to VREF. When the sign bit ... | Original |
6 pages, |
LTC1591 LTC1597-1 LTC1597 LT1112 LTC1236A-10 LTC1236 LT1468 Practical operation of dac specifications of 2N 1597 digital sine wave generator LTC1597 abstract |
| Abstract: line. Connect the VCO to the mismatched load, and vary the phase angle (between VCO and load) through , the load) of the incident voltage wave to the reflected wave ZL = load impedance Z0 = the , making appropriate changes to the internal IF bandwidth in each case. Oscillators with very low phase , , and -113dBc at 100kHz. A typical crystal oscillator, on the other hand, has 30dB to 40dB less phase , devices cannot compete because their noise corner is from two to three orders of magnitude greater than ... | Original |
9 pages, |
superheterodyne receiver GSM DCS1900 DCS1800 APP698 AN698 MAX2620 datasheet abstract |
| Abstract: accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single CMOS chip. Clock rates up to 50 MHz , can be used to generate a square wave from the sinusoidal DAC output. The DAC output should be , , is added to the phase accumulator output. The phase register to be used can be selected using the , fundamental frequency. Figure 5. Sine Wave Knowing that the phase of a sine wave is linear and given a , Oscillator + Phase Modulator SIN ROM Digital- to- Analog Convertor. Each of these sub-circuits are ... | Original |
20 pages, |
RU-20 EVAL-AD9834EB AD9834BRU ad9834 pin diagram AD9834 AD9834 abstract |
| Abstract: in today's competitive markets and the IM2000S IM2000S offers the ability to reduce all three. 3 , Clock Rate Internal Sine/Cosine Generator PWM Phase Current Control Minimal External Components , Clock select input. When low, the SCLK input will be directed to the internal sine/cosine generator , the EN input is low and, conversely, to the internal sine/cosine generator when the EN input is high. , Phase A and Phase B pulse width modulated output signals. These outputs can be used to control the phase ... | Original |
16 pages, |
LM234Z LMD18200 TLC372 VN0300 TLC271 ST L6203 Intelligent Motion Systems L6203 SGS L6203 IM2000S MICROSTEP l298 IR8200 L6203 im2000 sine cosine l298 IM2000S abstract |
| Abstract: proportional to the input amplitude as well as the phase difference between the input and the carrier. Because , phase, respectively. For simplicity, the input is shown as a sine wave of the same frequency as the , strapping pin 12 to 13. Doing so reduces device bandwidth and phase at unity gain to its lowest value and , amplifier, an absolute-value (precision rectifier) circuit or a phase detector applied to the device. To , If you should decide to use your own external feedback components, the sign and the gain magnitude ... | OCR Scan |
13 pages, |
HR1000 schaevitz HR lvdt Wien Bridge Oscillator sine 50 hz Wien Bridge Oscillator application b10k volume potentiometer lvdt sensor Wien Bridge Oscillator opamp Potentiometer b10k low distortion Wien Bridge Oscillator bridge transducer USING OP-AMP cookbook for ic 555 B10K AN-307 AN-307 abstract |
| Abstract: averaged output is proportional to the input amplitude as well as the phase difference between the input , bandwidth and phase at unity gain to its lowest value and reduces slew rate to 35V/^sec. With this pin open , (precision rectifier) circuit or a phase detector applied to the device. To understand the circuit operation , Ra ! â- lOOk «' Ra 10k PHASE TRIM AD630 AD630 _Ci S; O.Ol MF 10 Vref V Fig 7-To trim a carrier , wave, automatic gain control (AGC) is required to regulate the output amplitude. AGC is provided by ... | OCR Scan |
14 pages, |
HR1000 application of Wien Bridge Oscillator Wien Bridge Oscillator opamp sine wave generator using ic 555 Schaevitz Sensors hr 1000 Schaevitz Sensors AC bridge lvdt sensor precision rectifier Schaevitz lvdt controller AD630 Schaevitz lvdt AN-307 AN-307 abstract |
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| (fm) = single-sideband phase noise (in dBc/Hz) due to noise voltage modulating the VCO through the tuning line Hz. The external tank allows designers to optimize tuneability and single-sideband phase noise for a given ) varies with the voltage applied to its tuning port. Operating in a phase-locked loop (PLL), the VCO the VCO to the mismatched load, and vary the phase angle (between VCO and load) through 360° by load) of the incident voltage wave to the reflected wave Z L = load impedance Z 0 = the www.datasheetarchive.com/files/maxim/0008/view_048.htm |
Maxim | 04/04/2001 | 25.98 Kb | HTM | view_048.htm |
| . To use sensorless control, one phase must always be open. The motor has three windings, typically in multiplexer is used to combine the three zero-crossing signals into a single combined zero- crossing signal for the open phase. The microcontroller provides the three signals used to select the open phase. A single input capture function is then used to measure the zero-crossing time. Each motor phase has back-EMF selection logic is designed to combine the three zero-crossing signals into a single signal www.datasheetarchive.com/download/85023415-313978ZC/an1858sw.zip (AN1858.pdf) |
KyteLabs | 11/06/2002 | 444.92 Kb | ZIP | an1858sw.zip |
| - ence factor for the motor. It also obstructs rapid access to the generator voltage (EMF). Motors of coreless, bell armature or pancake de- sign are considerably less susceptible to winding inductance circuit with a DC tacho-generator yields a direct voltage that is proportional to speed, the circuit only one quadrant. For the same reason it is common practice to control the reference in a single few poles yield an adequate signal-to- noise margin. Three-pole motors with an AC component equal www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1656-v3.htm |
STMicroelectronics | 25/05/2000 | 23.41 Kb | HTM | 1656-v3.htm |
| is an interfer- ence factor for the motor. It also obstructs rapid access to the generator voltage (EMF). Motors of coreless, bell armature or pancake de- sign are considerably less susceptible to functions with a generator, the motor returning its own ki- netic energy and that of the load to the tachogenerator. However, only mo- tors with few poles yield an adequate signal-to- noise margin. Three special cases that demand a control error of zero - for example, when two drive shafts have to be phase www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1656.htm |
STMicroelectronics | 20/10/2000 | 24.08 Kb | HTM | 1656.htm |
| inductance is an interfer- ence factor for the motor. It also obstructs rapid access to the generator voltage (EMF). Motors of coreless, bell armature or pancake de- sign are considerably less susceptible to also functions with a generator, the motor returning its own ki- netic energy and that of the load to control circuit with a DC tacho-generator yields a direct voltage that is proportional to speed, the to a low speed or a lack of poles on the generator. However, multiple pole tachogenerators are ex www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1656-v1.htm |
STMicroelectronics | 02/04/1999 | 21.62 Kb | HTM | 1656-v1.htm |
| inductance is an interfer- ence factor for the motor. It also obstructs rapid access to the generator voltage (EMF). Motors of coreless, bell armature or pancake de- sign are considerably less susceptible to also functions with a generator, the motor returning its own ki- netic energy and that of the load to control circuit with a DC tacho-generator yields a direct voltage that is proportional to speed, the to a low speed or a lack of poles on the generator. However, multiple pole tachogenerators are ex www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1656-v2.htm |
STMicroelectronics | 14/06/1999 | 21.58 Kb | HTM | 1656-v2.htm |
| is to show how to perform the slip control of an AC three- phase induction motor with ST52x420, in the desired voltage level, the " Pulse generator " block generates three PWM signals to drive the The three pointers with 1200 phase shift give the values to be loaded in the PWMs PWM 0 PWM 1 used to drive the three legs of the bridge. The three-phase voltage is obtained by indexing 3 , in order to obtain three PWM signals. One single pointer is shifted on this table, synchronously www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7230-v1.htm |
STMicroelectronics | 18/07/2000 | 34.88 Kb | HTM | 7230-v1.htm |
| control of an AC three- phase induction motor with ST52x420, in order to obtain minimum input power and solution to reduce the rotor and stator copper losses. 1.1 Torque Characteristics of Asynchronous Three-Phase " Pulse generator " block generates three PWM signals to drive the inverter (refer to " Pulse of complex systems such as three-phase motors. Thanks to the three Timers and to the multiplication of the three PWM peripherals), are used to drive the three legs of the bridge. The three-phase www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7230.htm |
STMicroelectronics | 20/10/2000 | 36.62 Kb | HTM | 7230.htm |
| (not on past outputs) and it is easily constrained to produce a linear phase response. IIR filters can be unstable and produce a phase shift from input to output because past outputs as well as past visualized. The cascade form II network that corresponds to the above equation is: Single Stage, Two , 0001H 0001H 0001H 0001H is +0.00003051758 (1/32768), and FFFFH is -0.00003051758. A sine-wave signal generator was accomplishes that feat. Simply toggling the sign bit normalizes the A/D output to match the signed hexadecimal www.datasheetarchive.com/files/intel/design/mcs96/technote/2318-v7.htm |
Intel | 01/11/1998 | 24.53 Kb | HTM | 2318-v7.htm |
| (not on past outputs) and it is easily constrained to produce a linear phase response. IIR filters can be unstable and produce a phase shift from input to output because past outputs as well as past visualized. The cascade form II network that corresponds to the above equation is: Single Stage, Two , 0001H 0001H 0001H 0001H is +0.00003051758 (1/32768), and FFFFH is -0.00003051758. A sine-wave signal generator was accomplishes that feat. Simply toggling the sign bit normalizes the A/D output to match the signed hexadecimal www.datasheetarchive.com/files/intel/design/mcs96/technote/2318-v5.htm |
Intel | 30/04/1998 | 24.53 Kb | HTM | 2318-v5.htm |