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simulink model

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: point Simulink model of the MIL-STD 110A was the starting point for the SDR architecture. The 1,200 , performing complex Define Architecture - Start with existing floating point Simulink model - Design , . Design in DSP Builder blocks. 2. Get data from Simulink model. 3. Timing/detail design uses ModelSim , to the floating-point model. To correct errors, the designer updates the models in Simulink and , floating point Simulink model and output data to workspace Compare and analyze data in Simulink Altera
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VHDL code for floating point addition block interleaver in modelsim vhdl code for block interleaver simulink VHDL for implementing SDR on FPGA vhdl code for modulation MDR3125
Abstract: VHDL MATLAB Simulink Model Files M-Files FIR MAX+PLUS II Quartus impulse step random , ) MATLAB M (.m) Simulink Model (.mdl) Verilog HDL VHDL clock frequency s s s 12 , MATLAB/Simulink Model Files S-function FIR MAX+PLUS II FIR Compiler MATLAB Simulink , S-function ASCII FIR Compiler S _simulink.mdl Simulink Model File (.mdl) FIR Compiler Simulink Model File S-function .m .mdl.m Simulink Simulink Model File FIR Compiler FIR Altera
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qpsk simulink matlab 16 bit array multiplier VERILOG qam by simulink matlab FIR filter matlaB simulink design qpsk by simulink matlab QAM matlab
Abstract: Simulink Model & RTL" on page 25 Software Requirements This application note requires the following , directly in Simulink, you must update the model to reflect the variable settings: 1 Alternatively , name as the Simulink model file. 4. Configure the constraints on the design and select the device , ltera_wireless\ip\cfr\test\matlab\DSP Builder_\.salt. , \matlab\tb_.vhd. 11. Open tb_.tcl. 12. Replace the following Altera
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wireless power transfer matlab simulink wcdma simulink vhdl code for cordic CORDIC vhdl altera Crest factor reduction verilog code for histogram AN-396-1
Abstract: Bit-true Simulink model and MATLAB programs included Instantiation Template · Uses relationally , Bit-True Simulink Model; MATLAB Analysis programs Design Tool Requirements Xilinx Implementation , description of the analytical measures of performance and a description of the bit-true Simulink model , device and mirrors the architecture of the bit-true Simulink model. The code has embedded relative Xilinx
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DS210 BPSK modulation VHDL CODE vhdl code for bpsk modulation 16 bit qpsk VHDL CODE hardware implementation of bpsk bpsk simulink matlab QPSK using xilinx XIP2229
Abstract: (HDL) code from a system representation model in Simulink. The HDL design can then be synthesized for , development time by quickly iterating between the system-level model in Simulink and the hardware , translation software converts the Simulink model into synthesizable VHDL, with Xilinx FPGA hardware as the , activates the translation software that converts a Simulink model built from XBS elements into synthesizable , useful during design and debugging. Simulink You can model a VHDL design using any combination of Xilinx
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Abstract: .14 Model Your System Using MATLAB Simulink .18 Add the NCO Compiler Model to Your Simulink Model , . 4. Incorporate the NCO Compiler wizard-generated Simulink model files into your system model , your design. Model Your System Using MATLAB Simulink The MATLAB software performs complex , Browser opens. 4. Create a new model by clicking the page icon in the Simulink Library Browser or Altera
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FSK modulate by matlab book adpll.mdl QAM verilog simulink 16QAM 16 QAM modulation matlab vhdl program for cordic cosine and sine
Abstract: .49 Model Your System Using MATLAB Simulink , Drop the FIR Compiler Models into Your Simulink Model .59 Implement the , bittrue models) in the Verilog HDL and VHDL languages, and for the MATLAB environment (Simulink Model , , including MAX+PLUS II Vector Files (.vec), MATLAB M-Files (.m), Simulink Model Files (.mdl), Verilog HDL , . ModelSim is a trademark of Model Technologies. MATLAB is a registered trademark of the MathWorks Altera
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digital FIR Filter verilog code FIR filter matlaB design verilog code for decimation filter verilog code for interpolation filter digital FIR Filter VHDL code FIR Filter matlab
Abstract: bit-true models) in the Verilog HDL and VHDL languages, and for the MATLAB environment (Simulink Model , . Drag and drop the FIR compiler wizard-generated Simulink model files your system model. 5 , products or services mentioned in this document, including the following: MATLAB and Simulink are , Simulink models, and vector files. Once you license the function, you can use the MAX+PLUS II or Quartus , architectural (area/speed) tradeoffs, and generates MATLAB Simulink, Verilog HDL, and VHDL models. Does the Altera
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FIR FILTER implementation in c language verilog code for fir filter verilog code for fixed point adder 16 QAM modulation verilog code vhdl code hamming FIR Filter verilog code
Abstract: Simulink model. System Generator also supports automatic translation of a hardware-centric subset of the , Simulink to FPGA Xilinx FPGAs have become the preferred choice for many highperformance, programmable , is a software platform that uses Simulink to represent a high-performance DSP designs to Xilinx FPGAs, directly from the familiar MATLAB®/Simulink® environment of The MathWorks. Using this platform , architecture to suit your DSP algorithm. Model and Implement High-Performance DSP Systems · Create multi-rate Xilinx
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on Costas Loop on FPGA wavelet transform simulink 16 qam demodulator vhdl code for qam xilinx vhdl code project simulink
Abstract: Model in Simulink" on page 15-Analyze the DSP Builder-generated models and simulate the filtering , select the file filter_design.mdl (.mdl is a Simulink Model File). 4. Review the Simulink design , Corporation Exercise 2: Simulate the Model in Simulink Exercise 2: Simulate the Model in Simulink To simulate the model in the Simulink software, follow these steps: 1. Choose Configuration , Switch to the MATLAB window. Altera Corporation Exercise 2: Simulate the Model in Simulink 7 Altera
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Filter Noise matlab 1S25 MegaCore FIR matlaB Frequency multiplier 1mHz 10MHz FIR filter matlaB design altera
Abstract: Simulating the Model in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Simulink Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 4­3 Placing the MegaCore Function in the Simulink Model . . . . . . . . , . . . . . . . . 4­4 Creating a New Simulink Model . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . 8­2 Simulating the HDL Import Model using Simulink . . . . . . . . . Altera
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real time simulink wireless vhdl projects abstract and coding EP2C35F672C6 vhdl code to generate sine wave verilog code pipeline square root verilog code for twiddle factor ROM
Abstract: motor (plant), the control feedback circuits, and the digital controller. The plant model uses Simulink , models in the Simulink model and being hand coded in the application project. This approach is , CODE Simulink provides toolboxes such as Simscape and SimMechanics that can be used to easily model , before building and testing physical hardware. The latest simulation tools from MathWorks can model , designer to expand from more classical design schemes and move directly from model creation to simulation Analog Devices
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TA13139-0-4/15
Abstract: . 22 Simulink Model of Hydraulic Actuator . 23 Simulink Model of Servo-Valve , Simulink model of the servo-valve is shown in Appendix A. The inputs are command voltage from the , use of Simulink to model and design the system allows enhancements such as this to be easily added to , Figure A-2. Simulink Model of Hydraulic Actuator SPRAA76 ­ January 2005 Simulink Models 23 Texas Instruments
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Hydraulic Oil bulk modulus MOOG SERVO VALVE servo motors moog MILL MAX HYDRAULIC OIL 32 simulink moog tms320f2812 simulink TMS320C28 C2000
Abstract: following steps to create a model in Simulink and simulate. 1. Choose New > Model (File menu) in the , scope. Figure 9 shows the completed model. Figure 9. Simulink Model 25. Choose Simulation , represented by Out1 in the Simulink model. Frequency Response is the title of the plot. 4e7 is the sampling , . Exercise 3-In this exercise you will use the MATLAB and Simulink software to view the Altera-generated , edition or a purchased version) MATLAB version 6.0 or higher Simulink version 4.0 or higher 1 This Altera
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filter matlaB software design 200E EPC16 40-MH RS-232
Abstract: floatingpoint Simulink model. If help is needed with this step, refer to the appropriate Mathworks , Prerequisites 2 Model Examples 2 2 Task 1: Create the FIR Filter 3 Task 2: Create a Subsystem 6 , design in Simulink and converting it to a fixed-point design using the Lattice ispLeverDSP blockset for MATLAB/Simulink. Inexperienced users of Lattice ispLeverDSP blockset for MATLAB/Simulink are advised to , floating-point design in Simulink that achieves the desired system performance criteria. Create a testbench to -
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fixed point fir filter on matlab Design Filter using simulink in matlab fixed point matlab code ISPVM FIR filter matlaB design code matlab simulink
Abstract: Storage Logic Cells 3. Exercise 2: Simulate the Model in Simulink Click Cancel to exit IP , ',10e7) 12 Altera Corporation Exercise 2: Simulate the Model in Simulink where: · · · , SignalTap II block in the Simulink model Frequency Response - Unfiltered Data is the title of the plot , "Exercise 2: Simulate the Model in Simulink" on page 11. The hardware results match the Simulink simulation , system-level DSP tool Simulink with the Altera Quartus® II development software. DSP Builder provides a Altera
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AN320 EP2S60 800-EPLD
Abstract: model into hardware, the same vectors used in the Simulink simulation are used as golden test vectors , Simulink model to pass the mapped address to the OPB Export Tool. x264_08_111402 Figure 8: Mask , existing Simulink libraries can be used in the peripheral debugging process. When the model is translated , System Generator Simulink model · A more complex System Generator model called OPB_2D_FILTER. This , the OPB Export Tool, re-open the Simulink model and click on the System Generator dialog box. Select Xilinx
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XAPP264 verilog code for fir filter using DA xilinx uart verilog code vhdl code for rs232 fir Future scope of UART using Verilog signal path designer ChipScope
Abstract: initial state upon reset Bit-true Simulink model and MATLAB programs included VHDL Source Code Xilinx
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matlab code for turbo product code Turbo decoder Xilinx DO-DI-AWGN xilinx silicon device
Abstract: . With Matlab open, you can create a new Simulink model, and the Synplify DSP library should be showing , , compared to the Simulink model of the DSP design. Currently Matlab and Simulink (including Synplify DSP , Introduction This Quickstart and tutorial assumes that you already have the Mathworks Matlab®/Simulink , information. Synplify DSP requires the installation of Matlab/Simulink and can only be launched from the Matlab/Simulink tools. Synplify DSP AE (Actel Edition) Software and License Availability Synplicity Actel
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A3PE1500-PQ208 341a
Abstract: implementation model using Simulink/Matlab and Altera DSP Builder blocks. 0 -1 0 -1 -2 -2 -3 -3 , block diagram of the Matlab/Simulink model. The input/output black color blocks belong to the , predistorter has two inputs/ outputs. Figure 5. Matlab/Simulink and Altera DSP Builder model of 16-QAM data , using an Altera digital signal processing (DSP) board. The implementation uses Matlab/Simulink, Altera , the Matlab/Simulink environment. It is then converted to VHDL level using the signal compiler in the -
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m-qam modulation Kingston CF 16QAM modulation 16 QAM 16QAM predistorter EP1S80
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