NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: operational for normal Serial Bus arbitration, but otherwise capable of detecting both a physical cable , the idle bus time consumed by the subaction gap and the arbitration reset gap. 2001 May 14 3 , arbitration This allows a node that is transmitting asynchronous packets to arbitrate for the bus more than , configured to neither transmit, receive, nor repeat Serial Bus signals. There are two ways to disable a , set to a 1 when the arbitration controller times-out during tree-ID, which may indicate the bus is ... | Original |
16 pages, |
TSB41AB LQFP64 LQFP80 P11A PDI1394P11A PDI1394P21 PDI1394P22 PDI1394P23 PDI1394P25 IEEE 1394a AN2455 PDI1394P11A abstract |
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| Abstract: operational for normal Serial Bus arbitration, but otherwise capable of detecting both a physical cable , the idle bus time consumed by the subaction gap and the arbitration reset gap. 2001 May 14 3 , arbitration This allows a node that is transmitting asynchronous packets to arbitrate for the bus more than , configured to neither transmit, receive, nor repeat Serial Bus signals. There are two ways to disable a , set to a 1 when the arbitration controller times-out during tree-ID, which may indicate the bus is ... | Original |
16 pages, |
PDI1394P25 PDI1394P23 PDI1394P22 PDI1394P21 PDI1394P11A P11A LQFP80 LQFP64 fw802 AN2455 PDI1394P11A abstract |
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| Abstract: 45K22 1.2.1 PCI Express* Interface (Primary Bus) .15 1.2.2 PCI/PCI-X Bus Interfaces (Secondary Bus , * PCI/PCI-X Bus Interface .20 PCI Bus Interface 64-bit Extension , . 49 2.12.4 Serial Mode ... | Original |
194 pages, |
RWS - 371-6 M66EN 6700PXH 6700PXH abstract |
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| Abstract: str TV SMPS enabled, 6 slots (serial mode) HPA_PRST# O Primary Bus Reset Out (HPA_PRST#): This is asserted , 1.2.1 PCI Express* Interface (Primary Bus) .12 1.2.2 PCI/PCI-X Bus Interfaces (Secondary Bus , * PCI/PCI-X Bus Interface .16 PCI Bus Interface 64-bit Extension ... | Original |
214 pages, |
M66EN 6702PXH 6700PXH RWS - 371-6 74x165 6702PXH abstract |
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| Abstract: Bus Mode Selection : I C or Synchronous Bus Serial Port Enable : When disabled , SCK and SDO are kept , SERIAL PERIPHERAL INTERFACE ST9+ TRAINING / SPI / 1 SPI Main Features Serial Interface , ) FULL DUPLEX 3 wires SYNCHRONOUS TRANSFER SDI : Serial Data In SDO : Serial Data Out SCK : Serial , , 1 SPR0 CPHA 0 SCK 0 1 0 SCK 1 1 IM BUS SCK 1 Speed 1.5MHz 750kHz 93.75kHz 46.87kHz SCK I2C BUS Internal read strobe SDI : SDO MSB 6 5 4 3 ... | Original |
8 pages, |
spr1 sbus protocols datasheet abstract |
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| Abstract: VMEbus arbitration, power-up reset, system and serial bus clocks and bus time-out logic. The utility , speeds, while providing seven interrupt levels and four levels of bus priority arbitration. VERSAdos , M68000 M68000 processing power, Eurocard mechanical format, VME(bus) system versatility, powerful , Controllers VME Slot 1 System Controller Module providing round-robin and priority VMEbus arbitration, power-up reset, system clock and bus time-out logic. The board is designed to be used with MVME120 MVME120 series ... | OCR Scan |
1 pages, |
MVME701 MVME120 MVME050 motorola mc68000 MC68000 M68000 MVME025 M68000 abstract |
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| Abstract: I2C Master/Slave Bus Controller Core The I2C core implements a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic , I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is , provides a serial interface that meets the Philips I2C bus specification v.2.1, compliant with PVCI , provides the I2C slave serial interface that meets the Philips I2C bus specification and supports slave ... | Original |
2 pages, |
I2c core implementation I2C CODE OF READ IN V HDL 80C552 i2c 80C552 "programmable clock" i2c datasheet abstract |
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| Abstract: 16 kbytes DSP core Memory management unit (MMU) Cache memory 16 kbytes CPU bus (I clock) Bus state controller Direct memory access controller (DMAC) Interrupt controller (INTC) Internal bus (B clock) Serial/ smart card (SCI0) Hitachi user debug interface , generator (CPG) Internal bus 2 (B clock) Serial communication interface (SCIF) Timer (TMU) A , clock) Peripheral bus (P clock) Arbitration Peripheral bus 2 (P clock) 512-byte SRAM Li ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: peripherals fit into a single FPGA. Block Diagram Features iW-86 CPU Core with Bus Interface Unit Bus Arbitration Unit Wait Control Unit Multi Protocol Serial Controller similar to 8530 Programmable Timer similar to 8254 PCI Target Controller with on-chip memory Peripheral / Memory Bus Interface CPU on-chip peripherals Programmable 16-bit Timer similar to 8254 Serial Controller Unit similar to 8251 Interrupt , Timer - 8254 Interrupt Controller - 8259 DMA Controller - 8237 Serial Controller - 8251 ... | Original |
1 pages, |
a3pe1500 interfacing chip 8251 8251 timer 8254 8251 DMA controller USART 8251 interfacing with RS-232 interrupt controller verilog interrupt controller verilog code verilog code for 8251 8259 Programmable Peripheral Interface block diagram 8251 USART 8251 interfacing datasheet abstract |
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| Abstract: as the bus master. The interface requires an external arbitration logic to handle the necessary hand , memory. S然MIT DMA Arbitration The process of the S然MIT assuming control of the bus while another master , S然MIT asserts DMAR when it needs to control the bus. This signal is routed to the arbitration circuit , S然MIT provides the system designer with an intelligent solution to MIL-STD-1553 MIL-STD-1553 multiplexed serial data bus design problems. The S然MIT is a singlechip device that implements all three of the defined ... | Original |
3 pages, |
UT69151 UT22VP10 80C86 MIL-STD-1553 80C86 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| CPHA SPR1 SPR0 DATA BUS INTCLK Serial Peripheral Control Register R253 INT2 SDO SDI SCK/INT2 1 0 INT2 ST9+ SERIAL PERIPHERAL INTERFACE ST9+ TRAINING / SPI / 1 ® ST9+ SPI Main Features Serial DUPLEX 3 wires SYNCHRONOUS TRANSFER SDI : Serial Data In SDO : Serial Data Out SCK : Serial Clock Four INT2) : EOT (End of Transmission) I2C/S-BUS start or stop Condition Master mode only (ST9 generates BUS I2C BUS 0, 0 0, 1 1, 0 1, 1 1.5MHz 750kHz 93.75kHz 46.87kHz ST9+ TRAINING / SPI / 4 ® ST9+ SPI www.datasheetarchive.com/download/57358569-845302ZC/12_spipr.zip (12_spipr.pdf) |
STMicroelectronics | 20/10/2000 | 21.96 Kb | ZIP | 12_spipr.zip |
| 1394 High-Performance Serial Bus >> Semiconductor 1394 High-Performance Serial Bus TSB14C01A TSB14C01A TSB14C01A TSB14C01A Product Description The TSB14C01A TSB14C01A TSB14C01A TSB14C01A is a 5V, one Performance Serial Bus Standard. The TSB14C01A TSB14C01A TSB14C01A TSB14C01A is not designed to drive the backplane directly, so this . Target Applications: Backplane Environments The 1394 BackPlane Serial Bus (BPSB) plays a : Monitoring of peripherals (disk drives, fans, power supplies, etc. in conjunction with 1394 cable serial bus www.datasheetarchive.com/files/texas-instruments/data/www.ti.com/sc/docs/products/msp/intrface/serdes/1394/14c01a.htm |
Texas Instruments | 29/01/2000 | 9.2 Kb | HTM | 14c01a.htm |
| 1394 Serial Bus TSB14C01A TSB14C01A TSB14C01A TSB14C01A Product Page 1394 Designer's Kits 1394 Serial Bus Devices TSB14C01A TSB14C01A TSB14C01A TSB14C01A functions, as specified by the IEEE-1394-1995 IEEE-1394-1995 IEEE-1394-1995 IEEE-1394-1995 High Performance Serial Bus Standard. The TSB14C01A TSB14C01A TSB14C01A TSB14C01A is Backplane Environments The 1394 BackPlane Serial Bus (BPSB) plays a supportive role in backplane bus peripherals (disk drives, fans, power supplies, etc. in conjunction with 1394 cable serial bus. TINY AREA www.datasheetarchive.com/files/texas-instruments/data/sc/docs/msp/1394/14c01.htm |
Texas Instruments | 08/02/1999 | 4.95 Kb | HTM | 14c01.htm |
| 1394 High-Performance Serial Bus >> Semiconductor 1394 High-Performance Serial Bus TSB14C01A TSB14C01A TSB14C01A TSB14C01A Product Description The TSB14C01A TSB14C01A TSB14C01A TSB14C01A is a 5V, one Performance Serial Bus Standard. The TSB14C01A TSB14C01A TSB14C01A TSB14C01A is not designed to drive the backplane directly, so this . Target Applications: Backplane Environments The 1394 BackPlane Serial Bus (BPSB) plays a : Monitoring of peripherals (disk drives, fans, power supplies, etc. in conjunction with 1394 cable serial bus www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/products/msp/intrface/serdes/1394/14c01a.htm |
Texas Instruments | 28/01/2000 | 9.2 Kb | HTM | 14c01a.htm |
| PCI Bus Features - 1394 Firewire, TSB11C01 TSB11C01 TSB11C01 TSB11C01 & TSB12C01A TSB12C01A TSB12C01A TSB12C01A PCI Bus Features 1394 FIREWIRE High speed, low-cost serial bus that provides a straight . The 1394 serial bus includes daisy chaining and branching capabilities for up to 63 devices 200/100 Megabits per second. Logic performs system bus initialization and arbitration 1394 High-Speed Bus Standard. Supports data rates of 100, 200, and 400 Mb/s. Provides for "live www.datasheetarchive.com/files/texas-instruments/sc/docs/msp/1394/pcibus4.htm |
Texas Instruments | 11/02/1997 | 5.59 Kb | HTM | pcibus4.htm |
| PCI Bus Features - 1394 Firewire, TSB11C01 TSB11C01 TSB11C01 TSB11C01 & TSB12C01A TSB12C01A TSB12C01A TSB12C01A PCI Bus Features 1394 FIREWIRE High speed, low-cost serial bus that provides a straight . The 1394 serial bus includes daisy chaining and branching capabilities for up to 63 devices 200/100 Megabits per second. Logic performs system bus initialization and arbitration 1394 High-Speed Bus Standard. Supports data rates of 100, 200, and 400 Mb/s. Provides for "live www.datasheetarchive.com/files/texas-instruments/sc/docs/apps/computer/techapp/pcibus4.htm |
Texas Instruments | 15/11/1996 | 5.11 Kb | HTM | pcibus4.htm |
| 130Mbytes/sec throughput from one PCI bus to another PCI bus Supports two 32-bit, 33MHz buses Provides internal arbitration for up to SIX secondary bus masters with programmable control Provides SIX secondary PCI bus clock ouputs Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Provides a high-performance connection path between two 32-bit, 33MHz PCI buses. Package Supports four general purpose I/O's on the primary and secondary side External Arbiter Option Serial www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/msp/pci/pci2031.htm |
Texas Instruments | 17/01/2000 | 7.23 Kb | HTM | pci2031.htm |
| 130Mbytes/sec throughput from one PCI bus to another PCI bus Supports two 32-bit, 33MHz buses Provides internal arbitration for up to SIX secondary bus masters with programmable control Provides SIX secondary PCI bus clock ouputs Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Provides a high-performance connection path between two 32-bit, 33MHz PCI buses. Package Supports four general purpose I/O's on the primary and secondary side External Arbiter Option Serial www.datasheetarchive.com/files/texas-instruments/data/www.ti.com/sc/docs/msp/pci/pci2031.htm |
Texas Instruments | 18/01/2000 | 7.23 Kb | HTM | pci2031.htm |
| CPHA SPR1 SPR0 DATA BUS INTCLK Serial Peripheral Control Register R253 INT2 SDO SDI SCK/INT2 1 0 INT2 ST9+ SERIAL PERIPHERAL INTERFACE ST9+ TRAINING / SPI / 1 ® ST9+ SPI Main Features Serial DUPLEX 3 wires SYNCHRONOUS TRANSFER SDI : Serial Data In SDO : Serial Data Out SCK : Serial Clock Four INT2) : EOT (End of Transmission) I2C/S-BUS start or stop Condition Master mode only (ST9 generates BUS I2C BUS 0, 0 0, 1 1, 0 1, 1 1.5MHz 750kHz 93.75kHz 46.87kHz ST9+ TRAINING / SPI / 4 ® ST9+ SPI www.datasheetarchive.com/download/52976966-844721ZC/12_spipr-v1.zip (12_spipr.pdf) |
STMicroelectronics | 19/08/1998 | 21.96 Kb | ZIP | 12_spipr-v1.zip |
| /sec throughput from one PCI bus to another PCI bus Supports two 32-bit, 33MHz buses Provides internal arbitration for up to SIX secondary bus masters with programmable control Provides SIX secondary PCI bus clock ouputs Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Provides two Provides a high-performance connetion path between two two 32-bit, 33MHz PCI buses four general purpose I/O's on the primary and secondary side External Arbiter Option Serial IRQ www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/msp/pci/pci2030.htm |
Texas Instruments | 28/01/2000 | 7.22 Kb | HTM | pci2030.htm |