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Catalog Datasheet MFG & Type PDF Document Tags
Abstract: SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:15] SDRAM_DQM[0:1] DATA1 DATA2 3 0 3 SDRAM_CSn , ) SDRAM_Addr[0:12] 1FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] SDRAM_DQM[0:3] 000000D0 F , ) 1FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM[0:1] 3 0 SDRAM_DQ[0:15] D0D1 D2D3 , BA(A0) RA(A0) CA(A0) 1FFF SDRAM_Addr[0:12] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM[0:3 , 1FFF RA(A0)CA(A0) 1FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM[0:3] SDRAM_DQ[0:31] 0 Xilinx
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000000A5 sdram controller baa0 DRAM controller memory FPGA Spartan-IITM 200 vhdl code for DCM DS426J 100MH CR204161 CR208644
Abstract: access SDRAM. This is a pre-publication draft. This application note will run through all aspects of the DragonBall VZ operation that relates to SDRAM. 1 Introduction . . . . . . . . . . . . . . . . . . . . . , SDRAM0 BS0 BS1 A14 Figure 1. Pin Connection from VZ to SDRAM The above configuration was , 3.1.2 for details on using 32MByte SDRAM. 2.1 Address Lines One of the trickier steps in , Bank Select and maybe labeled as such. These configurations apply to both 8-bit and 16-bit SDRAM. Motorola
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MC68VZ328 AN2148 FFF106 FFF116 AN2148/D
Abstract: configured for SDRAM. Connect to SDRAM's CS (chip select) pin. RAS I/O/Z SDRAM Row Address Select , 's SDRAM controller provides a glueless interface with standard SDRAMs and supports: · 16M, 64M, and 128M , . · A programmable refresh counter to coordinate between varying clock frequencies and the SDRAM's required refresh rate. · Buffering for multiple SDRAMs connected in parallel. · Shared SDRAM devices in a , Description CAS I/O/Z SDRAM Column Address Select pin. Connect to SDRAM's CAS buffer pin. DQM Analog Devices
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ADSP-21065L sdcl pin diagram for core i3 processor i3 processor sdram dram ADDR23-0 07LPLQJ6SHFLILFDWLRQV
Abstract: should always be set in the SDRAM's mode register before using the SDRAM. The DragonBall VZ supports CAS , note provided information to setup and use the DragonBall VZ to access SDRAM. This application note discusses all aspects of the DragonBall VZ operation as it relates to the SDRAM. 1 Introduction This , 16-Bit) SDRAM PB5/CSD1/CAS1/SDCS1 CS SDRAM1 64 Mbit (4Meg x 16-Bit) SDRAM PB4/CSD0/CAS0 , on page 5 for details on using 32 Mbyte SDRAM. 2.1 Address Lines One of the more intricate steps Freescale Semiconductor
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A111 MC68VZ328UM/D
Abstract: latency of a SDRAM should always be set in the SDRAM's mode register before using the SDRAM. The , DragonBall VZ to access SDRAM. This application note discusses all aspects of the DragonBall VZ operation as it relates to the SDRAM. 1 Introduction This application note provides information to users who , 64 Mbit (4Meg x 16-Bit) SDRAM PB5/CSD1/CAS1/SDCS1 CS SDRAM1 64 Mbit (4Meg x 16-Bit) SDRAM , on page 5 for details on using 32 Mbyte SDRAM. 2.1 Address Lines One of the more intricate steps Freescale Semiconductor
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Abstract: [bankaddwidth:0] Bank address for DDR2 SDRAM. There is a variable through which the bank address is selectable , write to DDR2 SDRAM. No new command should be given to the controller until this signal is deasserted , is given to DDR2 SDRAM. Note: The output clock and reset signals can be used for data , Application Note: Spartan-3 FPGAs R XAPP454 (v1.1.1) June 11, 2007 DDR2 SDRAM Memory , a DDR2 SDRAM memory interface implementation in a SpartanTM-3 device, interfacing with a Micron Xilinx
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XAPP768 MT47H16M16FG-37E MT47H16M16FG XAPP768c interface ddr2 sdram with spartan3 MT47H16M16FG-37E IT
Abstract: ) supports a glueless interface to high-density and high-speed SDRAMs. Both 64-Mbit and 128-Mbit SDRAMs are , signals and the necessary signal connections between the DSP and various types of SDRAM. EMIF register , application with SDRAM. Contents 1 2 C55x SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . , (EMIF) supports a glueless interface to high density and high speed SDRAMs. Both 64-Mbit and 128 , . CLKMEM O/Z Memory interface clock for SDRAM. Placed in high impedance in hold mode. 2 C55x Texas Instruments
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SPRA719 C5000 MT48LC2M32B2 0x0812 8MB SDRAM COL10 HY57V653220B TMS320C55 128-M
Abstract: Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM , memory chips in addition to SDRAM. The SDRAM controller core with Avalon interface is SOPC , refresh the SDRAM. f See the Avalon Memory-Mapped Interface Specification for details about , . The SDRAM controller permanently asserts the CKE signal on the SDRAM. Sharing Pins with Other , SDRAM's row open time limit. Hardware Design and Target FPGA The target FPGA affects the maximum Altera
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NII51005-7 d4564163-a80 MT48LC4M32B2-7 d4564163 NEC D4564163-A80 d456 SDR100 PC100
Abstract: SDRAM_TIMING2. 11. Load register SDRAM_WIDTH to set the desired width of the SDRAM interface. 12. Delay for , register SDRAM_REFRESH to set the refresh period parameter RFSH. 8. Load register SDRAM_ADDR to set , setting the load mode register bit, LM, of SDRAM_INIT. The SDRAM's mode register is loaded with the , SDRAM_ADDR to set the number of row and column address bits. 9. Load register SDRAM_MODE0 to set the , SDRAM_MODE0 must be set in order to reset the DLL. 10. Load register SDRAM_MODE1 to set the extended mode Altera
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AN141 sdr sdram pcb layout guidelines sdr sdram pcb layout ldr resistor excalibur Board EPXA10 ARM922TTM 800-EPLD
Abstract: Au1x00 processor supports three ranks of 32-bit wide SDRAM. A rank is a physical grouping of SDRAM , processor is capable of saturating the SDRAM interface on both reads and writes from/to the SDRAM. Thus , from memory, and ultimately the throughput to the SDRAM. In the examples that follow, a 99-MHz SDRAM , determines the number of cycles until data can be read from the SDRAM. The CAS latency varies depending upon , / 10) = 237.6MB/s Utilizing CAS 3 SDRAM reduces throughput by 11.3MB/s relative to the CAS 2 SDRAM. Advanced Micro Devices
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48LC4M32B2TG-7 48lc4m16a2 48LC8M16A2 48LC4M32B2 48lc4m16a2-75 48LC8M16A2-75 AU1100 1000TM 1100TM 1500TM 00549AA9 560009EF
Abstract: SDRAMDoubule Data Rate Synchronous DRAM SDRAMDDR SDRAM SDRAM SDR SDRAMSingle Data Rate Synchronous DRAM 2 , .36 3-7 DDR SDRAMSDR SDRAMEDO DRAM , DDR SDRAMSDR SDRAMEDO DRAM .37 7-1 , SDRAMSDR SDRAM DDR SDRAM SDR SDRAM 2 2/tCK 1/tCK SSTL , SDRAM SDR SDRAM 1-3 DDR SDRAMSDR SDRAM DDR SDRAM SDR SDRAM × × Elpida Memory
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J0234E50 J0123N ELPIDA DDR User J0234E sdram elpida J0123N ELPIDA SDRAM J0123N CMJ0107 M01J0706
Abstract: allowing six banks of SDRAM. Please refer to the section, Signal Loading Issues and Buffer Requirements , # corresponding to the bank with size 0 will not be generated for SDRAM. PCIDV0 4Dh Default = 00h , 7-1-1-15-1-1-1-1 2 SDRAM Density Register 2 If SDRAMbased system, this bit must be written to 1. 0 = , synchronous DRAM (SDRAM). The purpose of this document is to assist the motherboard designer in implementing a system that will use synchronous DRAM. Supported SDRAM Features and Signals The 82C579 uses OPTi
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pin details of VIPER 22 SDRAM DIMM 1997 82C576 opti chipset SDRAM 1997 VIPer 32
Abstract: EMIF, including timing analysis. In addition, specific examples are provided using Micron SDRAM. , EMIF, EA12 maps directly to A10 on the SDRAM. The C621x/C671x EMIF does not use the SDA10 signal, as , of SDRAM. These can be in different CE spaces, all in a single CE space, or any combination of the , of SDRAM. These can be in different CE spaces, all in a single CE space, or any combination of the , C621x/C671x EMIF offers the capability to interface to 32-bit, 16-bit, and 8-bit SDRAM. Depending on Texas Instruments
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SPRA433E TMS320C6000 C6000 BSBE MT48LC4M16A2-10 EA11-EA1 EA16-EA15 EMIF SDRAM
Abstract: a SDRAM should always be set in the SDRAM's mode register before using the SDRAM. The DragonBall VZ , the DragonBall VZ to access SDRAM. This application note discusses all aspects of the DragonBall VZ operation as it relates to the SDRAM. 1 Introduction This application note provides information to users , VCC MC68VZ328 64 Mbit (4Meg x 16-Bit) SDRAM PB5/CSD1/CAS1/SDCS1 CS SDRAM1 64 Mbit (4Meg , (CSD) and Chip-Select Control Register 1 (CSCTRL1)" on page 5 for details on using 32 Mbyte SDRAM. Motorola
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ECD18
Abstract: SDRAM0MASK = 0xFC00_0000 64MB SDRAM1BASE = 0x0400_0000 SDRAM1MASK = 0xFC00_0000 64MB Note: The , SDRAM chips). SDRAMC.DTYPE = 64Mbit SDRAM (because the SODIMM is composed of eight 2Mbx8x4 SDRAM chips). SDRAMC.SOD = 1 (enable SODIMM mode). Other SDRAM fields, such as CL, RCD, RP, and RC should be , system loading requirements that should be followed when designing an SDRAM-based memory subsystem , SDRAM controller provides a glueless interface to industry standard SDRAMs and SDRAM SODIMMs. The SDRAM Integrated Device Technology
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AN-440 79EB355 RC32351 RC32355 8MBX32 RC32355/RC32351 79EB351 AN-382 256KB
Abstract: standard SDRAMS. 2 Overview of the i.MX SDRAM Controller The i.MX is an application processor , standard pinout/operation · Supports Micron's SyncFlash SDRAM-interface burst flash memory - Boot , SDRAMs, that the user choose the linear bank addressing mode of operation. 2.1.3 SDRAM Controller , SDRAM Controller MC9328MX1, MC9328MXL, and MC9328MXS By: Michael Kjar 1 Introduction This , processors interface to different configurations of SDRAM memory devices and how to initialize these Freescale Semiconductor
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AN2478 4Mx16x M110 MC9328MXLRM MC9328MX1RM controller for sdram
Abstract: SDRAM_BankAddr BankAddr Command State Machine SDRAM_Addr SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_CSn , SDRAM_DQ_i SDRAM I P12 SDRAM_DQ_t SDRAM O P13 SDRAM_Clk_in SDRAM I SDRAM , SDRAM_DQ_o Write_dqs_en, Write_data_mask SDRAM_DQ_t Read_data SDRAM_DQ_i IPIF Interface , Description P1 SDRAM_Clk SDRAM O 0 SDRAM Clock P2 SDRAM_CKE SDRAM O 0 , SDRAM_WEn SDRAM O 1 Active low SDRAM write enable P7 SDRAM_DQM SDRAM O 0 SDRAM Xilinx
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DS427 vhdl code for sdram controller DS426 XAPP132
Abstract: . 3 Choosing the appropriate , (SDRCON_PIPE1). · PAGE BOUNDARY. These bits define the page size, in number of words, of the SDRAM's banks , Lite), there are only two SDRAMs where no buffering of the signals is needed (SDRAM Therefore , : This meets the power-up timing specifications of the selected SDRAM. Therefore, this bit should , , the user can safely start accessing the SDRAM. The ADSP-BF533 Processor On-Chip Controller Analog Devices
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EE-210 ADSP-TS201S ADSP-TS201 ADSP-21161N BF533 ADSP-TS203S ADSP-TS203 ADSP-TS202 ADSP-BF531/ADSP-BF532/ADSP-BF533 MT48LC4M32B2 MT48LC16M16B2
Abstract: , low noise 1 - 1 8 non inverting buffer designed for SDRAM clock buffer applications. Out of the 18 outputs 16 may be used to drive up to four SDRAM DIMMs, and the remain ing two can be used for external , ] SDRAM 15 44 ] SDRAM 14 43 ] GND 42 3 VDd 41 ] SDRAM 13 40 ] SDRAM 12 39 3 GND 38 ] O E 37 ] v dd 38 3 SDRAM 11 35 3 SDRAM 10 34 ] GND 33 3 Vdd 32 3 SDRAM 9 31 3 SDRAM 8 30 ] GND 29 3 Vdd 28 3 SDRAM 17 27 ] GND 26 ] GND|2c 25 3 SCLK SDRAM 0 C 4 SDRAM 1 C 5 GND C 6 Vdd C 7 SDRAM 2 C 8 SDRAM 3 C 9 GND [ 10 -
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MDSC-00039-02 8 non inverting buffer QS5818 MO-118AB PSS-56B MO-118AA PSS-48B
Abstract: Now Now Now 40L-SOJ 44-40L-TSOPII 40L-SOJ SDRAM Density Organization Description , -6TG M12L128324A-7B(I)G M12L128324A-6B(I)G 4K 143MHz 86L-TSOPII SDRAM 3.3V 32Mb 1Mb*16 2K 2K 2K 2K 2K 2K 2K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K SDRAM 3.3V 16Mb SDRAM 2.5V SDRAM 2.5V SDRAM 3.3V SDRAM 3.3V SDRAM 3.3V SDRAM 3.3V SDRAM 3.3V SDRAM 2.5V SDRAM 3.3V SDRAM 3.3V SDRAM 2.5V SDRAM 3.3V SDRAM 3.3V SDRAM 2.5V SDRAM 2.5V SDRAM 3.3V SDRAM 3.3V -
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M11B416256A-25JP M11L416256SA-35JP M11L416256SA-35TG 90-FBGA M12L64164A-7T M13S2561616A-5TG M13S2561616A -5T diode 6BG 40/44L-TSOPII M11B416256A-35TG 143MH
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