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Part Manufacturer Description Datasheet BUY
CDC339DWRG4 Texas Instruments 339 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, GREEN, PLASTIC, SOIC-20 visit Texas Instruments
CDC339DBRG4 Texas Instruments IC 339 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, GREEN, PLASTIC, SSOP-20, Clock Driver visit Texas Instruments
2107713-2 TE Connectivity (2107713-2) SDC 240-35 V2006 visit TE Connectivity

sdc 339

Catalog Datasheet MFG & Type PDF Document Tags

sdc 339

Abstract: PALACE AE PALACE AE for design improvement. Furthermore, timing constraints in SDC or GCF format can be used to , generated by any synthesis tool · SDC timing constraint files June 2004 © 2004 Actel Corporation , PALACE AE. Synthesis Tool Timing Constraint File (GCF / SDC) Set Logic Effort Value , Constraint File (SDC) Designer Place-and-Route Figure 1 · ProASIC PALACE AE Use Flow 2 Using , Area Used 33.9 LE = 4 fMAX 86.9 74.8 Area Used 35.4 Result clk1 improved 55% clk2
Actel
Original

sdc 339

Abstract: SIM-31200 . 203 SDC-630/632/634 A/ST. 154 SDC-14531III. 158 SDC-14532 MONOBRID SERIES.169 S DC-14545. 171 SDC-14560. 179 SDC-14570/75 SERIES. 189 SDC-14580. 193 SDC-14600/05 SERIES. 195 SDC-14610/15 SERIES. 199 SDC-19204 MONOBRID SERIES
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OCR Scan
sdc 339 SIM-31200 scott-t transformer DTC-19300 Motorola xt 912 DSC 10 servo resolver RDC-19220

sdc 339

Abstract: digital clock ckt diagram 20 16 17 18 19 20 21 22 23 24 25 26 27 28 DB0/SDC N/C DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBS DB9 DB10 DB11 , £5, WE, RD AB0-AB4, ADEN, SDC Logical "1" Voltage V|h 2.4 5.5 2.4 5.5 V Logical "0" , supplies of less than 100mA for less than 100|is. TM 3422blfl OOObTbl TBI 3-39 This Material , DB11/SDO pin functions as the serial data output. The DBO/SDC pin functions as the serial clock input , bit appears at DB11/SDO on the next DBO/SDC high-to-low transition. The LSB (DBO) is present at DB11
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OCR Scan
MP3276 MP3274 digital clock ckt diagram DB10 MP3276AG MP3276AP
Abstract: Ground 40 48 7 15 DGND Digital Ground 41 49 8 16 DB0/SDC Data Output , after STL high to low DC DIGITAL INPUTS C5, WR, RD AB0-AB4, ADEN, SDC Logical â'1â' Voltage , 339 T TM MP3276 PRODUCT INFORMATION B asic D escrip tio n The MP3276 is a fault , functions as the serial data output. The DBO/SDC pin functions as the serial clock input and all other , appears at DB11/SDO on the next DBO/SDC high-to-low transition. The LSB (DBO) is present at DB11/SDO on -
OCR Scan
P3274

scpi parser

Abstract: sdc 339 3.3.5.1 3.3.5.2 3.3.6 3.3.6.1 3.3.7 3.3.8 3.3.8.1 3.3.8.1.1 3.3.9 3.3.8.1 3.3.9 3.3.9.1 3.3.10 , . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DCL - Device Clear - See SDC . . . . . . . . , 21 SDC ­ Selected Device Clear ­ Control Code . . . . . . . . . . . . . . . . . . . . . . . . . . . , interrupt *OPC? or *WAI. See SDC. ABORt is an event and does not have a query form. 3.3.15 *RST - , , SDC, *ESR?. *CLS is an event and does not have a query form. 3.3.2.1 Example: Reset Status To
Hittite Microwave
Original
scpi parser VXI11 SCPI-99 Hittite replace T2100 HMC-T2100 HMC-T2100B

sdc 339

Abstract: Bs" H 9 1 L 3 8 1 i '82 February 1992 1/4 339 L9812R ABSOLUTE M AXIM UM RATINGS Symbol , specified.) Parameter Test Condition Vi Isc Short Circuit Current V sdc < Output Current
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OCR Scan

sdc 339

Abstract: AM29F010 known good ­0.13 ­2.97 ­3.41 ­3.41 ­3.41 ­3.39 ­3.39 ­3.39 ­3.39 ­3.39 ­3.39 ­3.39 ­3.39 ­3.39 ­3.41 ­3.41 ­2.97 , . . . . . . . . . . . . . . . . . . . . . . . . . SDC Manufacturing ID. . . . . . . . . . . . . . .
Advanced Micro Devices
Original
AM29F010 known good AM29F010 die AMD 2909 Am29F010 Rev. A AM29F010 29F010B 29F010 29F010A

sdc 339

Abstract: AMD 2909 ­3.39 14 D1 ­17.89 ­133.31 ­0.45 ­3.39 15 D2 ­12.06 ­133.31 ­0.31 ­3.39 16 VSS ­6.40 ­133.31 ­0.16 ­3.39 17 D3 ­0.59 ­133.31 ­0.01 ­3.39 18 D4 5.25 ­133.31 0.13 ­3.39 19 D5 11.16 ­133.31 0.28 ­3.39 20 D6 17.00 ­133.31 0.43 ­3.39 21 D7 22.92 ­133.31 0.58 ­3.39 22 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDC Fabrication Process . . . . .
Advanced Micro Devices
Original
AMD ORDERING AM29F010B PACKAGE 98A01 amd programmers guide AMD ORDERING AM29F010B AM29F010B-120 AM29F010B-90

sdc 339

Abstract: HMC-T2100 3.3.5 3.3.5.1 3.3.6 3.3.7 3.3.7.1 3.3.8 3.3.9 3.3.10 3.3.10.1 3.3.11 3.3.11.1 , . . . . . . . . . . . 14 DCL - Device Clear - See SDC . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25 SDC â , interrupt *OPC? or *WAI. See SDC. Order On-Line: www.tm-hittite.com. For technical application questions , *OPC. See Also: *RST, STATus:PRESet, SDC, *ESR?. *CLS is an event and does not have a query form
Hittite Microwave
Original
CP111211

SMPTE425M

Abstract: RP168 design for Arria II GX. s2gx_tr Contains an example design for Stratix II GX, see AN 339: Serial lib , TimeQuest timing analyzer and patches the generated .sdc script with a new clock name. If your top-level , must apply the Altera-provided timing constraint file in Synopsys Design Constraints File (.sdc , timing requirements. To add the .sdc file, _sdi.sdc to your project. On the Project menu , script to patch the generated .sdc script with the new clock names. 1 A back-up copy of the .sdc
Altera
Original
SMPTE425M RP168 SMPTE-425M SD-525 alt4gxb 3G-SDI serializer UG-SDI1005-11

low pass fir Filter VHDL code

Abstract: sdc 339 from report tables, create custom reports sdc Specifies constraints and exceptions to the , sdc_ext Altera-specific SDC commands By default, only the minimum number of packages is loaded , logic_analyzer_ interface logiclock misc old_api project report sdc sdc_ext simulator sta stp timing , Quartus II TimeQuest Timing Analyzer supports SDC terminology for constraint entry and reporting , support for SDC commands in the :quartus:sdc package. f Refer to the Quartus II TimeQuest Timing
Altera
Original
QII52003-7 low pass fir Filter VHDL code 50MHZ EP1C6F256C6

ADM6992

Abstract: 1.3 1.4 2 2.1 2.2 2.3 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 , VCC2IK EESK EECS GNDIK SDC SDIO P0_ANDIS P0_RECHALF P0_REC10 VCCA2(2.5) TXP0 TXN0 GNDA RXP0 RXN0 VCCAD , . Serial Management Data Clock 15 SDIO I/O 14 SDC I 78 34 37 35 26 CKO25M CONTROL
Infineon Technologies
Original
ADM6992

ADM6992

Abstract: sdc 339 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 3.3.11 3.3.12 3.4 3.4.1 , INT_N EEDO EEDI VCC2IK VCC2IK EESK EECS GNDIK SDC SDIO P0_ANDIS P0_RECHALF P0_REC10 VCCA2(2.5) TXP0 , , this pin will be tri-state. Serial Management Data Clock 15 SDIO I/O 14 SDC I 78
Infineon Technologies
Original
ADM6992X 93c66p ADM6992/X

sdc 339

Abstract: el640.400-cb1 Overview Section and Register List reviewed SDC, PP, AAF, DIPA and ULB descriptions reviewed 1.1 20 , block size) SDC Register description reviewed 1.4 11. Oct 2001 Clarified AC Spec output , . . . . . . . . . . 74 B-3 SDRAM Controller (SDC) . . . . . . . . . . . . . . . . . . . . . . . . , . . . 105 2.3 Data Formats for Video RAM / SDC Interface . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . 115 1.3.3 Related SDC Configuration . . . . . . . . . . . . . . .
Fujitsu
Original
MB87P2020-A el640.400-cb1 PixTech HLD0909 EL640.400 C3 el640 400 hosiden hld0909 MB87J2120 MB87P2020 D-63303

50MHZ

Abstract: EP1C6F256C6 your design sdc_ext Altera-specific SDC commands sdc Specifies constraints and exceptions , Timing Analyzer includes support for SDC commands in the sdc package. f Refer to the Quartus II
Altera
Original
QII52003-10

el640.400-cb1

Abstract: HLD0909 Overview Section and Register List reviewed SDC, PP, AAF, DIPA and ULB descriptions reviewed 1.1 20 , block size) SDC Register description reviewed 1.4 11. Oct 2001 Clarified AC Spec output , . . . 74 B-3 SDRAM Controller (SDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . 105 2.3 Data Formats for Video RAM / SDC Interface . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 1.3.3 Related SDC Configuration . . . .
Fujitsu
Original
TCL COLOUR TV SCHEMATIC DIAGRAM TCL LCD COLOUR TV SCHEMATIC DIAGRAM free EL512.256 LDE052T EL320-240 LM64c142

NAT9914 application code

Abstract: TMS9914 ). 3-39 Interrupt Status Register 1 (ISR1) . 3-39
National Instruments
Original
NAT9914 NAT9914 application code TMS9914 9914 GPIB BO 336 TCA 420 TMS9914A-

sdc 339

Abstract: hd-SDI deserializer LVDS 339: Serial lib Digital Interface Demonstration for Stratix II GX Devices. Contains encrypted , TimeQuest timing analyzer and patches the generated .sdc script with a new clock name. If your top-level , Design Constraints File (.sdc) format and the additional Tcl Script File (.tcl) to ensure the SDI MegaCore function meets the design timing requirements. To add the .sdc file, _sdi.sdc to , top-level reference clock, tx_serial_refclk. 3. Execute the Tcl script to patch the generated .sdc
Altera
Original
hd-SDI deserializer LVDS hd-SDI deserializer HD-SDI SDI SERIALIZER SMPTE372M RX-2 -G 27Mhz UG-SDI1005-12
Abstract: . . . . . . . . . . . . . 15 3.3.3 DCL - Device Clear - See SDC . . . . . . . . . . . . . . . . . . , 3.3.9 DIAGnostic:COMPatibility[?] - Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . .  28 3.3.34 SDC â'" Selected Device Clear â Hittite Microwave
Original
HMC-T2200 HMC-T2220/40/70 HMC-T2220B CP120624 HMC-T2220 HMC-T2240

MLA039

Abstract: 150 UH COIL landscape pages to be . line (1) TEA1060 (LN) SREF SUP 4 2 SDC 3 THL1 THL2 LLC 14 , supply SUP 2 positive supply SDC 3 supply amplifier decoupling SREF 4 supply , Larsen limiter residual threshold level 23 DLC Larsen limiter capacitor THL2 24 VBB SDC 3 , amplifier stability (SDC) pin 3 To ensure stability of the TEA1085/TEA1085A, in combination with a transmission IC of the TEA1060 family, a 47 pF capacitor connected between SDC and SUP and a 150 µH coil
Philips Semiconductors
Original
TEA1085 TEA1085A MLA039 150 UH COIL AD2071 SO24 IC03A SCA60
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