500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
RST 5-BULK-SHORT Bel Fuse FUSE BRD MNT 5A 250VAC RADIAL visit Digikey Buy
RST 500 AMMO Bel Fuse FUSE BRD MNT 500MA 250VAC RADIAL visit Digikey Buy
RST 5 AMMO Bel Fuse FUSE BOARD MOUNT 5A 250VAC RAD visit Digikey Buy
RST 5-BULK Bel Fuse FUSE BOARD MOUNT 5A 250VAC RAD visit Digikey Buy
RST 500-BULK-SHORT Bel Fuse FUSE BRD MNT 500MA 250VAC RADIAL visit Digikey Buy
RST 500-BULK Bel Fuse FUSE BRD MNT 500MA 250VAC RADIAL visit Digikey Buy

rst-5 xb

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: "XBEE_VCC_BT" toggle to BT BT_PIO [ 7 6 5 4 3 2 1 0 ] DTR1 XB's DTR VCC FT232's DTR CTS DSR RI , NOTE: XB = XBee BT = Bluetooth Output up to 500mA at 3v3 Output up to 500mA at 5V RESET(XB's & BT's) PIO XB RX Signal Strength Indicator POWER VCC power select DSR R2 BT's breakout , C1+C3+C4+C5: stabilize power Receiveing data Indicator Uart U3 BTXB TopSide 5V , module power select USB VCC XB pin 1 XB plug on top R10 C8 ISP CTS PWR -
Original
FT232RL

P-FBGA144-1111-0

Abstract: 36MIPS Address output-10 for external SRAM 2000/01/24 5/40 TC9446F /XB 75 76 77 78 79 80 81 82 83 84 , /OFF Fig.5 Procedure of ON/OFF of soft reset 2000/01/24 12/40 TC9446F /XB 5) Incorrect , /40 TC9446F /XB 5) Non-inputted detection When existence of the edge of the input signal from , TC9446F /XB TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9446F/XB TENTATIVE , Handbooks. 2000/01/24 1/40 TC9446F /XB QFP100 TOP VIEW TC9446XB FBGA144 (Bottom View) M L
Toshiba
Original
P-FBGA144-1111-0 36MIPS TC9446F/XB QFP100-P-1420-0 50MIPS AD0-AD16

md 5406

Abstract: S i 5 3 4 1/40 L O W - J I T T E R, 1 0 - O U T P U T , A NY -F R E Q U E N C Y, A NY -O U T P U T , 60  Pin Assignments 61  3.3 V ±5% IN0  ï' VDDA: IN0 ï , : ï' VDD: 1.8 V ±5% 62   63  Generates free-running or synchronous output , FINC IN1 2 47 LOL IN_SEL0 3 46 VDD IN_SEL1 4 45 OUT6 SYNC 5 , XB 40 VDDO5 10 39 I2C_SEL OE Applications 9 X2 11 38 OUT4 30
Silicon Laboratories
Original
md 5406 64QFN

md 5406

Abstract: OUT2 X1 4 30 OUT2 XA 5 29 VDDO2 XB 6 28 LOS_XAXB X2 VDDA 7 , LOS1 X1 4 30 LOS0 XA 5 29 VDDS XB 6 28 LOS_XAXB X2 VDDA 7 , Si 5 3 4 5 / 4 4 /42 1 0 - C H A N N E L , A NY -F R E Q U E N C Y, A NY - O U T P U T J I T T E R , : 3.3 V, 2.5 V, or 1.8 V Output-output skew: , ï' VDD: 1.8 V ±5% 63  Generates any combination of  output frequencies from any input ï
Silicon Laboratories
Original

fr309

Abstract: VCO-113 MHz) 1, 3*, 3.125, 5, 6.25, 9*, 10, 12.5, 25, 30*, 50 kHz *: 10.25MHz X'tal (4) (5) L.P.F , 30 XIN I/O-1 2 S 29 CE I/O-2 3 S 28 DI XBUF 4 S 27 CL O-3 5 , -1 XIN XIN,XOUT *5 10.25 10.35 MHz *1: *2:DC *3: CTC=0 *4: CTC=1 *5: CI :CI70 , 7 I/O-1 I/O-2 2 3 O-3 5 LC72151V (VDD=4.55.5V) :VDD AVDD DDAVDD , =1 10500kHz :CTS0=0 1Hz20kHz 1 2 2 2Hz40kHz DO MSB :L/I-4 DO XOUT :XB=1 () XB
-
Original
SSOP30 fr309 VCO-113 LC72151 PDS01 N6976 O1106 B8-6328/92001 330MH

cro circuit diagram

Abstract: RPI 1035 STACK TO CRO - RSÜ+RIN-*B=1 ESÖ+RIN->ra=0 RSÔ+RIN-7B=1 X E5Ö+RIN-7B-0 RSÜ+RIN-5?ß=l XB*(CS4+S)=Û XB , ility is m aintained w ith 5 separate data ports. The M icroprogram C on tro l F unction as shown in the , 7 2 5 -0 1 M ic r o p r o g r a m C o n t r o l F u n c tio n B L O C K D I A G R A M -M C 1 0 8 , operations and m u lti way branching 5. Address masking on special instructions. 6. Repeat logic instructions , - V T T ( - 2 . 0 V) E E ( " 5 -2 V ) N e x t Address 4-111 This Material Copyrighted By
-
OCR Scan
MC10801 cro circuit diagram RPI 1035 alu M10800 M10800 CR02 CR0O-CR03

smd M21

Abstract: A08 smd · 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 , level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles · Interrupt , (area 4 and 5) · Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area · Unused , area from area 1 to 5) 3. DRAM interface · · · · · 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2
Fujitsu
Original
MB91121 smd M21 A08 smd A08 smd transistor pacific princeton A06 smd rf A07 smd DS07-16303-2E FPT-120P-M21

DS07-16303-2E

Abstract: A06 smd rf · · · · · 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency , Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16 , memory technologies DRAM interface (area 4 and 5) · Automatic wait cycle insertion : Flexible setting , endian mode supported (Select 1 area from area 1 to 5) 3. DRAM interface · · · · · 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus
Fujitsu
Original
FR30

smd 2d 1002 -reel

Abstract: FR30 Microelectronics Limited. FEATURES 1. FR CPU · · · · · 32-bit RISC, load/store architecture, 5 , Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles · Interrupt (push PC , (area 4 and 5) · Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area · Unused , area from area 1 to 5) 3. DRAM interface · · · · · 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2
Fujitsu
Original
smd 2d 1002 -reel smd code A06 DS07-16303-4E

062C

Abstract: 0627H · 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 , level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles · Interrupt , (area 4 and 5) · Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area · Unused , area from area 1 to 5) 3. DRAM interface · · · · · 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2
Fujitsu
Original
062C 0627H DS07-16303-3E

606-25

Abstract: panasonic 6169 26 FRQSEL2 LOS 3 25 FRQSEL1 NC 4 XA 6 XB 24 FRQSEL0 GND Pad VDD 5 23 BWSEL1 , . 27 5. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = ­40 to , . Table 2. DC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = ­40 to 85 ºC) Parameter , mA - 204 234 mA - 194 220 mA 1.8 V ± 5% 0.9 - 1.4 V 2.5
Silicon Laboratories
Original
606-25 panasonic 6169 SI5317A-C-GM 7812 voltage regulator spec. sheet SML-03 si5317 36-QFN

PF3F38

Abstract: FPT-120P-M21 , load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 MHz/external 25 MHz , executions · Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles , various memory technologies DRAM interface (area 4 and 5) · Automatic wait cycle insertion : Flexible , Little endian mode supported (Select 1 area from area 1 to 5) 3. DRAM interface 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle
Fujitsu
Original
PF3F38
Abstract: , 5-stage pipeline Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source , multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16 , various memory technologies DRAM interface (area 4 and 5) â'¢ Automatic wait cycle insertion : Flexible , . â'¢ Little endian mode supported (Select 1 area from area 1 to 5) 3. DRAM interface â'¢ â'¢ â'¢ â'¢ â'¢ 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single Fujitsu
Original
Abstract:   FEATURES 1. FR CPU â'¢ â'¢ â'¢ â'¢ â'¢ 32-bit RISC, load/store architecture, 5-stage pipeline , instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles â , technologies DRAM interface (area 4 and 5) â'¢ Automatic wait cycle insertion : Flexible setting, from 0 to 7 , endian mode supported (Select 1 area from area 1 to 5) 3. DRAM interface â'¢ â'¢ â'¢ â'¢ â'¢ 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Fujitsu
Original

A08 smd

Abstract: · 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 , level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles · Interrupt , (area 4 and 5) · Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area · Unused , area from area 1 to 5) 3. DRAM interface · · · · · 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2
Fujitsu
Original
F0111

QFN-36 LAND PATTERN

Abstract: XTL57 LOS 3 NC 4 VDD 5 XA 6 XB 7 NC GND Pad Functional Block Diagram XTAL/Clock GND 8 NC 9 , areas for optimum performance. For examples of connections to the XA/XB pins, refer to section 5. Figure , 38.88 MHz Clock on XA/XB, RATE[1:0]=LM 5 0 -5 Jitter Transfer (dB) -10 -15 -20 -25 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. Crystal , Operating Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = ­40 to 85 ºC) Parameter Temperature
Silicon Laboratories
Original
QFN-36 LAND PATTERN XTL57 crystal 444 ndk 24 mh 7400 CS0231 444 NDK 27

MC10801

Abstract: C10801 *B =1 ESÖ+RIN-XB=0 RSÛ+r i n -XB= i X RSQ+RIN-TB-O RSQ+RIN-XB=1 XB*(CS4+5)=0 XB*(CS4+B)=1 XB-(CS4+B , connected in parallel fo r larger m em ory ad dresses. M axim um system fle x ib ility is maintained w ith 5 , CR4-CR7. 4. Branch inputs fo r conditional operations and m u lti way branching 5. Address masking on , , CR03 CR30 CR31 CR32 CR33 CSO CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 Cjn C out Djn B XB RST Clk VEE VeE Vtt VtT
-
OCR Scan
C10801 CS45 CR3Q-CR33
Abstract: IN1 2 32 RST 3 31 VDD OUT2 X1 4 30 OUT2 XA 5 29 VDDO2 XB , S i 5 3 4 7/46 D UAL / Q UAD D S P L L A N Y - F R E Q U E N C Y, A NY -O U TP U T JITTER , +85 °C  Pb-free, RoHS-6 compliant Pin Assignments 60  3.3 V ±5% Independent , DCO mode: as low as 0.01 ppb steps per DSPLL Core voltage: ï' VDD: 1.8 V ±5% 63 ï , 47 LOL_D LOL_A 3 46 VDD LOL_B LOL_C 4 45 OUT4 5 44 OUT4 RST Silicon Laboratories
Original

FLB420001

Abstract: EXS00A-CS00997 30 29 28 RST 1 FRQTBL 2 LOS 3 NC 4 VDD 5 XA 6 XB 7 NC GND Pad Functional Block Diagram XTAL , as XA/XB input. 3. VDD = 2.5 V 4. TA = 85 °C 5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz , connections to the XA/XB pins, refer to section 5. Figure 23, "Si5317 Typical Application Circuit," on page 37. Jitter Transfer XA/XB Reference to CKOUT 38.88 MHz Clock on XA/XB, RATE[1:0]=LM 5 0 -5 Jitter , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Crystal/Reference Clock Input . .
Silicon Laboratories
Original
FLB420001 EXS00A-CS00997 crystal 444 ndk 63 7MA1400014 crystal 444 ndk 84 M1253S071

metal detector plans

Abstract: Si5315B FRQTBL 2 26 FRQSEL2 25 FRQSEL1 LOS1 3 LOS2 4 VDD 5 XA 6 XB 24 FRQSEL0 GND Pad 23 , . . . . . . . . . . . . . . . . . . . . . . . . 36 5. High-Speed I/O . . . . . . . . . . . . . . . , ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = ­40 to 85 ºC) Parameter Symbol Typ Max Unit ­40 , operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 ±5%, 2.5 , 1.8 V ± 5% 2.5 V ± 10% 3.3 V ± 10% Single-ended 0.9 1.0 1.1 20 0 0.2 - - - 40 -
Silicon Laboratories
Original
metal detector plans Si5315B TRF 7905 7835 regulator 7905 regulator bw5000
Showing first 20 results.