NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: device, can interface with up to 16 slave devices. Several important attributes of the SPI bus (e.g , read operation by reading the roe and rrdy bits in the status register. Altera Corporation 3 , ) Unused e rrdy trdy tmt toe roe Unused Unused e irrdy itrdy itmt Itoe , the status register clears the following bits: roe, toe, and e. Nios CPU-written control value. Can , ) Unused e rrdy trdy tmt toe roe Unused 3 Control (4) Unused e irrdy ... | Original |
8 pages, |
datasheet abstract |
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| Abstract: external level-shifting buffer is required (e.g., Linear Technology LTC-1386 LTC-1386) between the TxD/RxD I/O , ), receiver-overrun error (ROE), break detect (BRK), parity error (PE), and framing error (FE), bits in the Status , always be 0. ROE bit-A receiver-overrun error occurs whenever a newlyreceived character is transferred , ROE Altera Corporation Nios Embedded Processor UART Peripheral s Baud Rate Generation , TOE BRK FE PE iE iRRDY iTRDY iTMT iTOE iROE iBRK iFE iPE ROE Baud Rate ... | Original |
8 pages, |
uart with bit parity RS-232 RS-232 abstract |
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| Abstract: external level-shifting buffer is required (e.g., Linear Technology LTC-1386 LTC-1386) between the TxD/RxD I/O , ), receiver-overrun error (ROE), break detect (BRK), parity error (PE), and framing error (FE), bits in the Status , always be 0. ROE bit-A receiver-overrun error occurs whenever a newlyreceived character is transferred , ROE Altera Corporation Nios Embedded Processor UART Peripheral s Baud Rate Generation , TOE BRK FE PE iE iRRDY iTRDY iTMT iTOE iROE iBRK iFE iPE ROE Baud Rate ... | Original |
8 pages, |
RS-232 RS-232 abstract |
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| Abstract: collector-base voltage open emitter - 40 V VCER collector-emitter voltage RÅ"= 10 £2 - 35 V vceo , 20 HA 'cER collector cut-off current VCE = 30 V; RÅ"= 10 £2 - 100 HA 'ebo emitter cut-off current , 7110flEb Q04b3Ti THfi «PHIN f (GHz) s„ s„ s21 LIN. DEG. LIN. DEG. LIN. DEG. LIN. â-¡EG. 0.5 0.84 ... | OCR Scan |
3 pages, |
PTB23001X OP214 LTE42008R OP214 abstract |
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| Abstract: Multiplexer ROE RD0 14-Bit DAC 16*9 MPY 16 PCM Synthesizer ADPCM Synthesizer 8 , 40 RA1 TEST2 10 39 ROE TEST1 RD6 31 DGND 32 RESET 29 RD7 30 D6/SI 27 D7/SD 28 , when the RCS pin is "L". 39 ROE O Output enable pin for external memory. This pin becomes , I 20 CS I 14 SERIAL I When this pin is "L", RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is "H", RA23 to RA0 and ROE pins become high ... | Original |
9 pages, |
RA23 RA21 QFP64-P-1414-0 MSM9811GS-BK MSM9811 ROE capacitor FEDL9811DIGEST-02 FEDL9811DIGEST-02 abstract |
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| Abstract: Multiplexer ROE RD0 OP Amplifier 14-Bit DAC Digital Filter 16 Ã- 9 MPY 16 PCM , RA4 42 RA3 RCS 8 41 RA2 9 40 RA1 TEST2 10 39 ROE AVDD 6 DVDD TEST1 RD6 31 , become valid when the RCS pin is "H", and become invalid when the RCS pin is "L". 39 ROE O , I 20 CS I 14 SERIAL I When this pin is "L", RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is "H", RA23 to RA0 and ROE pins become high ... | Original |
9 pages, |
RA23 RA21 QFP64-P-1414-0 MSM9810BGS-BK MSM9810B M9810B ROE capacitor FEDL9810BDIGEST-02 FEDL9810BDIGEST-02 abstract |
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| Abstract: ROE bit in the command register or the external REQEN pin. Request enable input. REQEN ='0' enables , finishes. This leaves the control circuit (e.g. microprocessor) enougi time to use polling, instead of , STOP CONT enable CONT ROE enable ROE NOT USED '0'= INVALID '1' := STOP 00= INVALID 01 = INVALID 10 = , results in an immediate reset of the synthesizer to the STOP mode. The ROE and CO NT are not affec ted by , corresponding ROE enable bit is a "I". ROE determines whether the request in the status bit appears on the REQ ... | OCR Scan |
14 pages, |
MEA8000 mea8 MAB8048 IEC134 BC558 mullard mea8000 M4242 MEA8000 abstract |
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| Abstract: level, the notation will be subscripted (e.g., VCC or VPP). R-OE#, R-LB#, R-UB#, R-WE#: Used to , D13 D5 D10 D2 D8 A0 R-OE# D0 D1 D3 D12 D14 D7 OE#2 OE#2 D7 D14 D12 D3 D1 D0 R-OE# S-CS1# OE#1 D9 D11 D4 D6 D15 VCCQ , R-OE# Input SRAM OUTPUT ENABLE: R-OE#-low activates device output through the SRAM data buffers , [15:0] 8-Mbit SRAM R-WE# S-CS2 10 R-UB# R-OE# R-LB# Datasheet ... | Original |
24 pages, |
38F1020W0YTQ0 38F1020W0YBQ0 252635 28F320W18 38F1020W0YTQ0 abstract |
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| Abstract: VCC or VPP. When the reference is to timing or level, the notation will be subscripted (e.g., VCC or VPP). R-OE#, R-LB#, R-UB#, R-WE#: Used to identify OE#, LB#, UB#, WE#, RAM signals. Datasheet 5 , D13 D5 D10 D2 D8 A0 R-OE# D0 D1 D3 D12 D14 D7 OE#2 OE#2 D7 D14 D12 D3 D1 D0 R-OE# S-CS1# OE#1 D9 D11 D4 D6 D15 VCCQ , tri-state to high-Z. OE#2 is not used in this device and may be treated as RFU. R-OE# Input SRAM ... | Original |
24 pages, |
38F1020W0YTQ0 38F1020W0YBQ0 28F320W18 38F1020W0YTQ0 abstract |
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| Abstract: subscripted (e.g., VCC or VPP). R-OE#, R-LB#, R-UB#, R-WE#: Used to identify OE#, LB#, UB#, WE#, RAM signals. , VSS A[20:19] S-VCC VPP D[15:0] 8-Mbit SRAM R-WE# S-CS2 6 R-UB# R-OE , A14 A16 A16 A0 D8 D2 D10 D5 D13 WAIT CE#2 R-OE# D0 D1 D3 , D7 D14 D12 D3 D1 D0 R-OE# VCCQ VCCQ D15 D6 D4 D11 D9 OE#1 , R-OE# Input SRAM OUTPUT ENABLE: R-OE#-low activates device output through the SRAM data buffers ... | Original |
22 pages, |
88-ball 38F1020W0YTQ0 38F1020W0YBQ0 28F320W18 FLASH MEMORY 38F 38F1020W0YTQ0 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| SINGLE SUPPLY APPLICATIONS; E.G. VCC+ = 5 V, * VCC- = 0 V, VSAT+ = 3 V, VSAT- = 5 MV; POWER NOT CONNECTED + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1.11 + XTI = 3 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 = 1 + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1 + CJS = 0 + VJS = .75 + MJS = 0 + XTB = 0 + EG = 1.11 + XTI = 3 www.datasheetarchive.com/files/spicemodels/misc/opamp.lib |
Spice Models | 07/08/2009 | 299.04 Kb | LIB | opamp.lib |
| MODELS SINGLE SUPPLY APPLICATIONS; E.G. VCC+ = 5 V, * VCC- = 0 V, VSAT+ = 3 V, VSAT- = 5 MV; POWER NOT + CJO = 0 + VJ = 1 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 + N = 1 + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 + NK = .5 www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/opamp.lib |
Spice Models | 29/07/2012 | 301.82 Kb | LIB | opamp.lib |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] HP LaserJet 4/4M [port] LPT3.OS2 [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] Professional Torch Data Sheet 842293080 9 828378102 220 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fn www.datasheetarchive.com/files/duracell/amipro/docs/designer/prof.sam |
Duracell | 09/09/1996 | 534.7 Kb | SAM | prof.sam |
| f "noname"; #file 0 f " "; #file 1 f " "; #file 2 f " "; #file 3 f " "; #file 4 f " "; #file 5 f " "; #file 6 f "e:\projects\philipssemicon\design\vhdl www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (DdrToplevel.srd) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| (P!+$L )P&3;0F0:FF:;LHT D@ %$ASG7H'M)72H=AMK(FP0V0BR;:0*?]:!@H9?@ FV@(3EG4< ,!+(!D , !X_''E3)2$ UA]F: UN! C #[77 M#08?#Y[$"4P/W5 ^RB*^$IH:(^D-= XV)#^1$"* %PT @^26S-X 26S-X 26S-X 26S-X M& LTR@$=RI(4;HF^0C www.datasheetarchive.com/download/88668537-960519ZC/hex2bits.uu |
Xilinx | 05/09/1996 | 160.3 Kb | UU | hex2bits.uu |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] HP LaserJet 4/4M [port] LPT3.OS2 [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] Lockable Cycle Light Data Sheet 842293422 9 828378102 502 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [ www.datasheetarchive.com/files/duracell/amipro/docs/designer/lockcycl.sam |
Duracell | 09/09/1996 | 530.82 Kb | SAM | lockcycl.sam |
| # 0H_A-=)49 M%/M].L6CV,+//WBA*A!^% EG&3Q www.datasheetarchive.com/download/94358789-958265ZC/tactical.uu |
Xilinx | 02/07/1996 | 112.33 Kb | UU | tactical.uu |
| begin 755 chkinit.Z M'YV0 ;X!.!##G*M, !(J5(@$PH$ "P $ &"@ 0:)00@D- 5%(@XJ"04L3!B M!QP &D5JU'@ 0 $ V#&8#*RILV%+N"$(7/3)@62['K61.""3AD\=$:*#)FP MXD4 2X4N!)%SI]2%Z"@^>'H5 %$R8>B$N1H@(T4(714" www.datasheetarchive.com/download/52161151-960442ZC/chkinitr.uue |
Xilinx | 05/09/1996 | 397.58 Kb | UUE | chkinitr.uue |
| .$8!D!4*49[3")^1 +:CY3:CY;:B*\*0'?F[[?7D 8#I19#J1VN"&HA"F4T*FXXFF M$R6FPZD2_JD2'JH2/JH27JH- JH2/JH27JH- JH2/JH27JH- JH2/JH27JH-?JH4KJHGSG E_G"+$ 1U^(3MPA ,2@HS*!7%H&04@S+$ M#$I*,2@MQ:!T,8/24PQ 8/24PQ 8/24PQ 8/24PQ*4#$H= +*.0R&;Q?$SZWL4'F!3\*F,1BH/\H#BX$G0(8!P5!, , M0&B [T@AO www.datasheetarchive.com/download/37542492-960430ZC/4kefixsn.uue |
Xilinx | 05/09/1996 | 1804.08 Kb | UUE | 4kefixsn.uue |
| 705)%($EN8RX@06QL(%)I9VAT .QRR;" 8Z"80BZ M"(%, #G\C)N%;!2>) H&$Q-J3L(,Q"8#O M]P 34!-?.B !+; M GV9"EPZ*"HWK ; &@$9#)+JXIAC:FIICXB0 N=:&EI:9JLI:]I##$\NJ MF@ J\:!T\(:2AO+%H:&@1HK6P P6N*"EG *'=>WA>TKV8L E'14:92:E;G1? =ZD[R5\ M "U3H?-L#SA[R3-@LFP+.1H 'G'(E.]ZVD;/ -@%QF_W.\ WCI? www.datasheetarchive.com/download/94867712-997878ZC/pnpapp01.uu |
Xilinx | 10/09/1996 | 660.41 Kb | UU | pnpapp01.uu |