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rc+proportional+27mhz+toy+receiver

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Abstract: PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES · · · · · Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable capacitors. Wide pull range (+ , (ideal for 8.192MHz, 11.2896MHz, 12.288MHz). 27MHz crystal input. Audio Reference clock input. 3.3V , CONFIGURATION 1 6 1 5 1 4 1 3 1 2 1 1 1 0 N/C* 9 REF_Audio GND_27MHz OUT_27MHz VDD_27MHz , 27MHz. It also integrates an Audio clock phase locked loop ideal for the 8.192MHz, 11.2896MHz and PhaseLink
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PLL502-26SC PLL502-26SC-R P502-26SC VCXO 27MHZ CRYSTAL 27MHZ 27mhz 27MHZ crystal 27mhz control CRYSTAL RESONATOR 192MH 2896MH 288MH
Abstract: Preliminary PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES · · · · · Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable , Loop. Audio clock output (ideal for 8.192MHz, 11.2896MHz, 12.288MHz). 27MHz crystal input. Audio , 2 15 GND_27MHz VDD_VCXO 3 14 OUT_27MHz 13 VDD_27MHz 12 VDD_Audio 11 , , providing less than -135dBc at 10kHz offset at 27MHz. It also integrates an Audio clock phase locked loop PhaseLink
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Varicap P502-26 16SOIC
Abstract: Preliminary PLL601-27B 27MHz XO IC with Selectable Audio Clock PACKAGE PIN CONFIGURATION FEATURES · · · · XIN/FIN 1 VDD 2 GND 3 27MHz 4 PLL601-27B · 27MHz Reference Output (from 27MHz crystal or clock input). Selectable Audio Clocks supporting: F s of 32kHz , to work with a fundamental 27MHz crystal or clock input. In addition to a 27MHz clock reference, it , 12.288 24.576 (Default) BLOCK DIAGRAM Audio PLL [S1-S0] ACLK Xin/Fin XO 27MHz Xout PhaseLink
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PLL601-27BSC CRYSTAL SMD 27MHZ 27BSC 24.576MHZ crystal 32kHZ 576MH PLL601-27BSC-R P601-27BSC
Abstract: Device rx_std rx_status rx_serial_refclk rx_data rx_data_valid_out rx_clk sd_genclk_27mhz sd_data_27mhz clk_148_5Mhz 27mhz_gen SDI Transmitter SDI Receiver Serial Data (Input , wrreq rx_data_valid_out rx_clk wrclk gxb_tx_clkout 27MHz rx_serial_refclk HD/3G , 100MHz XTAL on Arria II GX FPGA Board PLL 27MHz 74.25MHz 27MHz ref PLL Data Data Unlocked Locked 148.5MHz 148.5MHz VCXO on SDI HSMC 27MHz XTAL on SDI HSMC Serial Digital Altera
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D10.2 pattern AN-601-1
Abstract: Preliminary ABMX0122 27MHz Multiple output XO with Audio Clock PACKAGE PIN CONFIGURATION FEATURES · · XIN 1 16 S1^ XOUT 2 15 27MHz VDD 3 14 VDD VDD 4 13 S0^ NC 5 12 27MHz GND 6 11 GND GND 7 10 ACLK PDOWN^ 8 ABMX0122 · · · · 2 XO outputs at 27MHz (27MHz crystal input). Selectable Audio Clocks supporting , power down feature, designed to work with a fundamental 27MHz crystal to provide the most common audio Abracon
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ABMX0122XC ABMX0122XC-T ABMX0122XCL crystal 32kHz jitter ABMX0122XCL-T
Abstract: RGBMODE OFF YCbCr ON RGB 7 MODE OFF NTSC CCIR ITU-R BT656 ON NTSC 27MHz YcbCr (ITU-R BT601 , 27MHz YcbCr (ITU-R BT601) OFF PAL 29.5MHz(Square Pixel) ON none OFF none ON PAL 13.5MHz YcbCr , OFF OFF ON ON 3 OFF ON OFF ON OFF ON OFF ON CLOCK 24.5454MHz 27MHz 28.6363MHz , ITU-R BT.656(SAV,EAV,blank (8bit) ON ITU-R BT.601 (16bit) ON RGB 7 CLKSEL OFF ex. 27MHz) ON , ) b a 1 16 MSM7654 CB2750 10/21 decoder: 27MHz / encoder: 27MHz OKI Electric Industry
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FJXL7664B-7654-01 dipsw_4 MSM7664B 200245 MSM7664 oki mr1 MSM7664B/7654 2002OKIELECTRICINDUSTRYCO
Abstract: Preliminary PLL501-22 27MHz Multiple Output VCXO with Audio Clock FEATURES · · 2 VCXO outputs at 27MHz (27MHz crystal input). Selectable Audio Clocks supporting: 32kHz, 44.1kHz, 48kHz, 64kHz , to work with a fundamental 27MHz crystal in order to provide most common audio clocks (8.192 , pulled 27MHz signal of the VCXO. The wide pull-range makes it ideal for STB and MPEG Video applications. XIN 1 16 S1^ XOUT 2 15 27MHz VDD 3 14 VDD VDD 4 13 S0 PhaseLink
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11.2896 22.5792 oscillator
Abstract: ) receiver equipment. It offers seven different clock signals while utilizing a single low-cost 27MHz , 1 GNDOSC VDD48K 27MHz 7 22 GNDDIG GND48K 8 21 GNDBUF GNDANA 9 20 GNDBUF GNDANA 10 19 12.288MHz GND27M 11 18 3.6864MHz 27MHz 12 17 1.536MHz 27MHz 13 16 VDD83M GND83M 14 15 83.33MHz 27MHz 83.33MHz , -27 Block Diagram PL603-27 XIN 27MHz Xtal Figure 2: PL603-27 Pin Assignment FEATURES · · · PhaseLink
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QUARTZ OSCILLATOR 27MHZ 27mhz receiver 1.536mhz 3.6864MHz Oscillator 3.6864MHz Crystal, 3.6864MHz VDD27M 6864MH 536MH
Abstract: cost integrated XO IC designed to work with a fundamental 27MHz crystal or a clock input. In addition to a 27MHz clock reference output, it provides two selectable audio frequencies (12.288MHz, and , . XIN/FIN 1 VDD 2 GND 3 27MHz 4 PLL601-26 · Supports the following output frequencies o 12.288MHz audio clock output o 24.576MHz audio clock output o 27MHz reference output · Accepts Crystal or reference clock inputs o Fundamental crystal: 27MHz o Reference input: 27MHz · PhaseLink
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PLL601-26SC PLL601-26SC-R PLL601-26SCL PLL601-26SCL-R P601-26SC P601-26SCL
Abstract: Duplex Loopback FIFO Design and VXCO 27mhz_gen rx_std rx_status rx_serial_refclk SDI Receiver , sdi_in sd_genclk_27mhz sd_data_27mhz clk_148_5Mhz rx_serial_refclk tx_serial_refclk HD/3G , then sends the receiver clock with the control bits to the VCXO device. 27mhz_gen This module generates a 27-MHz parallel clock to receive the SD-SDI data. Use the sd_genclk_27mhz output clock to clock the sd_data_27mhz parallel data for SD-SDI. Serial Digital Interface Reference Design for Stratix Altera
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AN-600-1
Abstract: ABV0226 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES · · · · · · · · · · Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable capacitors. Wide pull range (+/- , for 8.192MHz, 11.2896MHz, 12.288MHz). 27MHz crystal input. Audio Reference clock input. 3.3V operation , 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C GND_27MHz OUT_27MHz VDD_27MHz VDD_Audio OUT_Audio , , providing less than -135dBc at 10kHz offset at 27MHz. It also integrates an Audio clock phase locked loop Abracon
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11.2896MHZ 27Mhz CIRCUIT DIAGRAM oscillator 11.2896MHz ABV0226SC ABV0226SC-T
Abstract: SM8701BM DVD SM8701BM 27MHz 5 DVD PLL 2 1 DVD 256fs384fs768fs 27MHz 33.8688MHz fs 32kHz44.1kHz48kHz 64kHz88.2kHz96kHz · 27MHz (Top view) ( PLL ) · 27MHz , 3.3V ( ) 10 MO O 27MHz 11 MON O 27MHz ( ) 12 SO1 O 33.8688MHz , 32 XTI 27MHz MO, MON, SO1, SO2, SO3, SO4 XTI IIL1 MAX VDD = V DDP = 5.0V, VDDO = , 27MHz SM8701BM 27MHz XTI(Pin6) - XTO(Pin5) 2 27MHz 27MHz XTI C2 XTO (Pin5 Nippon Precision Circuits
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8688MH 40MAX 10MAX 62TYP NC9822C
Abstract: 27MHZ MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop (PLL). , The PLL1700 can generate four systems clocks from a 27MHz reference input frequency. The device , The PLL1700 is ideal for MPEG-2 applications which use a 27MHz master clock such as DVD players, DVD , , VDDB = +3.3V, fM = 27MHz crystal oscillation and fS = 48kHz, unless otherwise noted. PLL1700E , External Clock MCKO 27 300 50 50 40 60 fM = 27MHz, CL = 20pF PHASE LOCK LOOP (PLL Burr-Brown
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BEST active subwoofer subwoofer amplifier circuit diagram vco 27MHz subwoofer circuit diagram subwoofer amplifier subwoofer ic circuit diagram
Abstract: Preliminary ABM0127 27MHz XO IC with Audio Clock (for Set Top Boxes & MPEG Video) PACKAGE , integrated XO IC designed to work with a fundamental 27MHz crystal or a clock input. In addition to a 27MHz , MPEG Video applications. XIN/FIN 1 VDD 2 GND 3 27MHz 4 8 ABM0127 â'¢ 27MHz reference output (from 27MHz crystal input or clock input). Selectable Audio Clocks supporting , BLOCK DIAGRAM Audio PLL [S1-S0] ACLK Xin XO 27MHz Xout 30332 Esperanza., Rancho Abracon
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ABM0127SC ABM0127SC-T ABM0127SCL ABM0127SCL-T
Abstract: Preliminary PLL601-22 27MHz Multiple output XO with Audio Clock FEATURES · · 2 XO outputs at 27MHz (27MHz crystal input). Selectable Audio Clocks supporting: 32kHz, 44.1kHz, 48kHz, 64kHz , ^ XOUT 2 15 27MHz VDD 3 14 VDD VDD 4 13 S0^ NC 5 12 27MHz , feature, designed to work with a fundamental 27MHz crystal to provide the most common audio clocks , 16.384 22.5792 24.576 BLOCK DIAGRAM Audio PLL [S2-S0] ACLK PDOWN 27MHz Xin XO Xout PhaseLink
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PLL601-22XC PLL601-22XC-R PLL601-22XCL PLL601-22XCL-R P601-22XC P601-22XCL
Abstract: ABM0122 Preliminary 27MHz Multiple output XO with Audio Clock PACKAGE PIN CONFIGURATION FEATURES â'¢ â'¢ XIN 1 16 S1^ XOUT 2 15 27MHz VDD 3 14 VDD VDD 4 13 S0^ NC 5 12 27MHz GND 6 11 GND GND 7 10 ACLK 8 9 PDOWN^ ABM0122 â'¢ â'¢ â'¢ â'¢ 2 XO outputs at 27MHz (27MHz crystal input). , IC with power down feature, designed to work with a fundamental 27MHz crystal to provide the most Abracon
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ABM0122XC ABM0122XC-T ABM0122XCL ABM0122XCL-T
Abstract: from an inexpensive 27MHz crystal . · Frequency outputs: · · · · · · 27MHz Reference clock 27MHz , are generated using an inexpensive 27MHz Crystal. The accuracy of the 27MHz Input Clock should be , Block Diagram VDD OE VDDFOUT 27MHz 10MHz XIN Crystal Oscillator 24MHz PLL 28.322MHz XOUT 24.576MHz 27MHz GND GNDFOUT PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 , PCS1P2858A XIN XOUT VDD VDDFOUT GNDFOUT GND 27MHz 27MHz 1 2 3 4 5 6 7 8 16 15 14 NC OE NC 10MHz PulseCore
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crystal oscillator 24MHZ 322MH
Abstract: SM8703AV MPEG2 SM8703AV 27MHz 5 MPEG2 (MP@ML) PLL 2 1 DVD MPEG2 384fs 512fs768fs 27MHz 33.8688MHz fs 44.1kHz48kHz · 27MHz ( PLL ) · 27MHz 33.8688MHz 384fs 512fs , O Ip*1 O VDD VSS 27MHz 1 VDD VSS 33.8688MHz VSS 2 VDD 2 512fs 512fs VSS 1 VDD 1 384fs 768fs 27MHz 2 RSV*2 SO1 VSS2 VDD2 SO4 SO3 RSV*2 VSS1 VDD1 SO2 RSV*2 SO5 , 0.5VDD 7 27MHz SM8703AV 27MHz 1 XTI(Pin8) - XTO(Pin9) 2 27MHz 27MHz XTI C2 Nippon Precision Circuits
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PLL VCO 27MHz IC SO5 tmlh 0000MH NC9902B2001
Abstract: generator. The PCS1P2858A uses the latest PLL 27MHz crystal . · Multiple Clock outputs: technology. The six Clock outputs are generated using · 27MHz Reference clock an inexpensive 27MHz Crystal. The accuracy of the · 27MHz Reference clock 27MHz Input Clock should be within ±50ppm. , targeted for use in HDTV digital video Block Diagram VDD OE VDDFOUT 27MHz 10MHz XIN/CLKIN Crystal Oscillator 24MHz PLL XOUT 28.322MHz 24.576MHz 27MHz GND GNDFOUT PulseCore
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28.322MHz CLOCK27MHZ PulseCore Semiconductor TSOT23
Abstract: power push-pull pair 1 - REF, able to drive 3 loads, 14.318MHz 1 - 27MHz_SS/non_SS single-ended output , GNDDOT96MHz 2 DOT96T_LPR 3 DOT96C_LPR 4 VDD_27MHz 5 27MHz_nonSS 6 27MHz_SS 7 GND27MHz 8 9 10 11 12 13 14 15 16 , VDDDOT96MHz_3.3 GNDDOT96MHz DOT96T_LPR DOT96C_LPR VDD_27MHz 27MHz_nonSS 27MHz_SS GND27MHz GNDSATA SATAT_LPR , for the 27MHz output 3.3V. OUT OUT OUT 3.3V Single-ended 27MHz non-spread clock. 3.3V Single-ended 27MHz spread clock. Ground pin for the 27MHz outputs. 11 12 13 SATAC_LPR GNDSRC SRCT1_LPR 14 15 Integrated Device Technology
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ICS9LRS 9lrs F0413 S3187BIL CK505 ICS9LRS3187B 318MH VDDDOT96MH GNDDOT96MH GND27MH
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