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qpsk modulation VHDL CODE

Catalog Datasheet MFG & Type PDF Document Tags

16 QAM modulation verilog code

Abstract: 16 bit qpsk VHDL CODE Block Size (Bytes) Overall Code Rate Constituent Codes QPSK 23 48 ~ 1/2 (32,26 , comtech aha corporation PRODUCT BRIEF IEEE 802.16a COMPLIANT TURBO PRODUCT CODE DECODER ASIC CORE INTRODUCTION The IEEE 802.16a standard compliant TPC core implements the Turbo Product Code (also called Block Turbo Code) Forward Error Correction (FEC) decoding. (A TPC Encoder core is also available.) AHA delivers a VHDL or Verilog netlist for integration into an ASIC. This core implements the
Comtech AHA
Original

X9009

Abstract: verilog code for BPSK the modulation type to QPSK Microprocessor interface can be added to allow more flexibility Burst and , documentation Design File Formats EDIF Netlist, VHDL RTL available extra Constraints File decoder.ucf Verification VHDL testbench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used 1076 Compliant VHDL Simulator, Verilog Simulator Support Support , Supports BPSK modulation The following parameters can be configured to meet your needs: - Soft decision
Xilinx
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5 to 32 decoder using 3 to 8 decoder vhdl code

Abstract: branch metric modulation type to QPSK · Microprocessor interface can be added to allow more flexibility · Burst and , info@cast-inc.com 7. Bit error rate (BER) monitor required? _ 8. Modulation type: BPSK or QPSK , Supports BPSK modulation The following parameters can be configured to meet your needs: - Soft decision , documentation Design File Formats EDIF Netlist, VHDL RTL available extra Constraints File decoder.ucf Verification VHDL testbench Instantiation Templates VHDL, Verilog Reference designs & None application
Xilinx
Original

BPSK modulation VHDL CODE

Abstract: vhdl code for bpsk modulation 2 and Eb/N0 = SNR + 3 dB. If we have uncoded QPSK modulation with I = +/-1 and Q = +/-1 and add , structural VHDL · Probability density function (PDF) deviates less than 0.2 percent from the Gaussian , Provided with Core Documentation Verification Product Specification VHDL UCF MATLAB + ModelSim + Hardware VHDL Wrapper Additional Items BER Measurement of Uncoded BPSK in Hardware , : Xilinx is providing this design, code, or information "as is." By providing the design, code, or
Xilinx
Original

GSM 900 simulink matlab

Abstract: verilog code for ofdm transmitter Numerically Controlled Oscillator QPSK & QAM Hardware DSP Blocks Modulation Antenna FEC , (DSP) modulation functions, and traditional signal engineers face a difficult challenge: to , code while enjoying the PLD You can download signal processing IP functions benefits of hardware , encryption, forward error correction (FEC), and cyclic redundancy code (CRC) checking (see Figure 3). , system- DES core, Altera has Rijndael, SHA-1, and MD5 cores. electronic code book (ECB) or
Altera
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CRC matlab

Abstract: mini project simulink S T ECB Electronic Code BookDES DSP PLD DSP DES IP DES IP , QPSK & QAM DSP FEC DSP1Mbps FEC 100Mbps , Plug-In Manager QAMQuadrature Amplitude Modulation MPSKM-ary Phase Shift Keying: DPSK , AHDL Altera Hardware Description Language VHDL Verilog HDL MegaWizard Plug-InMATLABSimulink VHDL Verilog HDL 4 Altera Corporation MATLAB/Simulink PLD IPIP MegaStoreweb IP
Altera
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TC3024

Abstract: vhdl code hamming Gaussian channel and QPSK modulation. Results given with 5 -5 iterations. Product Code (32,26) x (32,26 , 29 00 18 03 www.turboconcept.com TC3000 Turbo Product Code decoders Introducing turbo product , Large block sizes : up to 65 kbits On-the-fly change of the code Shortening facilities to adjust , flexibility : TC3000 family member VHDL generic parameters before synthesis On-the fly parameters from block to block 9 9 9 9 9 9 9 9 9 9 9 BCH t=2 code support (YES/NO) Choice on bitrate
TurboConcept
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TC3014 TC3024 TC3022 TC3011 APEX20K vhdl code hamming vhdl coding for hamming code hamming decoder vhdl code hamming vhdl block diagram code hamming TC3012 TC3011TC3021

MIL-STD-188-182

Abstract: MIL-STD-188-183 -188-182 MIL-STD-188-183 PLD Provides ASIC Performance plus Software Flexibility VHDL Source Code Modules , error rate performance characteristics for detection of coherent QPSK with all code rates applied. BER , -6 10 -7 10 -8 10 Figure BER-2: BER in vs. BER out for coherent QPSK with all code , Sheet Table FEC-2 denotes the puncturing patterns for the k=7, Rate 1/2 code to achieve the 3/4 and , -1: Tap Configurations for k= 7 and 9 Code Rate Symbol 3/4 P1 : P2 : P1 : P2 : P1 : P2
Nova Engineering
Original
F805SC MIL-STD-188-181 MIL-STD-188-182 MIL-STD-188-183A MIl-STD-188-181B 16 bit qpsk VHDL CODE MIl-STD-188181B

baseband QPSK matlab code

Abstract: qpsk demapper VHDL CODE QPSK, 16QAM, and 64QAM modulation schemes. You can configure the hardware modules at run time, so you , performance, especially for higher order modulation schemes such as 64QAM. For QPSK, the soft information , soft decisions when operating in 64QAM modulation mode. In the 16QAM and QPSK modes, the output bus is , Physical Layer WiMAX Modulation Specifications This reference design provides a constellation mapper , modulation scheme. The symbols are normalized so that each constellation has an equal average power, as
Altera
Original
baseband QPSK matlab code qpsk demapper VHDL CODE Wimax in matlab simulink simulink 16QAM 16qam demapper VHDL CODE gsm simulink

lms algorithm using verilog code

Abstract: lms algorithm using vhdl code .152 QPSK Equalizer , optimized netlist that can be used without risk of changes during design processing. Although VHDL and Verilog HDL files are available from most partners, a source code license is usually more expensive than a post-synthesis netlist license because the source code versions represent more intrinsic value. Altera recommends , ensures that engineering effort is not required to reoptimize the behavioral source code. OpenCore
Altera
Original
lms algorithm using verilog code lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer verilog code for lms adaptive equalizer for audio digital IIR Filter VHDL code

qpsk AND 8PSK modulation VHDL CODE

Abstract: XILINX vhdl code LDPC QPSK, 8PSK, 16APSK, or 32APSK. Rate, frame size, and modulation can be changed on a frame-by-frame , Rate Input: Parameters to be used to encode frame (frame length, code rate, modulation information , Values (RATE[6.5]) Modulation 0 QPSK 1 8PSK 2 16APSK 3 32APSK Pilot , Modulation Type Rate QPSK 8PSK 16APSK 32APSK DOUT(0) 2i+1 3i+2 4i+3 5i+4 DOUT , is 4 with Symbol output format, as for a modulation type QPSK and 8PSK, only 2 bits and 3 bits of
Xilinx
Original
qpsk AND 8PSK modulation VHDL CODE XILINX vhdl code LDPC LDPC encoder verilog vhdl code FOR 8PSK qpsk modulation VHDL CODE vhdl code for ldpc DS505

vhdl code for ofdm

Abstract: ofdm matlab simulation block symbols by guard interval insertion. Core Modifications Source code uses VHDL generics in order to , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , for a range of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64
Xilinx
Original
vhdl code for ofdm ofdm matlab simulation block vhdl code for 16 prbs generator prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for block interleaver

vhdl code for cordic cosine and sine

Abstract: verilog code to generate sine wave synthesis (DDS), and quadrature amplitude modulation (QAM) / quadrature phase shift keying (QPSK) modulator , s Family: APEXTM 20K, ACEXTM, FLEX® 10, FLEX 8000, and FLEX 6000 s s s s Ordering Code , width-frequency modulation input User-defined frequency resolution User-defined angular and magnitude precision , Diagram Phase Increment Frequncy Modulation Output Phase Accumulator Waveform Generation , logic Modulation input Modulates the sinusoid and indicates the frequency modulation input width
Altera
Original
vhdl code for cordic cosine and sine verilog code to generate sine wave vhdl code to generate sine wave verilog code for CORDIC to generate sine wave CORDIC to generate sine wave verilog code for cordic algorithm sine cosine

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter insertion. Core Modifications Source code uses VHDL generics in order to customize MW_DVB-T/H Modulator , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64 states
Xilinx
Original
vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm OFDM matlab program CODES

IEEE Standard 1014-1987

Abstract: diagram of connectors of 4 USB and 1 RS232 and 1 Firewire 2 infrared susceptible to noise ­ than similar modulation techniques, such as QPSK and 64QAM. Buffer Random Access Memory , signal using Adaptive Differential Pulse Code Modulation. Data Encryption Standard Digital Frequency , ). The modulation method selected for 802.11b is known as CCK (complementary code keying), which , keying. QPSK is a digital frequency modulation technique used for sending data over coaxial cable , in-circuit test equipment. biphase shift keying. BPSK is a digital frequency modulation technique used for
Xilinx
Original
IEEE Standard 1014-1987 diagram of connectors of 4 USB and 1 RS232 and 1 Firewire 2 infrared verilog hdl code for traffic light control BPSK modulation VHDL CODE ternary content addressable memory VHDL DECT base station schematic Q1-02 VME64

vhdl code for lte channel coding

Abstract: vhdl code CRC for lte access to algorithmic source code for the W1910 library. It allows users to explore the 3GPP LTE , ) in order to precisely test any level of abstraction. With source code, users gain a dramatic head , mixture of implementations: · Algorithmic IP (block level, .m-file, C+) · Fixed-point and VHDL , license with 0% residual. QPSK 16 QAM 64 QAM Figure 3. The W1910 library allows link-level , that will improve my design process? · Algorithmic confidence. Proven, modifiable source code gives
Agilent Technologies
Original
W1912 vhdl code for lte channel coding vhdl code CRC for lte MODULATOR ofdm 64-qam lte mimo ofdm modulator channel equalization MIMO W1910EP/ET W1912ET 5990-4283EN

wimax OFDMA Matlab code

Abstract: OFDMA Matlab code quadrature phase shift keying (QPSK) or quadrature amplitude modulation (QAM). DDC Specific , type is expressed in terms of quadrature phase shift keying (QPSK) or quadrature amplitude modulation , designed to support scalable orthogonal frequency-division multiple access (OFDMA) modulation with a Fast , ) QPSK 1/ 2 -16.4 QPSK 3/4 -18.2 16QAM 1/2 -23.4 16QAM 3/4 -25.2 64QAM 2/3 , 11.2 1/2 16.4 18.2 2/3 22.7 3/4 16-QAM Coding Rate 3/4 QPSK Eb/N0 (db
Altera
Original
wimax OFDMA Matlab code OFDMA Matlab code matlab code for wimax transceiver Source code for pulse width modulation in matlab low pass Filter VHDL code ofdma simulink matlab AN-421-2

CRC matlab

Abstract: dsp processor design using vhdl ) Image-processing cores (e.g., JPEG, DCT) Modulation cores (e.g., QPSK, Equalizer) Encryption cores (e.g., DES , suitable hardware description language (HDL) such as VHDL or Verilog HDL. Thus the same FPGA can implement , changing a design's source code. Designers can integrate a parameterized IP core in any hardware , then implemented in C/C+ or Assembly code using a standard integrated development environment, such as the Code Composer Studio from Texas Instruments, that provides design, simulation, debug, and
Altera
Original
CRC matlab dsp processor design using vhdl turbo encoder model simulink how dsp is used in radar radar dsp processor VHDL code of DCT by MAC

soft 16 QAM modulation matlab code

Abstract: qpsk demapper VHDL CODE Differential Quadrature Phase Shift Keying M-ary Phase Shift Keying M-ary Quadrature Amplitude Modulation Pulse Amplitude Modulation Altera Corporation Contents About this User Guide , .36 VHDL Simulation in ModelSim , Release Date July 20 2002 Ordering Code IP-MAP/DEMAP Product ID(s) 0072 Vendor ID(s , , FLEX®, ACEX®, and StratixTM devices Supports a variety of modulation schemes, including: ­ M-QAM ­
Altera
Original
soft 16 QAM modulation matlab code 16 QAM modulation verilog code 16 QAM modulation matlab code vhdl code for bpsk demodulation verilog code for oqpsk modulator pulse amplitude modulation matlab code

verilog code for 2D linear convolution

Abstract: verilog code for GPS correlator used without risk of changes during design processing. Although VHDL and Verilog HDL files are available from most partners, a source code license is usually more expensive than a post-synthesis netlist license because the source code versions represent more intrinsic value. Altera recommends using , no engineering effort is required to reoptimize the behavioral source code. 1 Profiles , Text Design File (.tdf), or VHDL Design File (.vhd). Altera Corporation 5 Introduction
Altera
Original
verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter M-CAT-AMPP-02 EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50
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