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5962-8515522SA Texas Instruments OT PLD, 10ns, CDFP20, CERAMIC, DFP-20 pdf Buy
TIBPAL20R6-25CFN Texas Instruments OT PLD, 25ns, PQCC28, PLASTIC, CC-28 pdf Buy
TIBPAL20R8-10CFN Texas Instruments OT PLD, 10ns, PQCC28, PLASTIC, CC-28 pdf Buy

programmable peripheral Interface pentium

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: I2C BUS CONTROLLER IEEE 1149.1 JTAG INTERFACE PROGRAMMABLE CLOCKS 0.18 MICRON TECHNOLOGY. 1.8V , STPC PICTOR X86 CORE PC COMPATIBLE SOC with GRAPHICS and VIDEO PRODUCT PREVIEW s s PENTIUM , , S-VIDEO PCI 2.2 COMPLIANT MASTER/SLAVE CONTROLLER INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR , s s s s s s s s s PC PIC TO R PBGA388 PBGA388 Logic Diagram Pentium II Class , Pentium® MMX® Class processor, fully compatible with Industry Standard, and combines it with powerful ... STMicroelectronics
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datasheet

4 pages,
97.85 Kb

upscaler pentium mmx PBGA388 CRC-16 CCIR656 200MHZ 133MHZ colour tv chroma section TEXT
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Abstract: Parallel digital communication Interface to electromechanical and solid-state relays 8255 emulation Overview Hardware DAQ-DIO ASIC The DAQ-DIO ASIC is a 32-bit general-purpose digital I/O interface , /O interface for PCI, PXI, CompactPCI, PCMCIA, and ISA computers. The 6533 incorporates the National Instruments DAQ-DIO ASIC, a 32-bit general-purpose digital I/O interface specifically designed , www.natinst.com Data Acquisition Data Lines MITE PCI, PCMCIA, or AT Plug and Play Interface EEPROM ... National Instruments
Original
datasheet

4 pages,
52.43 Kb

NEC 8255 82C55 NEC atdio32hs 68F-50M 8255 a pin diagram 8255 PPI INTEL 430FX AT-DIO-32HS DAQCARD-6533 SH68-68-D1 intel 430FX 8255 pci or dma intel 8255 pin diagram pcidio32hs PCI-DIO-32HS PXI-6533 PCI-DIO PCI-DIO-32HS PXI-6533 8255 operating modes PCI-DIO-32HS PXI-6533 R6850-D1 PCI-DIO-32HS PXI-6533 8255 intel PCI-DIO-32HS PXI-6533 8255 Chip PCI-DIO-32HS PXI-6533 PCI-DIO-32HS PCI-DIO-32HS PXI-6533 PXI-6533 TEXT
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Abstract: on the Pentium Processor. System designers can take advantage of the power of the PCI (Peripheral , Interface with Full Bus Master Capability Supports the Pentium Processor Primary Cache in either , Interface - Single Component ISA Controller - Two Component EISA Bus Interface - Minimal External Logic , Peripheral Component Interconnect (PCI) Local Bus Operating at 30 MHz or 33 MHz - Up to 132 Mbytes/sec , Provides a 64-Bit Interface to DRAM Memory - From 2 Mbytes to 192 Mbytes of Main Memory - 70 ns and 60 ns ... OCR Scan
datasheet

13 pages,
436.88 Kb

HP-3 transceiver 82378zb 29046 "snoop filter" 82378IB TEXT
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Abstract: programmable event detectors · Full system, data, cache, and peripheral control - CY82C691 CY82C691 System Controller - CY82C692 CY82C692 Data Path Unit with integrated 128-KB 128-KB BSRAM - CY82C693 CY82C693 Peripheral Controller - CY82C693U CY82C693U Peripheral Controller with USB support - CY82C694 CY82C694 128-KB 128-KB Expansion Cache Unit · Supports all , main memory · Fully integrated Peripheral Controls - Keyboard Controller with full 8042 , Pentium-class processor based system with the USB (Universal Serial Bus), PCI (Peripheral Component ... Cypress Semiconductor
Original
datasheet

5 pages,
107.46 Kb

amd k5 32 bit block diagram CY2254ASC-2 CY27C010 cy82 CY82C691 CY82C692 CY82C693 CY82C694 Cyrix 6x86 82C691 AMD k6 addressing mode TEXT
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Abstract: PORT USB HOST CONTROLLER (OCHI) 10/100 ETHERNET MAC INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR EXTERNAL RTC ULTRA DMA-66 DMA-66 IDE CONTROLLER POWER MANAGEMENT UNIT 16-BIT 16-BIT LOCAL BUS INTERFACE I2C BUS CONTROLLER UART (1 RxTx) IEEE 1149.1 JTAG INTERFACE Eight GENERAL PURPOSE IO PROGRAMMABLE , s s s s s s s s s s s PENTIUM® II CLASS PROCESSOR UP TO 250 MHZ 64-BIT 64-BIT SDRAM , 10/100 MAC PMU DESCRIPTION The STPC VEGA integrates a fully static Pentium® II® Class ... STMicroelectronics
Original
datasheet

5 pages,
94.69 Kb

Pentium 166 MMX PBGA388 CRC-16 Intel 8237 dma controller block diagram TEXT
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Abstract: ). It is clear that, for the foreseeable future, the Pentium and Pentium-compatible processors will be the dominant microprocessors. Over 30 million Pentium processors were sold in 1995, and projections for 1996 show Pentium sales reaching 60 million units. This rapid growth will be accompanied by , faster Pentium processor. For this and other performance-related reasons, SRAM cache has become a standard feature in almost all Pentium designs. The typical PC configuration today consists of a central ... Cypress Semiconductor
Original
datasheet

4 pages,
57.53 Kb

"Keyboard Controller" CY82C691 CY82C692 8042 Keyboard Controller CY82C694 ibm pc keyboard 8042 keyboard TYPE OF SRAM cy82 CY82C693 8042 "Keyboard Controller" what is cache memory ibm pc keyboard controller TEXT
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Abstract: s s s s s s s s s s PENTIUM® II CLASS PROCESSOR RUNNING IN X1 MODE UP TO 133MHZ 133MHZ OR X2 , CONTROLLER USB HOST CONTROLLER (OCHI) 10/100 ETHERNET MAC INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT , CHANNELS 1 I2C BUS CONTROLLER UART (1 RxTx) IEEE 1149.1 JTAG INTERFACE 8 GENERAL PURPOSE IO PROGRAMMABLE CLOCKS 0.18 MICRON TECHNOLOGY. 1.8V CORE & 3.3V I/O'S MAXIMUM POWER DISSIPATION; 3.5W @ 200MHZ 200MHZ ST PC VE PBGA388 PBGA388 Logic Diagram Pentium II® Class Core USB Host I/F PCI I/F ... STMicroelectronics
Original
datasheet

4 pages,
28.37 Kb

PBGA388 PBGA-388 Intel 8237 dma controller block diagram ethernet to usb CRC-16 200MHZ 133MHZ DMA Controller 8237 TEXT
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Abstract: processor is communicating with a LPCI peripheral. This implementation of an independent data interface , interface to the BPCI supports two modes of operation, Central Resource and Peripheral Bridge. In the , can be viewed as the high-speed private peripheral bus for the local processor. The BPCI interface , processor is communicating with a LPCI peripheral. This implementation of an independent data interface , interface to the BPCI supports two modes of operation, Central Resource and Peripheral Bridge. In the ... RadiSys
Original
datasheet

4 pages,
192.79 Kb

IXP1200 8259s timer counter 8254 74LS612 TEXT
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Abstract: and Pentium III processors in FC-PGA and FC-PGA2 packages Intel® 815 GMCH and C-ICH chipset Up to , character display interface System management Fan control Dual watchdog timers Power management PhoenixBIOS* Expansion slot for SCSI module PCI/ISA PICMG 1.0 R2.0 compliant Peripheral connectivity , peripheral cards thus enabling the user to maximize the availability of backplane slots. It offers a scalable platform with a choice of processors ranging from an 850MHz Celeron* up to a 1.26GHz Pentium* III ... RadiSys
Original
datasheet

4 pages,
143.23 Kb

phoenixbios EPC2325S EPC-2325 82562ET vga D-sub connector RadiSys pcI diagnostic card codes MC146818B SLOT PGA 370 TEXT
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Abstract: 64-bit data width only 3.3V DRAM interface with 5V-tolerant inputs Programmable I/O drive , interface with 5V-tolerant inputs · Programmable I/O drive capability for MA, command, and MD signals · , board implementation Flexible CPU Interface · Supports 64-bit Pentium , AMD 5K86TM 5K86TM , AMD 6K86TM 6K86TM , BIOS support · Programmable ISA bus clock · Supports external IOAPIC interface for symmetrical , South Bridge with ACPI Power Management Flexible CPU Interface · Supports 64-bit Intel Pentium and ... VIA Technologies
Original
datasheet

14 pages,
791.6 Kb

VT82C595 AMD k6 addressing mode Apollo VP Apollo VP2 VT82C580VPX via apollo vp VIA vt82c580 Apollo vp VT82C586 Cyrix 6x86 VT82C585VPX datasheet VT82C587VP VT82C598AT VT82C586B APOLLO 2 SFF-8038i VT82C596 MVP3 SFF-8038 APOLLO vt82c580 vpx VT82C585VPX TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
Pentium® and Pentium® II Processor Interface Pentium® and Pentium® II Processor Interface The PIIX4 CPU interface allows connection to all Pentium and Pentium II processors. The Sleep mode for the Pentium II ISA/EIO Bridge IDE Interface Keyboard Controller, BIOS, Real Time Clock, a second microcontroller, as well as two programmable chip
/datasheets/files/intel/products one/design/intarch/techinfo/430tx/archover.htm
Intel 04/05/1999 16.86 Kb HTM archover.htm
Intel Graphics Accelerated Graphics Port Pentium® II   Intel 430TX 430TX PCIset Optimized for Pentium ® processor with Management Architecture (DPMA) provides support for ACPI (Advanced Configuration and Power Interface) for mobile as well as desktop systems for convenient and flexible peripheral connections outside the box desktop and mobile PC performance by optimizing the capabilities of the Intel Pentium ® processor with
/datasheets/files/intel/design/pcisets/prodbref/430tx/index-v3.htm
Intel 18/05/1998 24.94 Kb HTM index-v3.htm
n UART ( 1 RxTx ) n IEEE 1149.1 JTAG INTERFACE n 8 GENERAL PURPOSE IO n PROGRAMMABLE CLOCKS undergoing evaluation. Details are subject to change with out notice. [ Pentium is a Registered Trademarks of Intel Corporation TM Logic Diagram n PENTIUM [ II CLASS P ROCESSOR R UNNING IN X1 MODE UP MAC n I NTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR EXTERNAL RTC n U LTRA DMA- 66 IDE DESCRIPTION The STPC VEGA integrates a fully static Pentium [ II [ Class processor, fully compatible with
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7536.htm
STMicroelectronics 24/01/2001 10.17 Kb HTM 7536.htm
Pentium® Processor Family for High Performance Embedded Applications Pentium® Processor Family for High-Performance Embedded Applications Product Highlights Pentium® processor: 100, 133+VRT, and 166 MHz 64-bit data bus 8-Kbyte code cache 8-Kbyte data cache (write-back) 50 MHz and 66 MHz bus speeds On-chip APIC (Pentium processor 100 and 166 MHz) Integrated, high-performance floating point unit SL technology power management features (Pentium
/datasheets/files/intel/design/intarch/prodbref/27292901-v1.htm
Intel 31/01/1997 13.78 Kb HTM 27292901-v1.htm
management functions Emulated I/O Advanced programmable interrupt controller (APIC) bus interface Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/design/i960/prodbref/272740-v4.htm
Intel 01/02/1999 16.5 Kb HTM 272740-v4.htm
management functions Emulated I/O Advanced programmable interrupt controller (APIC) bus interface Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/products one/design/i960/prodbref/272740.htm
Intel 30/04/1999 16.5 Kb HTM 272740.htm
functions Emulated I/O Advanced programmable interrupt controller (APIC) bus interface unit Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/design/i960/prodbref/272740.htm
Intel 02/11/1997 16.61 Kb HTM 272740.htm
interface unit Multiprocessor interrupt management for Intel architecture CPUs (Pentium® and Pentium Pro Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/technologies/design/iio/prodbref/272740.htm
Intel 01/05/1999 25.13 Kb HTM 272740.htm
management functions Emulated I/O Advanced programmable interrupt controller (APIC) bus interface Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/design/i960/prodbref/272740-v5.htm
Intel 15/11/1998 16.53 Kb HTM 272740-v5.htm
interface unit Multiprocessor interrupt management for Intel architecture CPUs (Pentium® and Pentium Pro Pentium® and Pentium Pro processors. The i960 RP/RD I/O processor is a single-chip intelligent I/O interface for system management features, two DMA controllers as well as several other peripherals required cards that include an embedded processor, memory and various other peripheral components. Although this PCI bus arbitration unit Six secondary bus masters Priority programmable to three levels or
/datasheets/files/intel/design/iio/prodbref/272740-v2.htm
Intel 06/08/1998 21.79 Kb HTM 272740-v2.htm