NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: /Verilog-HDL Simulator Actel Designer Series Development System (Program File) Programmed FPGA , provide a fast path to system-level design. Through Actel's CoreHDL Alliance program, Actel has built , customizable single-chip PCI-compliant FPGA solution with better than 95% gate utilization and high-end PCI , developed in industry-standard VHDL and Verilog-HDL that can be rapidly customized and integrated. The , implemented in Actel FPGAs or SPGAs using netlist or RTL scripts. Verilog-HDL or VHDL simulation is ... | Original |
2 pages, |
uart vhdl fpga UART using VHDL FPGA based dma controller using vhdl C704 actel program uart vhdl fpga datasheet abstract |
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| Abstract: ( , gates) ·VHDL Synth Xilinx Alliance Series · · Expanded & Enhanced Alliance partnership program , Software - 5 FPGA Architect High Density Design Expertise Xilinx Core Software Roadmap Next , component specification · Automatic simulation model generation (VHDL and gate-level) · Automatic module , · Standard interfaces for seamless EDA integration · XNF, LPM, EDIF, Verilog, VHDL (VITAL ... | Original |
18 pages, |
XC9500 XC7300 XC5200 XC4000EX XC4000E XC3000 uart vhdl fpga program uart vhdl fpga datasheet abstract |
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| Abstract: ac_cast_c_uart.fm Page 1 Thursday, October 8, 1998 10:22 AM Compact UART October 12, 1998 , Features · · · · · · Compact UART 8 bit characters TxC / RxC (16 times the desired output baud , Formats .ngo, .XNF Netlist; VHDL Source RTL available extra Constraint Files .ncf Verification Tool VHDL Schematic Symbols Viewlogic Evaluation Model None Reference designs & None application , Entry/Verification VHDL RTL Tool Support Support provided by CAST, Inc. The C_UART core is used ... | Original |
3 pages, |
XC9500XL XC9500 XC4000XL 163-26 uart vhdl UART using VHDL program uart vhdl fpga 78005ap uart vhdl fpga datasheet abstract |
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| Abstract: (UART) UART_0 Nios II Processor UART Is the Interface ACEX1KEP1k100 for the Download Program , (compiled from VHDL code) SD178A SD178A voice circuit and program SD178A SD178A CNTR (compiled from VHDL code , voice circuit and an nRF2401 RF module on the DE1 board Design a SD178A SD178A controller using VHDL , using SOPC Builder Compile the program for the main interfaces of the digital bus station sign using , Build a Nios embedded system using SOPC Builder Compile the main program control settings of the bus ... | Original |
10 pages, |
led sign C language ACEX1K MAX232 nRF2401 program uart vhdl fpga RF MODULE CIRCUIT DIAGRAM SD178 SD178A LCD module in VHDL uart c code nios processor embedded system projects UART using VHDL vhdl code for lcd display datasheet abstract |
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| Abstract: Compact UART January 10, 2000 Product Specification AllianceCORETM Facts CAST, Inc. 24 , VirtexTM-E devicesCompact UART · 8-bit characters · TxC / RxC (16 times the desired output baud rate) · 1 , netlist, .ngo, Verilog Source RTL available extra Constraints File C_UART.ucf Verification VHDL testbench, test vectors Instantiation VHDL, Verilog Templates Reference Designs & None Application Notes Additional Items None Simulation Tool Used 1076 compliant, VHDL simulator, Verilog simulator ... | Original |
3 pages, |
xilinx 9500 program uart vhdl fpga uart vhdl fpga 9572XL uart verilog testbench UART using VHDL testbench of a transmitter in verilog datasheet abstract |
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| Abstract: DELIVERS FPGA INDUSTRY'S FIRST FULLY VERIFIED PCI MODULES TO KICK OFF NEW LOGICORE PROGRAM SAN JOSE, Calif., January 8, 1996-Xilinx, Inc., (NASDAQ:XLNX) today announced its new LogiCore(tm) program by delivering the industry's first 100 percent compliant PCI-Interface for FPGAs. The Xilinx program is unique , Series FPGA. The modules result in the highest transfer rate of any programmable solution in the , allowed us to focus our resources on our system design." \ The Xilinx LogiCore program will provide ... | Original |
3 pages, |
XC4000E Delco Electronics Delco XC4000E abstract |
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| Abstract: SOPC Builder FPGA I/O SOPC BuilderQuartus II DSP SOPC Builder , Builder q q q q 11 Quartus II Quartus II SOPC UART Timer CPU RAM Interface Architecture User Logic IP User DSP IP Quartus II FPGA CPLD Quartus II , DSP Builder Quartus II FPGA CPLD 2 Mentor Graphics LeonardoSpectrum 200331 TM Model TechnologyTMModelSim VHDL Verilog HDL HDL Quartus II EDA11 EDA11 Altera Corporation ... | Original |
12 pages, |
EP1S10 EP20K160E EP20K30E EP20K60E EPF10K30E EPF10K50S EPXA-DEVKIT-XA10D EPXA10-DEV-BOARD Nucleus PLUS RTOS PL-APU synopsys leda tool vhdl code rs232 altera datasheet abstract |
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| Abstract: Windows 98/ME/2000/XP 98/ME/2000/XP, VHDL code examples, FPGA loader program ( including Delphi source code ) and a , program / reprogram the FPGA over USB in a fraction of a second. Not only can the contents of the FPGA be , as FPGA primary · clock. · Windows FPGA loader interface DLL supplied VHDL programming , the FT2232C FT2232C channel A to program the FPGA "on-the-fly". The FPGA can be programmed / reprogrammed in , series FPGA ( EP1K10TC100-3 EP1K10TC100-3 ) in a compact ready to use module. The power and IO pins of the module are ... | Original |
9 pages, |
easy examples of vhdl program EP1K10TC100-3 FPGA Application Note 93C56 instrumentation projects vhdl code download vhdl code for uart communication UART using VHDL 93C56 14 pins IC data book free download uart vhdl fpga programmed fpga diagram and description datasheet abstract |
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| Abstract: FastTrack FPGA HDL a16450 UART (Universal Asynchronous Receiver/Transmitter , MAX+PLUS II EDIF VHDL Verilog HDL EDA Partners Program ACCESSSMAltera AMPP , 6000* FPGA FLEX 6000 -3 -2 -1 LE 16 16 140 MHz 131 MHz , Time-to-Market MegaCore PCI UART FFT AMPP Altera Megafunction SM FLEX 6000 ... | Original |
4 pages, |
EPF6024A EPF6016A EPF6016 EPF6010A bga-100 0.5 100 PIN tQFP ALTERA 0.5 100-pin BGA datasheet abstract |
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| Abstract: 10. Interfacing an External Processor to an Altera FPGA ED51011-1 ED51011-1.0 This chapter provides an overview of the options Altera® provides to connect an external processor to an Altera FPGA or Hardcopy , ) interface or a simple custom bridge that you can design yourself. By including both an FPGA and a , Create dedicated FPGA resources for co-processing data Reduce design time by using IP from , Simulate System Specify Constraints Compile Design Program Device © February 2009 Altera ... | Original |
14 pages, |
uart vhdl fpga AN320 PCI Lite Interface PCI Interface Master Program AN532 mosi miso snk dsp processor design using vhdl AN343 PCI express design avalon vhdl byteenable UART using VHDL ALTERA FPGA avalon vhdl ED51011-1 ED51011-1 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| developed in VHDL for FPGA and ASIC designs. Available cores include UARTs, DMA controllers CAST focuses on maximizing the success of FPGA designs by supplying high-quality, high-value models for simulation and synthesis. CAST provides a total modeling solution for FPGA design by delivering and supporting accurate, reliable, and affordable VHDL models ready for use by designers worldwide. CAST supplies a variety of support programs, VHDL training www.datasheetarchive.com/files/xilinx/docs/wcd0000d/wcd00d70-v1.htm |
Xilinx | 17/07/1998 | 17.06 Kb | HTM | wcd00d70-v1.htm |
| cores developed in VHDL for FPGA and ASIC designs. Available cores include UARTs, DMA controllers CAST focuses on maximizing the success of FPGA designs by supplying high-quality, high-value models for simulation and synthesis. CAST provides a total modeling solution for FPGA design by delivering and supporting accurate, reliable, and affordable VHDL models ready for use by designers worldwide. CAST supplies a variety of support programs, VHDL training programs, consulting services, and www.datasheetarchive.com/files/xilinx/docs/rp00008/rp00892.htm |
Xilinx | 06/03/2000 | 14.75 Kb | HTM | rp00892.htm |
| synthesizable cores developed in VHDL for FPGA and ASIC designs. Available cores include UARTs, DMA CAST focuses on maximizing the success of FPGA designs by supplying high-quality, high-value models for simulation and synthesis. CAST provides a total modeling solution for FPGA design by delivering and supporting accurate, reliable, and affordable VHDL models ready for use by designers worldwide. CAST supplies a variety of support programs, VHDL training programs, consulting services, and www.datasheetarchive.com/files/xilinx/docs/wcd00010/wcd0102a.htm |
Xilinx | 16/02/1999 | 15.64 Kb | HTM | wcd0102a.htm |
| ac_cast_c_uart.fm Page 1 Thursday, October 8, 1998 10 -354-0325 E-Mail: info@cast-inc.com URL: www.cast-inc.com Features • Compact UART • 8 bit characters • Tx • Flexibility for adding other features Applications The C_UART core is used in serial data communications documentation Design File Formats .ngo, .XNF Netlist; VHDL Source RTL available extra Constraint Files .ncf Verification Tool VHDL Schematic Symbols Viewlogic Evaluation Model None Reference designs & application www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (compact_uart.pdf) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| new features supported for this release. New FPGA and CPLD families in the release (XC4000XLA XC4000XLA XC4000XLA XC4000XLA, XC implementation tools. Furthermore, the HDL project management capabilities provided as part of Synopsys' FPGA the industry's most powerful FPGA design tools provides dramatic improvements in the project Synopsys FPGA Express. This release of the Foundation Series enables true HDL design flows as well as mixed-language (VHDL and Verilog HDL) synthesis and optimization. Support for mixed-language design flows is becoming www.datasheetarchive.com/files/xilinx/docsan/fqs/fqs1_2.htm |
Xilinx | 12/11/1998 | 8.83 Kb | HTM | fqs1_2.htm |
| Program Available Services Overview Comit : FPGA Design Design Conversions ASIC Design & Verification System/board level design Core Customization/Integration VHDL/Verilog Models Hardware/Software co-design Specialization High speed FPGA design FPGA design optimization (size & speed) FPGA ) DSP Interleaver (XC4020-XL XC4020-XL XC4020-XL XC4020-XL) DSP Interface controller (XC4013-XL XC4013-XL XC4013-XL XC4013-XL) Specialized UART www.datasheetarchive.com/files/xilinx/docs/rp00027/rp02727.htm |
Xilinx | 06/03/2000 | 10.33 Kb | HTM | rp02727.htm |
| Program Available Services Overview Comit : FPGA Design Design Conversions ASIC Design & Verification System/board level design Core Customization/Integration VHDL/Verilog Models Hardware/Software co-design Specialization High speed FPGA design FPGA design optimization (size & speed) FPGA ) DSP Interleaver (XC4020-XL XC4020-XL XC4020-XL XC4020-XL) DSP Interface controller (XC4013-XL XC4013-XL XC4013-XL XC4013-XL) Specialized UART www.datasheetarchive.com/files/xilinx/docs/wcd00035/wcd035e8.htm |
Xilinx | 16/02/1999 | 10.46 Kb | HTM | wcd035e8.htm |
| Updated: May 6, 2002 FPSLIC - Application Notes FPSLIC-AVR AVR-FPGA Interface Designs FPSLIC-FPGA Starter Kit Tutorial IP Cores Application Design Program Note explains how to use VHDL with IP Core Generator to implement the FreeRAM inside the AT40K AT40K AT40K AT40K FPGA and Flash Memory FPGA Configuration Memory FPGA Conversion ULC FPSLIC Gate Arrays migration of AL to AX designs. UART and 2-Wire Interface Reconfiguration of the AT94K AT94K AT94K AT94K FPSLIC www.datasheetarchive.com/files/atmel/atmel/prod318.htm-v1.bak |
Atmel | 07/05/2002 | 74.52 Kb | BAK | prod318.htm-v1.bak |
| Updated: May 6, 2002 FPSLIC - Application Notes FPSLIC-AVR AVR-FPGA Interface Designs FPSLIC-FPGA Starter Kit Tutorial IP Cores Application Design Program Note explains how to use VHDL with IP Core Generator to implement the FreeRAM inside the AT40K AT40K AT40K AT40K FPGA and Flash Memory FPGA Configuration Memory FPGA Conversion ULC FPSLIC Gate Arrays migration of AL to AX designs. UART and 2-Wire Interface Reconfiguration of the AT94K AT94K AT94K AT94K FPSLIC www.datasheetarchive.com/files/atmel/atmel/prod318-v1.htm |
Atmel | 07/05/2002 | 74.52 Kb | HTM | prod318-v1.htm |
| DEVELOPING PROGRAMS AND SOLUTIONS FOR # XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION # FPGA Device FAMILY = virtex2p # virtexe / virtex2 / virtex2p DEVICE = xc2vp20 # e.g. xc2v -level name for simulation # Target System #TARGET = ml1 # ml1 / ml2 / v2pdk # FPGA Device #FAMILY -level name for simulation # Target System #TARGET = ml2 # ml1 / ml2 / v2pdk # FPGA Device #FAMILY substituting "debug" with "release" # Software Application - Hello UART SW_MAKE = make -C $(V2PRO)/source/sw/apps/hello_uart www.datasheetarchive.com/download/70419997-996008ZC/xapp640.zip (flow.cfg) |
Xilinx | 30/07/2002 | 9501.22 Kb | ZIP | xapp640.zip |