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SN74LS320J Texas Instruments 20MHz, OTHER CLOCK GENERATOR, CDIP16 visit Texas Instruments
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EL4585CS Intersil Corporation 36MHz, VIDEO CLOCK GENERATOR, PDSO16, SO-16 visit Intersil
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prbs generator using vhdl

Catalog Datasheet MFG & Type PDF Document Tags

vhdl code for 16 prbs generator

Abstract: verilog code of prbs pattern generator Application Note: Xilinx FPGAs An Attribute-Programmable PRBS Generator and Checker XAPP884 , application note describes a PRBS generator/checker circuit where the generator polynomial, the parallelism , users who want to know how to use the PRBS generator and checker. The final section, PRBS Sequences , or checks it is indicated by the term LFSR. Table 1: PRBS Generator/Checker Attributes Attribute , . XAPP884 (v1.0) January 10, 2011 www.xilinx.com 1 Standard Polynomials Table 2: PRBS Generator
Xilinx
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XC5VLX30-FF324-1 vhdl code for 16 prbs generator verilog code of prbs pattern generator VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR in PRBS prbs generator using vhdl prbs pattern generator using vhdl XC6SLX4-TQG144-2

simulation for prbs generator in matlab

Abstract: block diagram prbs generator in matlab 16-bit pseudo random binary sequence (PRBS) generator which is initialized at beginning of a Data Field. The PRBS polynomial generator is: G(16) = X16 + X13 + X12 + X11 + X7 + X6 + X3 + X + 1. The sync byte of the incoming packet marks the beginning of Data Field, and the PRBS generator is loaded with , Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL
Xilinx
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simulation for prbs generator in matlab block diagram prbs generator in matlab vhdl code for pseudo random sequence generator in vhdl code for pseudo random sequence generator pulse shaping FILTER implementation xilinx vhdl code for 7 bit pseudo random sequence generator

vhdl code for 8 bit barrel shifter

Abstract: verilog code for barrel shifter binary sequence (PRBS) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern. The , and works in parallel, while the PRBS generator is serial. The 10-bit output of the DRU is processed , Controllable via ChipScope Pro Analyzer Each of the four channels is equipped with: · A PRBS generator , specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both the generator and the checker can be found in the
Xilinx
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vhdl code for 8 bit barrel shifter verilog code for barrel shifter vhdl code for loop filter of digital PLL vhdl code for 4 bit barrel shifter ML523 vhdl code for phase frequency detector XAPP875 DS202

verilog code for barrel shifter

Abstract: vhdl code for 8 bit barrel shifter CLK_DT PRBS Generator Ideal Deserializer HF_CLK (3.11 GHz) Simulation Only NI-DRU (Unit , pseudorandom binary sequence (PRBS) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern , checker is synthesizable and works in parallel, while the PRBS generator is serial. The 10-bit output of , equipped with: · A PRBS generator continuously sending a PRBS 15 pattern. The user can force each of , the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both
Xilinx
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XAPP868 vhdl code Pseudorandom Streams Generator vhdl code for clock and data recovery verilog code for 16 bit barrel shifter verilog code of parallel prbs pattern generator 8 bit barrel shifter vhdl code vhdl code for 16 bit barrel shifter

vhdl code for ofdm

Abstract: ofdm matlab simulation block for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL
Xilinx
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vhdl code for ofdm ofdm matlab simulation block vhdl code for block interleaver 4585 dvb vhdl code for interleaver vhdl code for ofdm transmitter

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator continues, but its , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL
Xilinx
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OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm OFDM matlab program CODES vhdl code for 8 point ifft in xilinx

vhdl code for loop filter of digital PLL

Abstract: vhdl code for All Digital PLL speedsel_0 DCO 0 prbs0 PRBS Generator 0 CDR 0 rec_clk2m0 (K18) dt_out0 (AF19) CDR 1 rec_clk2m1 (AH15) dt_out1 (AG15) Common REFCLK: CLK_N (J16)/CLK_P (J17) DCO 1 PRBS Generator 1 , clock recovery and jitter attenuation functionality in the low frequency range using the SelectIOTM , ) is used to extract the clock. This LIU can be removed by using the code provided with the reference , binary sequence (PRBS) data pattern and applies a step in frequency (about a 20 ppm increase) to show
Xilinx
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vhdl code for All Digital PLL vhdl code for DCO E1 pdh vhdl vhdl code for loop filter of digital PLL spartan vhdl code for phase frequency detector for FPGA vhdl code dds

VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter here is added to a PRBS generator polynomial using modulo-2 arithmetic. This addition is performed , Figure 5. RBS Generator Table 1. PRBS Sequence State Q0 Q1 Q2 0 1 1 1 1 0 , generator will produce the sequence shown in Table 1. Serial Data-In PRBS Generator Scrambled , data over a high-speed serial connection using fiber-optic or copper cables. HOTLink was designed , such non-standard data over a serial connection using the built-in features of HOTLink and simple PLD
Cypress Semiconductor
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vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus prbs using lfsr vhdl code for a 9 bit parity generator 8B/10B CY7B923/933

vhdl code scrambler

Abstract: prbs generator using vhdl Figure 6. The data here is added to a PRBS generator polynomial using modulo-2 arithmetic. This , . Q0 D Q1 D Q2 CLK Figure 5. RBS Generator Table 1. PRBS Sequence State Q0 Q1 , generator will produce the sequence shown in Table 1. Serial Data-In PRBS Generator Scrambled , over a high-speed serial connection using fiber-optic or copper cables. HOTLink was designed , such non-standard data over a serial connection using the built-in features of HOTLink and simple PLD
Cypress Semiconductor
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vhdl code scrambler vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code for nrz vhdl code 10 bit LFSR CY7B923

vhdl code for 16 prbs generator

Abstract: vhdl code for 9 bit parity generator LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , .18 Transmit FEAC Generator , .19 Generation & Detection of PRBS , 'h2 . 28 PRBS_CTRL - PRBS control - 'h6 . 28 PRBS_INT - PRBS
Altera
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free verilog code of prbs pattern generator verilog code for pseudo random sequence generator in sonet testbench CRC-16 GR-499-CORE h60 buffer

block diagram code hamming using vhdl

Abstract: hamming test bench 802.16a standards · Optimized for Virtex®-II and Virtex-II Pro FPGAs, using structural VHDL and , to 4 Kbits, 64 possible product codes Documentation · Fully synchronous design using a , VHDL .ucf (user constraints file) Verification VHDL Test Bench VHDL Wrapper Design Tool , constituent codes. Table 2 lists the Hamming code generator polynomials supported by the core. The extended , Code Generator Polynomials n k Generator Polynomial 7 4 X3+X+1 15 11 X4+X
Xilinx
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block diagram code hamming using vhdl hamming test bench vhdl code hamming window vhdl code hamming hamming code FPGA block diagram code hamming DS211

verilog code of parallel prbs pattern generator

Abstract: , pseudo-random binary sequence (PRBS) generator and checker, and a frequency checker. All the necessary design , . The code you can reuse in the reference design is the PRBS generator, PRBS checker, and, most , TX PRBS Generator ANY PHY IP Block PRBS Checker RX Avalon Master PRBS Generator and , environment between the TX and the RX function using a PRBS as a test pattern source. The testbench checks , ) core in Stratix ® V devices using the Interlaken PHY IP interface. You can use the reference design
Altera
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AN-634-1

iodelay

Abstract: vhdl code for 16 BIT BINARY DIVIDER Jittered Clock DCM CLKIN CLKFX REFCLK BUFG MUX FILL-LEVEL PRBS Generator DCM FIFO , oscillator. A PRBS generator is driven by the multiplied CLKFX output and writes into a standard FIFO. The , from the FIFO is then checked by a PRBS checker with the same polynomial as the generator. Once both , Application Note: Virtex-5 FPGAs Creating a Controllable Oscillator Using the Virtex-5 FPGA , resolution of 80 ps per tap and are permanently calibrated using a reference clock of 200 MHz ± 10 MHz. The
Xilinx
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XAPP872 iodelay vhdl code for 16 BIT BINARY DIVIDER vhdl code for frequency divider iodelay Virtex 5 vhdl code for FFT 32 point vhdl code for multiplexer 32 BIT BINARY UG190

FSP250-60GTA

Abstract: fsp250-60gta power supply schematic a viewer tool, which you can use as reference to accelerate PCB design using the Stratix GX device , Before using the kit or installing the software, be sure to check the contents of the kit and inspect , locations. You should install the following software before you begin using the kit. Quartus® II software , Stratix GX devices using the Quartus II software, you need a special FEATURE line. Therefore, you have to , period, you will still be able to compile and simulate using these MegaCore functions, but you will not
Altera
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FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual P25-09565-00 RS-232 D-85757

XC7VH580T-HCG1155-2

Abstract: User Guide Documentation Design Files Vivadoâ"¢: RTL Example Design Verilog/VHDL Test , desired, giving many different Pseudo-random binary sequence (PRBS) and clock patterns to be sent over , communicates to the IBERT core through JTAG, using the Xilinx cables and proprietary logic that is part of the , Generation and Checking Each GTZ transceiver enabled in the IBERT design has a pattern generator and a pattern checker. The pattern generator sends data out through the transmitter. The pattern checker
Xilinx
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XC7VH580T-HCG1155-2 DS878

vhdl HDB3

Abstract: PQFP208 footprint Display is controlled by the microprocessor. The ACTEL A1460A FPGA provides a PRBS data generator , FPGA provides a PRBS generator, loopback capabilities, logic for alarm LEDs, and several timing , options are described in the Timing Options section. 3.9.2 Additional Features A PRBS data generator , `1' selects Common Backplane Timing. 23 A 2 -1 PRBS generator allows the TQUAD/EQUAD with QDSX reference design to loopback the line side T1/E1 signals. The PRBS generator is selected by DIP Switch 1
PMC-Sierra
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PM4344 PM6344 vhdl HDB3 PQFP208 footprint digital alarm clock vhdl code 74XXX139 alarm clock design of digital VHDL MLL41 TQUAD/PM6344 PMC-980328 PM4344/PM6344 PMC-951013

10Gbase-kr backplane connector

Abstract: Virtex-7 serdes Agreement and can be generated using CORE Generator tool v13.3 and higher. The CORE Generator tool is , End User License Agreement and can be generated using the Core Generator v14.1 tool and higher , Circuit (NGC) netlist VHDL, Verilog VHDL, Verilog User Constraints File (UCF) VHDL, Verilog Test Bench VHDL, Verilog Wrapper Verilog or VHDL Structural Model N/A · · Tested Design Tools Design Entry , . This IP was verified in software using pre-production speed files. For the complete list of supported
Xilinx
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10Gbase-kr backplane connector Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr DS739 10GBASE-KR 10GBASE-R 10GBASE-SR

XC7K325T-2FFG900

Abstract: XC7K325T Agreement and can be generated using the Xilinx CORE GeneratorTM system 13.3 or higher. The CORE Generator , Specification User Guide Netlist Verilog/VHDL Not Provided Xilinx Constraints and Synthesis Constraints Not , sequence (PRBS) and clock patterns to be sent over the channels. The configuration and tuning of the GTX , Analyzer tool communicates to the IBERT core through JTAG, using the Xilinx cables and proprietary logic , -7 FPGA IBERT CORE Generator tool GUI. X-Ref Target - Figure 2 '48%?#(!.%, #0, 48 28 '48%?#(!.%
Xilinx
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XC7K325T-2FFG900 XC7K325T XC7K325T specification kintex 7 XC7K325T user guide ChipScope IBERT DS855

free verilog code of prbs pattern generator

Abstract: CRC-16 LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , .18 Transmit FEAC Generator , .19 Generation & Detection of Pseudo- Random Bit Streams (PRBS , . 29 PRBS_CTRL - PRBS control - 'h6 . 29 PRBS_INT - PRBS Interrupt Status - 'h8
Altera
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digital alarm clock vhdl code in modelsim HDLC verilog code

verilog hdl code for encoder

Abstract: X9013 binary sequence (PRBS) generator whose output is XORed with the clear data stream on the transmitter side , packets remain 0x47. During the inverted sync byte interval (SYNC 1), the PRBS generator is loaded with a seed value of "100101010000000". After the seed is loaded, the PRBS generator runs continuously through , . Randomizer Disable Control: When asserted high, the output of the PRBS generator is not XORed with the data , Instantiation Templates VHDL, Verilog Reference Designs & Application Note Application Notes Additional Items
Xilinx
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verilog hdl code for encoder X9013 digital FIR Filter verilog code polyphase 171OCT QPSK using xilinx V50-4
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