NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features 1 to 7.8 Mbits memory True Dual Port/Pseudo Dual Port/Single Port Dedicated FIFO logic for all block RAM 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... | Original |
243 pages, |
DS1004 PR80C 426 b34 umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 transistor pt42c transistor pt36c PB110C pt36C DS1004 abstract |
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| Abstract: LatticeECP3TM Serial Protocol Evaluation Board Revision D User's Guide September 2009 Revision: EB44_01.1 LatticeECP3 Serial Protocol Evaluation Board Revision D User's Guide Lattice Semiconductor Introduction The LatticeECP3 Serial Protocol Evaluation Board (referred to in this document as "SPB") allows designers to investigate and experiment with the features of the LatticeECP3 high-speed SERDES transceivers. The SPB is available for full and detailed characterizat ... | Original |
46 pages, |
88E1111 config FUSE SMD L829-1J1T-43 TCO-2111 box header2x5 88E1111 marvell 88E1111 U1J SMA CW-P423 ROHM capacitor 100nf 16v 1005 x7r smd sot23-3 W32 CW-P423-156.25MHZ SMD SOT23 transistor MARK Y2 TCO2111-245.76MHZ datasheet abstract |
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| Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.6, March 2010 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 DS1006 Pre-Engineered Source Synchronous I/O Features · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support SPI4.2, SFI4 (DDR Mode), XGMII High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support DDR1: 400 (200MHz) / DDR2: 533 (266MHz) · Dedicated DQS support High Logic Density for ... | Original |
393 pages, |
c 4161 DS1006 DS1006 abstract |
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| Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.3, August 2008 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 DS1006 Pre-Engineered Source Synchronous I/O Features · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support SPI4.2, SFI4 (DDR Mode), XGMII High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support DDR1: 400 (200MHz) / DDR2: 533 (266MHz) · Dedicated DQS support High Logic Density for ... | Original |
386 pages, |
socket 1156 pinout pr77a PR68A CEI 23-50 socket am3 socket pinout CEI 23-50 226 35K capacitor datasheet L33 thermal fuse LFE2M50 marking l33 LFE2M20SE-5FN484C M33 thermal fuse PB58 DS1006 DS1006 DS1006 abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typ ... | Original |
238 pages, |
PR83a PR91A SC40 SC80 SC25 SC15 SC115 SCM15 transistor pt42c PB138 LFSCM3GA80EP1-6FC1152C pb127d PB110C transistor pt36c pr94a diode DS1004 DS1004 DS1004 abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... | Original |
237 pages, |
W32 MARKING DS1004 PB124A PL84C PR55D pr94a diode SC115 SC15 SC25 transistor pt42c BA5 904 AF P SCM15 SC80 SC40 pr82a DS1004 abstract |
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| Abstract: LatticeECP3TM Video Protocol Board Revision B User's Guide March 2010 Revision: EB39_01.3 Lattice Semiconductor LatticeECP3 Video Protocol Board Revision B User's Guide Introduction The LatticeECP3TM FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented with 16 channels of embedded SERDES/PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be suppo ... | Original |
40 pages, |
0154010.DR CS10 Citizen 0154003.DR LP3878MR-ADJ PT140 AJ8 sot K34 mosfet EXB28V102JV nC66, fuse CS10-27.000MABJ-UT MT47H128M16HG B34 diode smd smd sot23-3 W32 MT47H128M16HG-3 datasheet abstract |
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| Abstract: PB179B PT121B LCMX02280 LCMX02 LCMX02280C P 3 NC/PR97A NC/PR97A* AD34 N 3 NC/PR97B NC/PR97B* A3 AE30 P 3 PR74A/PR101A* B3 , 2 PR43E PR43E_A/PR61E A/PR61E_A/RUM0_GPLLT_FB_A G2 Y34 P 3 PR56A/PR74A* H2 Y33 N 3 ... | Original |
60 pages, |
PR88A sgmii 88E1111 D B-AG Q0N CW-P423-156.25MHZ PR65A Vishay SOT23 MARKING G7 MARKING W16 SOT23-3 ethernet phy sgmii PR83a MARKING C25 SOT23 jtag cable lattice Schematic hw-dln-3c LatticeECP3-95 FG8 SERIES DIODES datasheet abstract |
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| Abstract: LatticeMico32/DSP Development Board for LatticeECP2 User's Guide June 2009 Revision: EB26_02.6 LatticeMico32/DSP Development Board for LatticeECP2 User's Guide Lattice Semiconductor Introduction This document describes the features and functionality of the LatticeMico32TM/DSP Development Board for LatticeECP2TM devices. This board is designed as a hardware platform for design and development with the LatticeMico32 microprocessor, as well as for the LatticeMico8TM microcontroll ... | Original |
57 pages, |
K6R4016V1D ui10 LESR4 transistor c1027 C0215 MX29LV128MBTI-90Q CY7C67300 FB0701 BEL 100N K6R4016V1D 7-segment LED display 1 to 99 vhdl transistor c1026 R1004 TP0950 datasheet abstract |
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| Abstract: LatticeECP2TM Advanced Evaluation Board User's Guide January 2009 Revision: EB23_01.6 LatticeECP2 Advanced Evaluation Board User's Guide Lattice Semiconductor Introduction The LatticeECP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user designs and IP cores targeted to the LatticeECP2-50 device. The main features of this board are listed below: · LatticeECP2 FPGA with a 1.2V DC core in a 672-ball fpBGA package (default LatticeECP2-50 FP ... | Original |
45 pages, |
MDLS-40266 OPTREX 120 OPTREX C-51505 TP177 tp154 Vishay SOT23 MARKING F5 POWR1220AT8 PB58A TP194 Vishay SOT23 MARKING G7 K4T51163QG-HCE60 lcm-s02402 marking AF2 sot-23 LCM-S01602 datasheet abstract |
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