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LTC1645CS#TR Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 14; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1645CS8#PBF Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1645CS#TRPBF Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 14; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1645CS#PBF Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 14; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1645CS Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 14; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1645IS8#PBF Linear Technology LTC1645 - Dual-Channel Hot Swap Controller/Power Sequencer; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

pn sequence generator using d flip flop

Catalog Datasheet MFG & Type PDF Document Tags

pn sequence generator using d flip flop

Abstract: pn sequence generator using jk flip flop .52 Flip Flop - D Type .54 Flip Flop - Toggle , Generator Output Component Generate component only - do not output count sequence Count File , generator output option. Count sequence formatting file Filename Name of the file (found in the , . Count Sequence Output When the Generator Output option is set to Count or Both, an output file called
Atmel
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6120* PDP-8 microprocessor

Abstract: tda 7560 4 x 35 W of the internal RUNHLT flip flop on the positive transition of the RUN/HTr line. 0 6 RUN Low This , -bit flip flop that serves as a high-order extension of the AC. It is used as a carry flip flop for 2 , modified. RUN/HLT The RUN/HLT line changes the state of the RUNHLT flip flop. This flip flop Isjnltlally , not cause the RUNHLT flip flop to be cleared, but causes entry Into panel mode with the HLTFLG set , . That is, the next instruction is guaranteed to be fetched barring a reset, DMAREQ pr RUN/HCT flip flop
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H7442

Abstract: Matra-Harris Semiconductor Putte generator 4 tut trueJcomplement ISSD flip flop 28 14 1» 14 s Fig. 11 : Macrocell , \ P i I tpHL I 3 + 1000/xm m etal interconnect (3) D Flip Flop (w ith R) propagation delay , Hop R S NON (he flop j K flip flop with neg Set and Reset j K rko lo p w # t nog Set One dock OFF , OFF w«h pos Set and Reset Late* witti pos Set j K flip flop wttti pos Reset Togg« ikp nop Mtti , ns 4 input N A N D Prop. Delay tp (N A N D 2 ) 4 input NOR Prop. Delay tp (NO R4) D Flip
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bcd counter using j-k flip flop diagram

Abstract: pn sequence generator using jk flip flop o utput is subject to decoding spikes and therefore should not be used as a clock. The flip -flop s , CE CP Pn Qn Sn TC C ou n t Enable Input (A ctive LOW) C lo ck Pulse Input (Positive-G oing A ctive Edge) Preset D ata In p u ts F lip -flo p O u tp u ts Veci ^ 1 2 14 15 2 3 (2) (3) (6) (7) V CC1 , C Ve e C M Li - -C O U N T UP (p li - -C O U N T D O W N © f* iy © -© -© - M ^ W , llo w s a straightforw ard binary sequence. The F10137 fo llo w s the 8421 BCD sequence, as indicated
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F10136 bcd counter using j-k flip flop diagram pn sequence generator using jk flip flop ECL Handbook F10536 F10537 F10136/F10536 F10137/FI

logos 4012B

Abstract: 1LB553 Section 3 the Type Number index is arranged in numeric sequence using the basic type numbers stripped o f , EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY SEM IC O N IN D EXES LIMITED THE , VOLUME 3 D IG ITA L & ANALOGUE I.C. TH E SEMICON INDEXES VOLUME 3 5th E D I T I O N 1985 Revised June 1985 IN T E R N A T IO N A L INTEGRATED CIRCUITS IN D E X CONTENTS SECTION , DIAGRAMS, OUTLINES, TTL SERIES 54/7400 ABBREVIATIONS COMPILED A N D PUBLISHED BY SEMICON INDEXES L IM
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logos 4012B 1LB553 Rauland ETS-003 Silec Semiconductors 4057A transistor sr52 IEC179 TDA1510 TDA1510A

7400 fan-out

Abstract: 16 bit comparator using 74*85 IC Copyrighted By Its Respective Manufacturer Silicon-Gate HCMOS Logic Arrays LL 3000 Series _ ANY FLIP FLOP ANY FLIP FLOP «V v* ' * -v- H- »'-i'-' TI TE° "~1 TI TE° """} TI Ti Li»J i 11 J. ."â ! â  " â"¢ ANY M ACROFU NOTION CONTAINING FLIP FLOPS QD TE ' â . râ'"v: - ' ; ouynir ajHHHH , of arrays are manufactured using a proven 3.5-micron, oxide-isolated silicon-gate HCMOS fabrication , can be configured into a variety of logic elements such as exclusive-OR gates or flip-flops using
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7400 fan-out 16 bit comparator using 74*85 IC IC 7400 SERIES ALL DATA IC 7400 SERIES list IC TTL 7400 propagation delay lsi ll3000 LL3000

Matra-Harris Semiconductor

Abstract: MB-7500 ) (1)12) 2.5 3.7 4.3 4.9 ns 4 input NOR Prop. Delay tp (NOR4) (1X2) 4.2 5.8 6.7 7.7 ns D Flip , Flip Flop (with R) propagation delay is corresponding to propagation delay between clock , Outline part number gat ny compi standard E (1) .exity using ram number of rows max. i/o pads dedicated , external RC or Crystal oscillator (see AN 1023 "A design guide for oscillators using MHS gate Arrays"). ON , discharged through an N-Channel transistor in the CMOS P-N pair. When such switching takes place at a
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Matra-Harris Semiconductor MB-7500 pn sequence generator using d flip flop H749 H741 matra harris gate array

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram ) 7404 EL 1 2 SET G1 DFFS GND PN D CLBMZ DFFS Q QN RN SN DN CK FF1 Q0 QN0 RO0 SO0 DO0 DFFS Q QN RN SN DN PN D CK Q1 QN1 RO1 SO1 DO1 FF2 PN D , QN2 RO2 SO2 DO2 Q QN RN SN DN PN D CK FF4 Q3 QN3 RO3 SO3 DO3 Philips , achieve the function. Figure 2 shows two consecutive D flip-flop fusing images. Note that asynchronous , . Two Flip-Flops Implemented in the NAND Foldback Strucutre One straightforward example of using a
Philips Semiconductors
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full 18*16 barrel shifter design IC 3-8 decoder 74138 pin diagram full adder using ic 74138 TTL SN 7404 12 bit comparator images of pin configuration of IC 74138 PLHS501 AN049
Abstract: Considerations. 24 Configuration Using the SPI , using the fast detect output bits of the ADC. If the input signal level exceeds the programmable , . All of these features can be programmed using a 1.8 V to 3.4 V capable 3-wire serial port interface , ° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE , . 0 | Page 13 of 64 13015-008 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK Analog Devices
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AD9684 PKG-004472 MO-275-GGAB-1 196-B BP-196-3 AD9684BBPZ-500

str w 6556 equivalent

Abstract: str x 6556 CPU to alternately run and halt by changing the state of the internal RUN/HLT flip flop. 7 RESET L , '"DXo- 28 dx, See Pin 16â'"dx0. 29 LINK H Unk flip flop. 30 DEVSEL L Device Select for I/O transfers. 31 , 8052/7101 - 31/2 Digit A/D Pair. 113 8052A/7103A - 41/2 Digit Pair . 121 , using 12-bit, two's complement arithmetic. The processors recognize the instruction set of Digital , crystal can be removed and the processor clocked by an external clock generator. A 12
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IM6523 str w 6556 equivalent str x 6556 tv power supply str 6556 str w 6556 str w 6556 a IM6100 IM6101/6101A IM6102 IM6312/6312A IM6402/6403 IM6508/6518

ICM72171

Abstract: CD4013 UP DOWN COUNTER uses an ICM7213 precision one minute/one second timebase generator using a 4.1943MHz crystal for , digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is , output of the flip flop goes high and turns on the NPN transistor, thereby inhibiting leading zero , 28] SEG d 27] SEG b 26] SEG f 25] SEG C E]vdd 23] SEG a 22] SEG e 21] SEG g 20] DISPLAY CONT. il , SCAN A B C D E F G D4 D3 D2 D1 9-13 ICM7217 Absolute Maximum Ratings Supply Voltage (VDD - VSS
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ICM7109 ICM72171 CD4013 UP DOWN COUNTER 2N6034 ICM7217IJI three digit common anode multiplexed 7-segment display 1943MH 24288MH ICM7207A CD4011

dh3ad

Abstract: FD1771 ).2-4 Ready/DMA Speed Selection-2-4 End-of-Process Flip/Flop.2-5 Power-On Hold , First/Last Flip/ Flop.3-51 Master Clear.3-51 Floppy Disk Formatter , /FLOP The End-of-Process flip/flop is normally set by the EOP output from the DMA controller; however, when a jumper is installed between pins 101 and 102, the EOP flip/flop can be set as a result of the INTREQ (FD1771). When this jumper is installed, either EOP (Am9517) or INTREQ (FD1771) sets the flip/flop
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dh3ad am9517 CR2 D312 25LS2520 74ls04 pin diagram TTL 74LS11 00680108C

mc4001

Abstract: MC4040 Quad Type D Flip Flop MC4315F.L MC4015F,L,P 10 16 190 Programmable Module-N Decade Counter MC4316F.L , DIAGRAM One flip flop shown Only inputs shown on block diagram are present. 111 This Material , Segment Character Generator - MC4039F,L,P 240 Binary to Two-of-Eight Decoder - MC4040F,L,P 200 Single-Error Hamming Code Detector and Generator - MC4041 F,L,P 240 Quad Predriver MC4342F.L MC4042F,L,P . , "0" (Sense "0"> - OPERATING SEQUENCE -FIGURE 1 - READ MODE TIMING DIAGRAM X, Y Select Lines Sense Output
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mc4001 MC4040 MC4060 MC4052 BCD to Seven Segment 4055 diagram of LED matrix using 4017 MC4300/MC4000 MC4300F MC4000F MC4001 MC4302F MC4002F

PT3983

Abstract: FS22-101Y4 both ACK and COL are logic low when asserted. The D type flip flop is used to synchronize the reset , ± Preamble Phase = Locked Loop TP Port 0 Jam Sequence FIFO Control Manchester Encoder RXD , generate the Collision Jam sequence independently. Data Out Output AUI port differential driver , generator uses a 20 MHz crystal attached to pins X1 and X2. Alternatively, an external 20MHz CMOS clock , Crystal 2 Crystal Connection The internal clock generator uses a 20 MHz crystal attached to pins X1 and
Advanced Micro Devices
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PT3983 FS22-101Y4 Valor Electronics pt3983 78z1122b-01 Pulse Transformers tp 12 SMD fuse BA 79C982 79C980 79C981 10BASE-T 10BASE-5 10BASE-2

FD1771

Abstract: 3A050C -2-4 End-of-Process Flip/Flop.2-5 Power-On Hold.2-5 Hold Request/Bus Priority In , »-3-49 Software Commands.3-51 Clear First/Last Flip/ Flop.3-51 Master Clear , . 2-13. END-OF-PROCESS F:LIP/FLOP The End-of-Process flip/flop is normally set by the EOP output from the DMA controller; however, when a jumper is installed between pins 101 and 102, the EOP flip/flop can be , (FD1771) sets the flip/flop. The OEM version of the FDC board is shipped without this jumper installed
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3A050C U2829 E610 ADE 408 008E AM9716 25LS2521

PE-65467

Abstract: are logic low when asserted. The D type flip flop is used to synchronize the reset signals to both , Design using Minimum Mode Am79C982 1-23 AM D B X1 PRELIMINARY TCK (Note 1) CRS , for PCI Systems 1 -4 Am79C982 CONNECTION DIAGRAM 3 a H ^ D X X )< i "0 < O o < u u o p w , 00 " n J 0) (J\ > C O to - 00 03 C O M 00 i CI+ C lDI+ D lRXD0+ RXDOAVSS RXD1+ RXD1 , < 0 ® ' ' j 0 >tn DVssC STR C DVSS Q CRS si c SCLKC TEST o 3 m o II DVd d C Xi
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PE-65467 10BASE-F

Fairchild dtl catalog

Abstract: Fairchild 9960 nixie driver 15 MHz Binary Elements RS Flip Flop Buffered JK Flip Flop Dual Flip Flop AC Coupled Flip Flop Type D Flip Flop Dual Rank Flip Flop One Half Shift Register With Inverter One Half Shift Register , % B 10 % 15% C D 10 - 10 % 15% % 15% E 10 % 15% F 10 % CLOCK PIN WAVEFORMS (For 931 Test Sequence , CIRCUITS I.C. Index â'" Numerical Sequence 1-1 I.C. Index by Family 2-1 A. Compatible Current Sinking Logic , '" Products to be Announced 5-37 D. Linear Integrated Circuits Numerical Index of Devices 6-1 Cross Reference
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Fairchild dtl catalog Fairchild 9960 nixie driver fairchild micrologic MARKING code WMM RF transistor UL903 gi 9644 diode BR-BR-0034-58

NE555 AN170

Abstract: an170 philips e predom inance o f Q 15 on the base o f Q 16, controlling the state o f th e bistable flip -flop . , and NE556 applications AN170 Square Wave Tone Burst Generator D epressing the pushbutton provid , DC-to-DC Converter V Ramp Generator F ig u re 32. D C -to-D C C o n v e rte r D ecem ber 1988 , per half hou r to 500kH z can be realized. D uty cycles can be adjusted from less than one percent to , com parators; a resistive voltage d ivider reference; a bistable flip-flop; a discharge transistor
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NE555 AN170 an170 philips 74L00 ne555 Bistable car tachometer using 555 timer burglar alarm ic 555 NE555

nec 2114

Abstract: PD17005 /driver, A /D converter, D /A converter (PWM output), and clock generator ports. Consequently, a high , · · · · · Clock generator port (CGP) · 4 .4 4 ;us (using 4 .5 M H z quarts oscillator) 7 levels , ariable D u ty Pulse) and SG (Signal Generator) functions LCD controller/driver · 3 0 segments, 2 common 1 , NOTES ON USING D ATA MEMORY . , . 165 D ATA BUFFER AND TABLE REFERENCE NOTES ON USING D ATA BUFFERS
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PD17005 nec 2114 uPD17005 NEC 743 kss delay line ms-19 OC500 poe PD17003A PD17P005

DM8570

Abstract: DM9093 ) . DM54174/DM74174 (SN54174/SN74174) Hex D Flip Flop , . 1-143 DM7512/DM8512 Dual Gated Master/Slave JK/D Flip Flop , .1-195 DM 7613 DM8613 Quad Gated D Flip Flop , Flop with Separate Clocks. (SN54H74/SN74H74) Dual D Edge-Triggered Flip F lo p , . DM54L74/DM74L74 (SN54L74/SN74L74) Dual D Flip Flop
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DM8570 DM9093 DM8520 CV 7599 diode lm5534 logic diagram of 74185 54L/74L AN-12 DM7200/DM8200 AN-17 AN-22 AN-35
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