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CDCS503IPWRQ1 Texas Instruments IC PLL BASED CLOCK DRIVER, Clock Driver visit Texas Instruments
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pll circuit by bjt

Catalog Datasheet MFG & Type PDF Document Tags

microwave transceiver

Abstract: abstract for wireless communication system increasing the bias current or by using higher-Q components in the LC resonator circuit. Note, however , minimized. Some PLL circuit examples will be used to highlight these points in the next section. more , describes the performance improvements which can be obtained by its utilization in mixed-signal microwave circuits and systems. By way of examples, the article highlights the fact that the combination of , paper aims to highlight the advantages obtained by use of a mature SiGe BiCMOS technology in RF and
IBM
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IOB12

Abstract: 49mhz toys input mode Works with IOB4 by adding a RC circuit between IOB2 set as inverted output Feedback , by adding a RC circuit between IOB3 set as inverted output them to get an OSC to EXT2 interrupt , V2VREF IOA[6:0] (7-channel LINE_IN) GPCE060A Application Circuit (LINE_IN and with BJT amplifier , believed to be accurate and reliable. Information provided by GENERALPLUS However, GENERALPLUS , responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third
Generalplus Technology
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SPCE060A IOB12 49mhz toys gpy0030a GPY0029A datasheet 49mhz fm transmitter receiver circuit PLCC84

HL04

Abstract: SPCE040A1 application needs. Basically, the system clock is provided by PLL and programmed the standby mode , Output2 IOB3 set as input mode Works with IOB5 by adding a RC circuit between IOB3 set as , . can be obtained from EXT1 (EXT2) by simply adding a RC circuit An INT (TimerA/TimerB) signal is , amplifier circuit is capable of reducing common mode noise by transmitting signals through differential , [6:0] 220 µ GPCE040A1 Application Circuit (MIC_IN and with BJT amplifier, for 3-battery use
Generalplus Technology
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SPCE040A1 HL04 xx01B GPY0030 S200

ax 2008 lqfp 48

Abstract: GPCE060A 6.3.1.1. System clock application needs. Basically, the system clock is provided by PLL and , (Negative-edge Triggered) IOB2 set as input mode Works with IOB4 by adding a RC circuit between IOB2 set , with IOB5 by adding a RC circuit between IOB3 set as inverted output them to get an OSC to EXT2 , noise by transmitting signals through differential accepted, IC will turn the system clock (PLL) off , ] GPCE060A1 Application Circuit (MIC_IN and with BJT amplifier, for 3-battery use only) 220 µ MAY 23
Generalplus Technology
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ax 2008 lqfp 48 GPY0030A HS011 Microphone amplifier XTAL 32.768MHz SPCE060A1

GPCE040A

Abstract: HL04 . Basically, the system clock is provided by PLL and programmed standby mode. The initial CPU clock is , IOB4 by adding a RC circuit between IOB2 set as inverted output Feedback Output1 them to get , ) Feedback Output2 IOB3 set as input mode Works with IOB5 by adding a RC circuit between IOB3 set as , . can be obtained from EXT1 (EXT2) by simply adding a RC circuit An INT (TimerA/TimerB) signal is , MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through
Generalplus Technology
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GPCE040A GPCE SPCE040A

SPCE061A

Abstract: SPY0030A ) Basically, the system clock is provided by PLL and programmed for low power application needs. To , (Negative-edge Triggered) IOB2 set as input mode Feedback Works with IOB4 by adding a RC circuit between , counting from N, N+1, N+2, . through can be obtained from EXT1 (EXT2) by simply adding a RC circuit , the system clock (PLL) on. The MIC amplifier circuit is capable of reducing AD needs to select , 5.1K 5000p 0.1µ 47µ 470K IOA[6:0] SPCE061A Application Circuit (MIC_IN and with BJT
Sunplus Technology
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SPY0030A 70733 36v DC MOTOR SPEED CONTROLLER schematic SPCE spy0030 DAC-213

SIEMENS saw filter f2

Abstract: CFUCG455D .4 LAYOUT SKETCHES, ASSEMBLY DRAWINGS AND CIRCUIT DIAGRAM , by keystrokes. Technical features: RF power up to 2.5mW (4dBm) programmable in 1dB steps -110 , controlled by PC Selectable 3V or 4-10Vunregulated voltage supply inputs This user manual describes how , contain the following items: Evaluation circuit boards (PCB) 2 ex CC900 single chip transceiver 5 ex , includes an evaluation circuit board (PCB) with the following items: · A SmartRF® CC900 chip. ·
Chipcon
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SIEMENS saw filter f2 CFUCG455D SIEMENS saw filter C121-C123 matsushita 455KHz ceramic filter Variable resistor 10K ohm CC900DK N-0349

bluetooth transmitter receiver ic

Abstract: Qualcomm, MSM Radio Programming and Control SiW1722 BLUETOOTH® RADIO MODEM Qualcomm MSM ASIC Reference PLL Reference Clock Ext Power CLK Circuit Analog Regulator Digital Regulator Product Description , Loop (PLL) capable of accepting various reference clock frequencies. The level of integration enables a low system cost with fewer external components. The SiW1722 is packaged in a 5-by-5-mm, Pb-free, 32 , Modem Optimum Technology Matching® Applied Si BJT Si Bi-CMOS GaInP/HBT GaAs HBT SiGe HBT GaN HEMT
RF Micro Devices
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bluetooth transmitter receiver ic Qualcomm, MSM QUALCOMM QFN RF micro designed in at Qualcomm qualcomm RF W1722

VHF transmitter circuit

Abstract: uhf TRANSMITTER CIRCUIT DIAGRAM ables the transmitter output when the PLL is out-of-lock. Optimum Technology Matching® Applied P ackage Style: QFN, 16-Pin, 4 x 4 sf Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Features · Fully Integrated PLL Circuit · , Security Systems Product Description The RF2514 is a monolithic integrated circuit intended for use as , Inhibit Circuit Ordering Inform ation RF2514 RF2514 PCBA VHF/UHF Transmitter Fully Assembled
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OCR Scan
VHF transmitter circuit uhf TRANSMITTER CIRCUIT DIAGRAM block diagram PLL fm transmitter am transmitter circuit diagram FM transmitter ISM 916MH 318MH

F2516

Abstract: block diagram PLL fm transmitter Technology Matching® Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: SSOP-16 Features · Fully Integrated PLL Circuit · Integrated V , integrated circuit intended for use as a low-cost AM/ASK transmitter. The device is pro vided in a 16 , transmitter output when the PLL is out-of-lock. 0.0688 0.0532 NOTES: 1. Shaded lead is Pin 1. 2. All , Capability · 100M H z to 5 0 0 M H z Frequency Range · Out-of-Lock Inhibit Circuit Ordering Inform ation
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F2516 AM Transmitter block diagram 2n001 block diagram fm transmitter RF2516 QSOP-16 433MH 57734MH

GPCE063A

Abstract: GPCE063 AGC 15 17 IO AGC by pass filter (refer to application circuit) VMIC 22 24 O , first. 6.3.1.1. System clock Basically, the system clock is provided by PLL and programmed wakeup , IOA8 by adding a RC circuit between them to get an OSC to EXT1 interrupt Set IOA9 as inverted , IOA12 SPI CS IOA13 IOA14 Work with IOA10 by adding a RC circuit between them to get an OSC to , EXT1 (EXT2) by simply adding a an appropriated clock source. RC circuit between IOA8 (IOA10) and
Generalplus Technology
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GPCE063A GPCE064A GPCE063 GPY0029B gpce064 LQFP64

crystal 7.15mHZ

Abstract: micro vco vhf low voltage 10- 0 ^ Si BJT Si Bi-CMOS GaAs HBT GaAs MESFET Features · Fully Integrated PLL Circuit · Integrated VCO and Reference Oscillator · 2.7V to 5.0V Supply Voltage · Low Current and Power , Source The RF2510 is a monolithic integrated circuit intended for use as a low-cost Frequency , 0 ii load, no output attenuator To maintain PLL lock PLL and Prescaler Prescaler Divide Ratio VCO Gain, ^vco PLL Phase Noise Harmonics Reference Frequency Crystal Frequency Spurs Max Crystal Rs
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crystal 7.15mHZ micro vco vhf low voltage 915MH 300MH 1000MH RFMDS00067

bluetooth transmitter receiver circuit diagram

Abstract: internal diagram of external modem Reference PLL Modem Clock Generator Analog Regulator SPI XTAL Circuit Ext Power Digital , Supports multiple external reference clocks or crystal frequencies with onchip reference PLL. · , pins reduce system BOM cost by eliminating a balun. On-chip RX/TX switching eliminates external RX/TX , VCO/ PLL PWR CNTL 0 RF_OUT DRIVER 90 DAC GFSK MODEM RX_TX_DATA CD_TXEN IDAC DAC Control XTAL_P/CLK XTAL_N BB_CLK VTUNE PLL Control Clock Generation and Distribution System Control
RF Micro Devices
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bluetooth transmitter receiver circuit diagram internal diagram of external modem CIRCUIT DIAGRAM FOR WIRELESS DATA MODEM 8 pin ic used for bluetooth noise figure of a wireless modem bluetooth transmitter circuit diagram W1711

mobile nokia circuit diagram

Abstract: bluetooth transmitter receiver circuit diagram crystal frequencies with onchip reference PLL. · Direct-conversion architecture with no external channel filter or VCO resonator components. · Single-ended RX/TX pins reduce system BOM cost by eliminating a , and Power Distribution LNA RF_IN 0 90 ADC ADC VCO/ PLL PWR CNTL 0 RF_OUT DRIVER 90 DAC GFSK MODEM RFBUS1 IDAC DAC Control XTAL_P/CLK XTAL_N BB_CLK VTUNE PLL Control Clock Generation and , incorporates analog and digital voltage regulators, a reference Phase Lock Loop (PLL) to enable multiple input
RF Micro Devices
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mobile nokia circuit diagram NOKIA VCO nokia rf power supply diagram nokia nokia cmos bluetooth programming W1713

D178004A

Abstract: PD178018A U M IM o n c c i MOS INTEGRATED CIRCUIT f i D178004A, 178006A, 178016A, 178018A 8-BJT , tuning, a PLL frequency synthesizer and a frequency counter. The /iPD178P018A, one-time PROM or EPRO M , interface, timer, frequency counter, power-ON clear circuits. On-chip hardware for a PLL frequency , sources: 17 Supply Voltage: V dd = 4.5 to 5.5 V (during PLL operation) V dd = 3.5 to 5.5 V (during CPU , (including when this mode is implemented by program without using the peripheral hardware), consult your
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PD178018A d1780 PD178004A PD178006A PD178016A 78K/0 PD178P018A

SPCE061A

Abstract: for low power application needs. Basically, the system clock is provided by PLL and programmed , input mode Feedback Works with IOB4 by adding a RC circuit between IOB2 set as inverted output , (Negative-edge Triggered) IOB3 set as input mode Feedback IOB3 Works with IOB5 by adding a RC circuit , be obtained from EXT1 (EXT2) by simply adding a RC circuit FFFF. between IOB2 (IOB3) and IOB4 , command is accepted, IC will turn the system clock (PLL) off. common mode noise by transmitting
Sunplus Technology
Original
QPF84

power bjt advantages and disadvantages

Abstract: 915MHz Spread Spectrum -186 bilities are exploited by the RF2908, 915MHz spread spectrum receiver with PLL frequency synthesizer , RFIC, the designer is faced with many choices including: the package; the circuit topology; and, the , is enhanced by a large experience base coupled with an in-depth knowledge of the application and , Transmitter (Si BJT); and, SiGe. The relative strengths and weaknesses of each technology determine the , . TECHNICAL NOTES AND ARTICLES 13 Si BiCMOS and Si BJT are widely used process technologies for RFICs
RF Micro Devices
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TA0037 power bjt advantages and disadvantages 915MHz Spread Spectrum small signal BJT transistor common base bjt GaAs MESFET amplifier

nfc19

Abstract: the PLL is out -of -lock. 1 .157 .150 .009 .010 .004 .012 .008 .196 .189 .025 .244 .228 8°MAX 0°MIN .069 .053 .050 .016 .010 .008 !" Si Bi-CMOS Si BJT GaAs HBT GaAs MESFET · Fully Integrated PLL Circuit · Integrated VCO and Reference , Systems The RF2516 is a monolithic integrated circuit intended for use as a low-cost AM/ASK , Current and Power Down Capability · 100MHz to 1000MHz Frequency Range · Out-of-Lock Inhibit Circuit 1 2
RF Micro Devices
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nfc19 100MH
Abstract: PLL Circuit â'¢ Integrated VCO and Reference Oscillator â'¢ 2.7 V to 5.0 V Supply Voltage â'¢ Very , TBD 17 50 dBc/Hz MHz n -40 +40 The PLL lock time is set externally by the bandwidth , .157 .150 The RF2510 is a m onolithic integrated circuit intended for use as a low-cost Frequency , 0454 http://www.rfmd.com 11-1 TRANSCEIVERS g f Si BJT Absolute Maximum Ratings Rating , ms 2 200 Differential 1 k£2 load Single-ended 1 k i l load PLL and Prescaler Prescaler -
OCR Scan

SPCE061A

Abstract: GPCE061A power Basically, the system clock is provided by PLL and programmed application needs. by the , IOB5 by adding a RC circuit between IOB3 set as inverted output Output2 them to get an OSC to , through can be obtained from EXT1 (EXT2) by simply adding a RC circuit FFFF. between IOB2 (IOB3 , amplifier circuit is capable of reducing common mode noise by transmitting signals through differential , INC. is believed to be accurate and reliable. Information provided by GENERALPLUS However
Generalplus Technology
Original
GPCE061A gpce061 SPCE061A 80 PROBE-T-33 49MHz FM transmitter
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