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CD4046BNSR Texas Instruments CMOS Micropower Phase-Locked Loop 16-SO -55 to 125 visit Texas Instruments Buy
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5962-9466401MEA Texas Instruments CMOS Micropower Phase-Locked Loop 16-CDIP -55 to 125 visit Texas Instruments

pll 565

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Frequency Synthesizer 50â"¦ KSN-585A-119+ 565 to 585 MHz The Big Deal â'¢ Low phase , 565 to 585 MHz for CDMA cellular base station application. The KSN-585A-119+ is packaged in a metal , Surfaceà¸'Mount Frequencyà¸'Synthesizer KSN-585A-119+ class="hl">565 to 585 MHz Features â'¢ Integrated VCO + PLL â'¢ Low phase noise and spurious â'¢ Robust design and construction â'¢ Low operating voltage (VCC VCO=+5V, VCC PLL=+5V) â'¢ Small size 0.80" x 0.58" x 0.15" CASE STYLE Mini-Circuits
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DK801 TR-F28 PL-249 TB-567 ENV03T2

pll 565

Abstract: ADF4118 -585A-119+ 565 to 585 MHz Features · Integrated VCO + PLL · Low phase noise and spurious · Robust design and construction · Low operating voltage (VCC VCO=+5V, VCC PLL=+5V) · Small size 0.80" x 0.58" x , Frequency Synthesizer 50 KSN-585A-119+ 565 to 585 MHz The Big Deal · Low phase noise and , Product Overview The KSN-585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz , General Description The KSN-585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz
Mini-Circuits
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pll 565 ADF4118 565 application frequency synthesizer 56497

adl537x

Abstract: MO-220-VNND-4 suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital , : ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516 , CLK_SEL PLL CONTROL PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT POWER-ON RESET MULTICHIP , CONSUMPTION 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 CVDD18 DVDD18 Power-Down Mode (Register 0x01 =
Analog Devices
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MO-220-VNND-4 adl537x D8P analog devices AD9122-EP ADL537 AD9122 CP-72-7 AD9122SCPZ-EP

pll 566

Abstract: pll 565 application EM78567/566/565 Manual ;= PLL = 0X06 RF = 0X0F , ) 5639977 FAX: (03) 5630118 EM78567/566/565 Manual EM78P567/566/565 Manual EM78R567 SPEC , capacitor 0.01u to 0.047u with GND . External interrupt 1 EM78567/566/565 Manual INT6 INT7 P7 , disable/enable internal pull low. 2 EM78567/566/565 Manual ICE TOP VIEW LEFT SIGHT 1 2 JP1 , /AD2 P93/AD1 P92/DAOUT P91 JP3 connection 1999/Jun/14 3 EM78567/566/565 Manual ICE
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ICE567 EM78565 EM78566 EM78567 pll 566 pll 565 application DJZ capacitor CA1310 CA10 CA12 EM78567/566/565 EM78P567/566/565

PLL IC 565

Abstract: plerowTM APL0565-T PLL Synthesizer Module · 7dBm Output Level at 565 MHz The plerowTM PLL , 50 MHz to 6 GHz. ASBâ'™s PLL provides exceptionally low spurious and phase noise performance with , Specifications Parameter Unit Min. Typical Max. Frequency Range MHz 555 565 575 , = 25ï'°C, VCC = 5 V, Freq. = 565 MHz, 50 ohm system. 1/2 www.asb.co.kr June 2010 plerowTM APL0565-T PLL Synthesizer Module Outline Draw- ing 2/2 www.asb.co.kr June 2010
Advanced Semiconductor Business
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PLL IC 565

565 pin diagram

Abstract: F562 F2MC-16LX MB90560/565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to
Fujitsu
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DS07-13715-3E 565 pin diagram F562 565 pin dETAILS ocs4 565 PLL AF9704 MB90560/565 F2MC-16L F0204

T614F

Abstract: pll 565 * 5.65 4.30 3.28 PLL+ All 1 Yes VCO Sigma- No Delta 1168-1395, LMX2531LQ2570ECT-ND , 2170-1395 LMX2505LQ1321TR-ND§ 3744.80/1,000 PLL+ 6.34 LMX2512LQ0967CT-ND* 5.65 4.30 , Wire- Inte- Integrated Frequency PLL less grated Loop RF IF Range Digi-Key Type Std. VCOS Filter PLL PLL (MHz) Part No. PLL with VCO Wire- Inte- Integrated Frequency PLL less grated Loop RF IF Range Digi-Key Type Std. VCOS Filter PLL PLL (MHz) Part No. PLL
Nearson
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S467AH-915S 730-1012-ND SG101N-915 730-1017-ND 730-1020-ND T614F loop Antennas vhf 433 Mhz VCO PLL S151FL-5-RMM-2450 765 PLL PLL 2400 MHZ LMX2525LQ1321CT-ND LMX2531LQ1700ECT-ND LMX2531LQ1700ETR-ND LMX2525LQ1321TR-ND LMX2531LQ1650ECT-ND LMX2531LQ1650ETR-ND

565 PLL

Abstract: DIP-64P-M01 F2MC-16LX MB90560/565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to
Fujitsu
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DIP-64P-M01 FPT-64P-M06 FPT-64P-M09

FF201

Abstract: programmable timer F2MC-16LX MB90560/565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to
Fujitsu
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FF201 programmable timer
Abstract: F2MC-16LX MB90560/565 Series MB90561A/562A/F562B/V560/567/568/F568 I DESCRIPTION The MB90560/565 , '¢ Internal oscillator circuit and PLL clock multiplication circuit â'¢ Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the , instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) â Fujitsu
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DS07-13715-5E

MB90F562BP

Abstract: DS07-13715-5E F2MC-16LX MB90560/565 Series MB90561A/562A/F562B/V560/567/568/F568 DESCRIPTION The MB90560/565 , oscillator circuit and PLL clock multiplication circuit · Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation , execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) · Maximum CPU
Fujitsu
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MB90F562BP MB90561APMC MB90F562BPMC MB90560 MB90F562 MB90F562B

FTP-64P-M09

Abstract: DIP-64P-M01 F2MC-16LX MB90560/565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to
Fujitsu
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FTP-64P-M09 DDR4 jedec DS07-13715-2E

stg170

Abstract: CH8398 for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , triple 256 x 6-bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A pixel bus , BIOS or driver software can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode
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stg170 CH8398 TQD4133 ATT20C498 T004133

gi 9440 diode

Abstract: CH8398 features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68 , -bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the simultaneous
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gi 9440 diode 7S1 zener diode 1N4733A

gi 9440 diode

Abstract: CH8398 "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the simultaneous
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D0023E

AM DEMODULATOR USING PLL 565

Abstract: NE565 PLL Signetics AN 183 Circuit Description of the NE565 PLL Application Note Linear Products CIRCUIT DESCRIPTION OF THE NE565 PLL The 565 is a general purpose PLL designed to operate at frequencies , counter for frequency m ultiplication applications. W ith the 565, it is also possible to break the toop , utput o f the Schm itt trigger. The com ple te circuit for the 565 is show n in Figure 2. T ransistors Q , connecting them to Pins 6 and 7. The free-running center frequency o f th e 565 is adjusted by m eans o f R
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AM DEMODULATOR USING PLL 565 NE565 PLL CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 AM DEMODULATOR USING ne565 circuit diagram PLL NE565 565 PLL pin diagram AN183

PLL IC 565

Abstract: for PLL IC 565 °C operating temperature range 1 Patented, self-acquiring PLL GaAs IC design â  Available in standard frequencies: 100,155.52, 250, 565, and 622.08 Mbit/s. Custom frequencies available upon request. â'¢ PLL , (GBLj GigaBit Logic 16G041-H Low Power, PLL Clock & Data Recovery Circuit 100 to 625 Mbit/s , -H integrates GigaBit's 16G041 PLL clock and data recovery GaAs IC together with a high performance loop filter and other components to realize a complete, 3-terminal (data in, clock and data out) PLL clock
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for PLL IC 565 lock range of 565 PLL IC 0420 LOP FO56 ic 565 advantages 16G041-HA 10G041A
Abstract: SHEET DS07-13715-5E 16-bit Proprietary Microcontrollers CMOS F2MC-16LX MB90560/565 Series MB90561A/562A/F562B/V560/567/568/F568 â  DESCRIPTION The MB90560/565 series is a general-purpose 16 , FUJITSU Flexible Microcontroller. â  FEATURES â'¢ Clock â'¢ Internal oscillator circuit and PLL , clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by Fujitsu
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Signetics NE561

Abstract: AM DEMODULATOR USING PLL 565 of a single external component. Signetics makes three basic classes of single-chip PLL circuits', the general pur pose PLL, the PLL with an added m ultiplier and the PLL tone decoder. The 560N. 562N and 565 , synchronous reception o f radio signals using PLL techniques was de scribed (Ref. 1) in the early thirties , of transistors. This com plexity made PLL techniques im practical or uneconomi cal in the m ajority , frequency-to-voltage transfer character istic. The 561N contains a complete PLL as those above, plus the additional m
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Signetics NE561 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco

pll 565

Abstract: PLL 40 kHZ 2009 9 17 VCXO - MH -( ) (VCXO) 600 MHz700 MHz 7.0×5.0mm 1/10 10fs (VCXO)NV7050SA MHz PLL PLL PLL 1/41/5 () NV7050SA 3,000 5,000 Typ. 7.0 ´ 5.0 ´ 1.6 (mm) 170 MHz to 700 MHz +3.3 V ±10 % Max. ±50×10-6 APR (Absolute Pull range) Min. ±100×10-6 , ) () (rms) NV7050SA () (PLL ) 12 kHz to 20 MHz 38.0 fs 210.0 fs 50 kHz to 80 MHz 56.5 fs 220.0 fs APR () APR TEL 03-5453-6751 FAX 03-5453-6756 E-Mail
Nihon Dempa Kogyo
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PLL 40 kHZ
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