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LMC568CMX/NOPB Texas Instruments IC PHASE LOCKED LOOP, PDSO8, M08A, PLL or Frequency Synthesis Circuit ri Buy
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pll 565

Catalog Datasheet Results Type PDF Document Tags
Abstract: 2009 9 17 VCXO - MH -( ) (VCXO) 600 MHz700 MHz 7.0-5.0mm 1/10 10fs (VCXO)NV7050SA NV7050SA MHz PLL PLL PLL 1/41/5 () NV7050SA NV7050SA 3,000 5,000 Typ. 7.0 ´ 5.0 ´ 1.6 (mm) 170 MHz to 700 MHz +3.3 V ±10 % Max. ±50-10-6 APR (Absolute Pull range) Min. ±100-10-6 , ) () (rms) NV7050SA NV7050SA () (PLL ) 12 kHz to 20 MHz 38.0 fs 210.0 fs 50 kHz to 80 MHz 56.5 fs 220.0 fs APR () APR TEL 03-5453-6751 FAX 03-5453-6756 E-Mail ... Original
datasheet

2 pages,
134.84 Kb

NV7050SA 565 PLL PLL 40 kHZ pll 565 NV7050SA abstract
datasheet frame
Abstract: der (hochfrequenten) Eingangsspannung, bei der die PLL einrastet Uou,nf • • - NF-Ausgangsspannung k , 10,7 ±75 NE 562 B 1 2 + 18 + 26 12 2,0 200 70 0,5 40 10,7 ±75 NE 565 A 2 (3) ±6,0 ±13 8,0 10 Im 150 0,2 40 0,5+ NE 565 K 4 3 ±6,0 ±13 8,0 10 Im 150 0,2 40 0,5+ NE 567 T 5 4 + 5,0 + 10 7,0 20 20 m 200 0,5+ ±70 NE 567 V 3 4 + 5,0 + 10 7,0 20 20 m 200 0,5+ ±70 Pinkompatibel Typ Typ Typ LM565CH LM565CH NE 565 K NE 560 N-16 NE 560 B SE 560 B NE 560 B LM565CN LM565CN NE 565 A NE 561B NE 560 B SE 560 F NE 560 B LM 565 ... OCR Scan
datasheet

1 pages,
56.51 Kb

561b pll lm565 m 13 560 FUNKAMATEUR - Bauelementeinformation vergleichsliste NE565 lm 567 ne 565 pll 567 cn pll 565 PLL 567 Funkamateur datasheet abstract
datasheet frame
Abstract: * 5.65 4.30 3.28 PLL+ All 1 Yes VCO Sigma- No Delta 1168-1395, LMX2531LQ2570ECT-ND LMX2531LQ2570ECT-ND , 2170-1395 LMX2505LQ1321TR-ND LMX2505LQ1321TR-ND§ 3744.80/1,000 PLL+ 6.34 LMX2512LQ0967CT-ND LMX2512LQ0967CT-ND* 5.65 4.30 , Wire- Inte- Integrated Frequency PLL less grated Loop RF IF Range Digi-Key Type Std. VCOS Filter PLL PLL (MHz) Part No. PLL with VCO Wire- Inte- Integrated Frequency PLL less grated Loop RF IF Range Digi-Key Type Std. VCOS Filter PLL PLL (MHz) Part No. PLL ... Original
datasheet

1 pages,
316.31 Kb

vhf ism 730-1017-ND 818 vco LMX2531LQ2265ECT PLL 2400 MHZ 730-1012-ND S331AH-915 s467a S467AH-915S SG101N-915 sma M7 diode VCO PLL 730-1020-ND 765 PLL LMX2525LQ1321CT-ND LMX2525LQ1321CT-ND abstract
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Abstract: Signetics AN 185 Circuit Description of the NE566 NE566 Application Note Linear Products CIRCUIT DESCRIPTION OF THE 566 PLL The 566 is the voltage-controlled oscillator portion of the 565. The basic die is the same as that of the 565; modified metalization is used to bring out only the VCO. The 566 circuit diagram is shown in Figure 1. Transis tor Q ie provides a buffered triangle waveform output. (The triangle waveform is available at capacitor Ci also, but any current drawn from Pin 7 will ... OCR Scan
datasheet

1 pages,
22.38 Kb

ne566 vco CI 565 pll Signetics NE566 NE566 Signetics 565 ci 565 566 vco NE566 application note 566 pin diagram triangle wave vco 566 vco 566 pll 565 application PLL 566 565 PLL pin diagram NE566 abstract
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Abstract: palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A CH8398A pixel bus is 16 bits , driver software can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the , /256 pseudo-color mode to be mixed with 64K color 5-6-5 or 32K color 55-5 bypass. Mixed mode switching , "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop ... Original
datasheet

1 pages,
21.01 Kb

supervga STG1703 pll 565 CH8398A 565 PLL pin diagram CH8398A abstract
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Abstract: S5K4CAG 1/4" 3-Mega Pixel SOC [Features] · JPEG On-the-fly · AF/AE/AWB ­ 3A · MIPI CSI2 ­ compliant (2-lane) · Any Size Image scaling up/down · Output Format - IUT-R 601/656 - RGB 565/666/888 - 10 bits Raw Data · Support Xenon and LED type flash · Max. PLL output freq: 1GHz for MIPI · Internal Regulator: 1.8V to 1.2V(120mA) · Control I/F: I2C(slave/master), 6PWM, GPIO · External Sensor , /Reset Generator Row Driver PLL C-Processing JPEG Scaling BPR/Shading Y-Processing ... Original
datasheet

1 pages,
46.39 Kb

csi2 MIPI CSI2 4 lane pll 565 application rgb CSI2 interface rgb sensor 666 RGB S5K* CMOS s5k4ca MIPI CSI2 interface 1GHz PLL Generator MIPI TO RGB 2048x1536 565 PLL datasheet abstract
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Abstract: EM78567/566/565 Manual ;= PLL = 0X06 RF = 0X0F , ) 5639977 FAX: (03) 5630118 EM78567/566/565 Manual EM78P567/566/565 Manual EM78R567 EM78R567 SPEC. , capacitor 0.01u to 0.047u with GND . External interrupt 1 EM78567/566/565 Manual INT6 INT7 P7.0 , /enable internal pull low. 2 EM78567/566/565 Manual ICE TOP VIEW LEFT SIGHT 1 2 JP1 , /AD2 P93/AD1 P93/AD1 P92/DAOUT P92/DAOUT P91 JP3 connection 1999/Jun/14 3 EM78567/566/565 Manual ICE ... Original
datasheet

17 pages,
75.01 Kb

565 PLL AD P71 CA10 CA12 EM78565 EM78566 EM78567 ICE567 DJZ capacitor pll 565 pll 565 application pll 566 ICE567 abstract
datasheet frame
Abstract: adopt digital PLL. An Anti-alias filter and an 8-order BPF (switched capacitor filter) are incorporated , 3) 57kHz band pass filter (8-order switched capacitor filter) 4) DSB demodulation(digital PLL) 5 , 0.2 1.0 V RCLK RDATA QUAL Io=1.0mA Center frequency FC Gain GA 56.5 57.0 , filter 3 RCLK 16 2.2µF VDD1 5 1 Analog Power supply VSS1 QUAL 1 6 PLL 57kHz 1 , 3 PLL 1187.5Hz Bi-phase decoder 33pF 3 RDATA 2 Measurement circuit 10 XO ... Original
datasheet

2 pages,
49.52 Kb

SSOP-A16 capacitor filter RDS decoder "Decoder IC" pll 565 pll 565 application Biphase decoder for PLL IC 565 PLL IC 565 BU1924/F/FS BU1924/F/FS abstract
datasheet frame
Abstract: BCM3418 BCM3418 PRODUCT Brief ® BCM3418 BCM3418 CMOS B C M 3 4 1 8 VoIP F E AT U R E S CABLE S U M M A R Y · Supports 64 - 256 QAM · Input Noise Figure 12 dB · IP3 = 15 dBm (two tone) · SNR 40 dB · CTB, CSO, Xmod all > 50 dB · PLL Step Size 100 KHz · IF AGC 30 dB Range · 48-Pin , BCM3418 BCM3418 LNA 54-860 MHz CMOS Tuner PA LPF 5-65 MHz SAW BCM3300 BCM3300 QAM Rx QPSK/QAM Tx , 4 1 8 O V E R V I E W IF AGC PLL The BCM3418 BCM3418 is a complete QAM Digital Cable ... Original
datasheet

2 pages,
130.04 Kb

BCM3300 8 qam 256 QAM cable tv tuner pin BCM3310 BCM3418 BCM3418 abstract
datasheet frame
Abstract: operating temperature range 1 Patented, self-acquiring PLL GaAs IC design - Available in standard frequencies: 100,155.52, 250, 565, and 622.08 Mbit/s. Custom frequencies available upon request. • PLL design , (GBLj GigaBit Logic 16G041-H 16G041-H Low Power, PLL Clock & Data Recovery Circuit 100 to 625 Mbit/s NRZ , GigaBit's 16G041 16G041 PLL clock and data recovery GaAs IC together with a high performance loop filter and other components to realize a complete, 3-terminal (data in, clock and data out) PLL clock recovery subsystem. No ... OCR Scan
datasheet

8 pages,
559.66 Kb

16G041-HA ic 565 advantages 16G041-HD CERAMIC LEADLESS CHIP CARRIER FO56 pll 565 0420 LOP lock range of 565 PLL IC 565 PLL pin diagram for PLL IC 565 PLL IC 565 16G041-H 10G041A 16G041-H abstract
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Datasheet Content (non pdf)

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APPLICATIONS The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA Clock Internal oscillator circuit and PLL clock multiplication circuit Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL to 16 MHz base oscillation) . The PLL clock is the oscillation Clock multiplied by one time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = x 4, V CC = 5.0 V
www.datasheetarchive.com/files/fujitsu/fumcsite/products/mb6.htm
Fujitsu 16/08/2001 21.92 Kb HTM mb6.htm
APPLICATIONS The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA Clock Internal oscillator circuit and PLL clock multiplication circuit Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL to 16 MHz base oscillation) . The PLL clock is the oscillation Clock multiplied by one time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = x 4, V CC = 5.0 V
www.datasheetarchive.com/files/fujitsu/fumcsite/products/mb905606.htm
Fujitsu 16/08/2001 21.93 Kb HTM mb905606.htm
More. Table APPLICATIONS The MB90560/565 series is a general-purpose oscillator circuit and PLL clock multiplication circuit Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the PLL clock is the oscillation Clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz , PLL clock setting = x 4, V CC = 5.0 V) Maximum CPU memory space : 16 MB
www.datasheetarchive.com/files/fujitsu/micros dvd 4.0/products/mb15.htm
Fujitsu 17/01/2006 22.61 Kb HTM mb15.htm
compact write strategy coding PLL oscillator features a self-learning oscillator mode for non-locked operation during read Wide frequency range: PLL locking factor min. 2.5 Two output channels, delta 565 MHz Forward Sense (FS) Laser Power Control (LPC) loop to compensate laser drift due to
www.datasheetarchive.com/files/philips/pip/tza1032_1.html
Philips 23/04/2003 6.16 Kb HTML tza1032_1.html
filter and cross detector, a bit rate clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder POR ON POR Threshold 2.5 V FILTER(measured an pin 4 FILOUT) F C Center Frequency 56.5 57 57.5 KHz BW data. According to the internal PLL lock condition this data change can results on the falling or on the Circuit Measure f1 (KHz) f2 (KHz) f3 (KHz) D Ph max A 56.5 57 57.5
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1492-v2.htm
STMicroelectronics 14/06/1999 8.26 Kb HTM 1492-v2.htm
filter and cross detector, a bit rate clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder POR ON POR Threshold 2.5 V FILTER(measured an pin 4 FILOUT) F C Center Frequency 56.5 57 57.5 KHz BW data. According to the internal PLL lock condition this data change can results on the falling or on the Circuit Measure f1 (KHz) f2 (KHz) f3 (KHz) D Ph max A 56.5 57 57.5
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1492.htm
STMicroelectronics 02/04/1999 8.3 Kb HTM 1492.htm
and cross detector, a bit rate clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder Threshold 2.5 V FILTER(measured an pin 4 FILOUT) F C Center Frequency 56.5 57 57.5 KHz BW 3dB clock (RDCL line) is synchronized to the incoming data. According to the internal PLL lock Measure f1 (KHz) f2 (KHz) f3 (KHz) D Ph max A 56.5 57 57.5
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1492-v1.htm
STMicroelectronics 25/05/2000 10.04 Kb HTM 1492-v1.htm
clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder, differential decoding circuit, ARI in - POR ON POR Threshold 2.5 V FILTER(measured an pin 4 FILOUT) F C Center Frequency 56.5 57 57.5 KHz BW the incoming data. According to the internal PLL lock condition this data change can results on the diagram Figure 3: Test Circuit Measure f1 (KHz) f2 (KHz) f3 (KHz) D Ph max A 56.5 57 57.5
www.datasheetarchive.com/files/stmicroelectronics/books/ascii/docs/1492.htm
STMicroelectronics 25/05/2000 10.5 Kb HTM 1492.htm
No abstract text available
www.datasheetarchive.com/download/56892061-30216ZC/rl-arm_gs_examples.zip (LPC2300.lst)
ARM 20/05/2010 22570.37 Kb ZIP rl-arm_gs_examples.zip
100nF 10 m F OSCILLATOR & DIVIDER 57KHz PLL FAST ARI INDICATOR POLARITY BIPHASE DEC. INTEGRAL BIPHASE DEC. 1187.5Hz PLL MUX 0 1 DIFF. DECODER TEST LOGIC QUAL DET. 6 GND 11 EXTRES 14 13 5 9 16 7 1 Center frequency 56.5 57 57.5 kHz BW 3dB Bandwidth 2.5 3 3.5 kHz G Gain f = 57kHz 18 20 22 dB A on RDCL line is synchronized to the incoming data. According to the internal PLL lock condition data
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5278-v2.htm
STMicroelectronics 14/06/1999 8.54 Kb HTM 5278-v2.htm