500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
CD4046BNSR Texas Instruments CMOS Micropower Phase-Locked Loop 16-SO -55 to 125 visit Texas Instruments Buy
CD4046BNSRG4 Texas Instruments CMOS Micropower Phase-Locked Loop 16-SO -55 to 125 visit Texas Instruments
CD4046BNSRE4 Texas Instruments CMOS Micropower Phase-Locked Loop 16-SO -55 to 125 visit Texas Instruments
PTRF1212IRGZR Texas Instruments PLL FREQUENCY SYNTHESIZER visit Texas Instruments
X98014L128-3.3-Z Intersil Corporation 140MHz Triple Video Digitizer with Digital PLL; MQFP128; Temp Range: 0° to 70° visit Intersil Buy
ISL98002CRZ-170 Intersil Corporation Triple Video Digitizer with Digital PLL; QFN72; Temp Range: 0° to 70° visit Intersil Buy

pll 564 schematic

Catalog Datasheet MFG & Type PDF Document Tags

Wideband FM Modulator schematic diagram using NE564

Abstract: SR01028 Demodulator at 12V FSK Demodulation The 564 PLL is particularly attractive for FSK demodulation since it , 10 16 9 3 15 pF 390 VCO OUYPUT DEMODULATED OUTPUT 0.1µF 14 564 13 C1 12 8 , geometries extends the frequency of operation to greater than 50MHz. In addition to the classical PLL , PLL can be written as shown in the following equation: VO = (fIN - fO) KVCO (1) Phase Comparator , in the output signal can be eliminated. As shown in the equivalent schematic, the DC retriever is
Philips Semiconductors
Original

NE564

Abstract: 50MHz VCO schematic 8. FM Demodulator at 12V FSK Demodulation The 564 PLL is particularly attractive for FSK , DEMODULATED OUTPUT 14 0.1µF 564 R2 4 13 5 12 430pF C2 390 1K 7 C2 15 pF , 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a , output of the PLL can be written as shown in the following equation: VO = (fIN - fO) KVCO (1) KVCO = conversion gain of the VCO As shown in the equivalent schematic, the DC retriever is formed
Philips Semiconductors
Original
NE564D NE564N 50MHz VCO schematic Wideband FM Modulator schematic diagram using NE564 limiter circuit operation in basic fm demodulate 80pf philips Trimmer capacitors Wideband FM Modulator schematic diagram pll 564 schematic NE/SE564 SR01025 R9-11 SR01034

EWM 1000

Abstract: 902750 2 0 2 902.350 563 31 0 924.950 578 3 0 3 902.400 564 0 0 925.000 578 4 0 4 902.450 564 1 0 925.050 578 5 0 5 902.500 564 2 0 925.100 578 6 0 6 902.550 564 3 0 925.150 578 7 0 7 902.600 564 4 0 925.200 578 8 0 8 902.650 564 5 0 925.250 578 9 0 9 902.700 564 6 0 925.300 578 10 0 10 902.750
Radiotronix
Original
EWM 1000 902750 902950 pll 564 EWM-900-FDTC-HS 50E3 EWM-900-FDTC 902-928MH

Wideband FM Modulator schematic diagram using NE564

Abstract: Wideband FM Modulator schematic diagram at 12V FSK Demodulation The 564 PLL is particularly attractive for FSK demodulation since it contains , than 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. The output of the PLL can be written as shown in the following equation: (f , free-running frequency of the VCO The process of recovering FSK signals involves the conversion of the PLL , present at the output of the PLL due to the wideband nature of the loop filter. To avoid the use of
-
OCR Scan
SE564N pll fsk MODULATOR PLL TV MODULATOR philips components Phase-locked loop circuits SE564 FSK DEcoder 0005D 0406C 47HFCER

Wideband FM Modulator schematic diagram using NE564

Abstract: Philips FA 564 The 564 PLL is particularly attractive for FSK demodulation since it contains an internal voltage , addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. The output of the PLL can be written as shown in the following equation: Vo = (f|N - , free-running frequency of the VCO The process of recovering FSK signals involves the conversion of the PLL , present at the output of the PLL due to the wideband nature of the loop filter. To avoid the use of
-
OCR Scan
Philips FA 564 NE564 equivalent

Stratix PCI

Abstract: higig specification chip view. Figure 1­1. Stratix IV GX Chip View (Note 1) PLL General Purpose I/O and Memory Interface PLL PLL General Purpose I/O and Memory Interface Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL PLL PLL PCI Express Hard IP Block PLL PCI Express Hard IP Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) General Purpose
Altera
Original
Stratix PCI higig specification TSMC 40nm SRAM EP4SE820 FBGA 1760 higig SIV51001-3

EP4SE

Abstract: FBGA 1760 1­1 shows a high-level Stratix IV GX chip view. Figure 1­1. Stratix IV GX Chip View (Note 1) PLL General Purpose I/O and Memory Interface PLL PLL General Purpose I/O and Memory Interface Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL PLL PLL PCI Express Hard IP Block PLL PCI Express Hard IP Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory
Altera
Original
EP4SE EP4SGX ordering information EP4SGX180 3G-SDI serializer CMOS applications handbook DDR SDRAM HY

IC NE564

Abstract: SPD600 classical PLL applications, the NE 564 can be used as a m odulator w ith a controllable freq uency deviation , x f|N. 2. C alculate value o f the VC O freq uency set capacitor: FSK Demodulation T he 564 PLL , : 1% V CC = 4.5V V Cc = 5.5V V CC = 5V h , ho V 0 u t = 5V, Pins 16, 9 lo U T LIM ITS NE 564 M AX MIN 45 40 TYP 60 70 % o f fo 70 40 M AX M Hz UN ITS SE 564 TYP 65 70 30 80 50 40 20 Lock , specification Phase-locked loop NE/SE564 FUNCTIONAL DESCRIPTION (Figure 1) The NE 564 is a m onolithic
-
OCR Scan
IC NE564 SPD600 E564N

50MHz VCO schematic

Abstract: Wideband FM Modulator schematic diagram using NE564 . Calculate value of the VCO frequency set capacitor: C° ~ FSK Demodulation The 564 PLL is particularly , frequency of operation to greater than 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. The output of the PLL can be written , signal can be eliminated. As shown in the equivalent schematic, the DC retriever is formed by the , free-running frequency of the VCO The process of recovering FSK signals involves the conversion of the PLL
-
OCR Scan
pin configuration 500K variable resistor wideband fsk receiver NE564/SE564 7110A2 007A733

IC NE564

Abstract: Signetics NE564 CIRCUIT DESCRIPTION Of The NE564 The 564 contains the functional blocks shown in Figure 1. In addition to the normal PLL functions of phase comparator, VCO, amplifi er and low-pass filter, the 564 has , variations in the FM input signal improves the AM rejection of the PLL. Addi tional features of the 564 , 564. Figure 1. Schematic Diagram o f NE564 December 1988 4-252 Signetics Linear Products , for the 564 is shown in Figure 1. functional with variable supply voltages be tween 5 and 12V
-
OCR Scan
Signetics NE564 schmitt trigger ecl

EP4S

Abstract: EP4S40G5H40 1­1. Stratix IV GX Chip View (Note 1) PLL General Purpose I/O and Memory Interface PLL PLL General Purpose I/O and Memory Interface Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL PLL PLL PCI Express Hard IP Block PLL PCI Express Hard IP Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL , High-Speed LVDS I/O with DPA and Soft CDR PLL General Purpose I/O and High-Speed LVDS I/O with
Altera
Original
EP4S EP4S40G5H40 EP4SGX70 fbga -1932 TSMC 40nm interlaken higig
Abstract: Stratix IV GX chip view. Figure 1â'"1. Stratix IV GX Chip View (Note 1) PLL General Purpose I/O and Memory Interface PLL PLL General Purpose I/O and Memory Interface Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL PLL PLL PCI Express Hard IP Block PLL PCI Express Hard IP Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks Altera
Original

fbga -1932

Abstract: EP4SGX180 Interface Transceiver Transceiver Transceiver Transceiver Block Block Block Block PLL General Purpose I/O , Interface PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PCI Express Hard IP Block , PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PCI Express Hard IP Block PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL General Purpose I/O and Memory Interface
Altera
Original
fb h35 EP4S100G5

m3870

Abstract: TDA2320 equivalent 1992 1/4 561 TDA2320 SCHEMATIC DIAGRAM (1/2 TDA2320) ABSOLUTE MAXIMUM RATINGS Symbol , Transmitter Using M709 or M710 Figure 3 : MMC II - PLL TV Frequency Synthetizer _ £= 7 SGS-1HOMSON 564 " 7#. BKosgausm siaHies
-
OCR Scan
m3870 TDA2320 equivalent M709A/M710A/MC1S M3870 TDA2320N

EP4SGX180

Abstract: KB920 to 12 PLLs per device supporting PLL reconfiguration, clock switchover, programmable bandwidth , , 0, 8+0 - - - - - HC4GX25 - 289, 0, 16+0 564, 44, 16+0 564, 44, 16+8 - 564, 44, 16+8 - HC4GX35 - - - - 564, 44, 16+8 564, 44, 16+8 , 372, 28, 16+0 - - - - EP4SGX180 372, 28, 8+0 - 564, 44, 16+0 564, 44, 16+8 - - 744, 88, 24+12 EP4SGX230 372, 28, 8+0 - 564, 44, 16+0 564, 44, 16+8
Altera
Original
HIV51001-2 KB920 EP4SGX290 EP4SGX360 ddr3 PCB footprint DDR3 embedded system SCHEMATIC

6020M

Abstract: SE564F Demodulation T he 564 PLL is particularly attractive for FSK dem odu latio n since it contains an internal , NE/SE564 DESCRIPTION T he N E /S E 564 is a ve rsa tile , high gua ra n te e d fre q u e n cy pha , /S E 564 consists o f a VC O , lim iter, phase com parator, and post detection processor. FEATURES , specified. LIM IT S LIM ITS N E 564 MAX MIN 45 40 TYP 60 70 MAX M Hz % of f 0 40 20 SYM BOL PA R A M E T E R T E S T C O N D IT IO N S M IN SE 564 TYP 60 70 30 80 U N ITS M axim um V C O
-
OCR Scan
6020M SE564F

CRCW0603331JRT1

Abstract: LMX2353 and low noise measurement. Remove the 51 resistor at OSCin input port (R51 of the schematic in , alternately over time. It is necessary to put a sufficient delay between PLL programming (i.e. 100,000). Refer , time difference between the point the frequency starts to change and the point that the PLL frequency , O P E R A T I N G I N S T R U C T I O N S RF PLL Phase Noise and Loop Bandwidth MKR REF -2 1 .3 dBm ATTEN 1 dB 15 -56.4 Hz dB dB/ SAMPLE MARKER 15 Hz -56.4 dB
National Semiconductor
Original
LMX2353 CRCW0603331JRT1 CCIJ255G VCO191-1960U 2C18PPMZZ HTSM3203-10G2 C28 Kemet C0603C154J4RAC CRCW0603102JRT1 CRCW0603472JRT1 CRCW0603103JRT1

4433b

Abstract: APP1123 phase-locked loop (PLL). Also external was the 19.2MHz temperature compensated crystal oscillator which provides the PLL reference frequency. Although an external RF VCO module, loop filter, and internal RF PLL , signal at approximately -9dBm. The mode of operation, IF PLL dividers, and IF VGA gain were set via the , settings. For a schematic diagram of the MAX2361 Korean Band test circuit see Figure 4. For Larger , -56.4 -72.3 118 2.36 100 6.86 -55.9 -72.2 106 2.34 100 5.27 -54.6 -72.4 96 2.32 011
Maxim Integrated Products
Original
APP1123 4433b App112 1750MH 1750-1780MH MAX236X 1765MH AN1123

circuit diagram of 4 channel 315 rf transmitter

Abstract: 4433B components comprising an IF phase-locked loop (PLL). Also external was the 19.2MHz temperature compensated crystal oscillator which provides the PLL reference frequency. Although an external RF VCO module, loop filter, and internal RF PLL synthesizer could have been used the requisite VCO module was not available , the appropriate high-side injection signal at approximately -9dBm. The mode of operation, IF PLL , . Page 3 of 9 Figure 3. Interface software settings. For a schematic diagram of the MAX2361 Korean
Maxim Integrated Products
Original
circuit diagram of 4 channel 315 rf transmitter 1780MH

LF1152

Abstract: "Stratix IV" Package layout footprint regional clocks, and 88 peripheral clocks per device Up to 12 PLLs per device supporting PLL , - - - - - HC4GX25 - 289, 0, 16+0 564, 44, 16+0 564, 44, 16+8 - 564, 44, 16+8 - HC4GX35 - - - - 564, 44, 16+8 564, 44, 16+8 744, 88 , , 16+0 - - - - EP4SGX180 372, 28, 8+0 - 564, 44, 16+0 564, 44, 16+8 - - 744, 88, 24+12 EP4SGX230 372, 28, 8+0 - 564, 44, 16+0 564, 44, 16+8 564, 44
Altera
Original
LF1152 EP4SE530H35 EP4SE360 HC4E35 EP4SGX180KF40
Showing first 20 results.