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Part Manufacturer Description Datasheet BUY
5962-8671701EA Texas Instruments 8-Bit Shift Registers With Output Latches 16-CDIP -55 to 125 visit Texas Instruments
5962-8671701FA Texas Instruments 8-Bit Shift Registers With Output Latches 16-CFP -55 to 125 visit Texas Instruments
SN54LS595J Texas Instruments 8-Bit Shift Registers With Output Latches 16-CDIP -55 to 125 visit Texas Instruments
SN74LS599D Texas Instruments 8-Bit Shift Registers With Output Latches 16-SOIC 0 to 70 visit Texas Instruments
SNJ54LS595J Texas Instruments 8-Bit Shift Registers With Output Latches 16-CDIP -55 to 125 visit Texas Instruments
SNJ54LS595W Texas Instruments 8-Bit Shift Registers With Output Latches 16-CFP -55 to 125 visit Texas Instruments

plc shift register with latch outputs

Catalog Datasheet MFG & Type PDF Document Tags

bmw lvds cable

Abstract: TN1037 shift register brings data into the register from the PLC array. The parallel low-speed data from the , Description Input signal from associated pad via PIC. OUTD0 Input to shift register from PLC routing during output mode. OUTD1 Input to shift register from PLC routing during output mode. OUTD2 Input to shift register from PLC routing during output mode. OUTD3 Input to shift register from , 200 Mbits/s. · 420 MHz I/O performance to support UTOPIA 4 standards. · Input/output shift register
Lattice Semiconductor
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R16C17

Abstract: R14C17 from latch/FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC. The , example, the latches/FFs can be used as a 4-bit shift register, and the LUT can be used to detect when a , functions, fO and f3, are also usable simultaneously with the logic gate outputs. The output of the , can be routed out on the o[4:0] PFU outputs or to the latch/FFs d[3:0] inputs. To increase memory , , the latch/FF input can also be tied to logic 0, which is the default. The four latch/FF outputs, q[3
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MAX6922AQH D

Abstract: Nippon capacitors and operated together. The output latch is transparent to the shift register outputs when LOAD is high , data from the shift register to the output latch when LOAD is high (transparent latch), and latches the , , then the data shifted into the shift register at DIN appears at the OUT0 to OUTn-1 outputs. CLK and DIN , clocked out of the internal shift register to DOUT (MAX6932) on CLK's falling edge. For the MAX6933 , Input. Data is loaded into the internal shift register on CLK's rising edge. On CLK's falling edge, data
Maxim Integrated Products
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MAX6922AQH D Nippon capacitors 68 20L MAX6922/MAX6932/MAX6933/MAX6934 MAX6850 MAX6853 MAX6922/MAX6934 MAX6922/MAX6932/MAX6934 MAX6932/MAX6933/MAX6934

T3168

Abstract: ATT ORCA fpga and next state of a latch/ FF, build a 4-bit shift register, etc. Each of the outputs can drive any , or Raast 3. Latch/FF with Front-End Sslset Figure 12. Latch/FF Set/Reset Configurations PLC Routing , out of the PLC. The eight signals are the four LUT outputs (fO, f1,12, f3) and the four latch/FF , a PLC in the second row and third column is BC. PICs are indicated similarly, with PT (top) and PB , independently. For example, the latches/FFs can be used as a 4-bit shift register, and the LUT can be used to
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T3168 ATT ORCA fpga gc 5.5V .22f 207 525s ATT1C05 op3120 QDS002 IEEE1149 C07-1R280 ATT1C07 280-P 132-P
Abstract: paths from latch/FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC , independently. For example, the latches/FFs can be used as a 4-bit shift register, and the LUT can be used to , ORCA Series Field-Programmable Gate Arrays Programmable Logic Cells (PLC) (continued) Each latch , /FF dO and latch/FF d3 inputs, or directly to the outputs oO and o3. The use of the LUT for two , , are also usable simultaneously with the logic gate outputs. ORCA Series Field-Programmable Gate -
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364-P AL-500404200 DS92-099FPGA

ATT ORCA fpga architecture

Abstract: ATT ORCA fpga and next state of a latch/FF, build a 4-bit shift register, etc. Each of the outputs can drive any , the PLC. The eight signals are the four LUT outputs (fO, f1, f2, f3) and the four latch/FF outputs , latches/FFs can be used as a 4-bit shift register, and the LUT can be used to detect when a register has , routed to the latch/FF dO and latch/FF d3 inputs, or directly to the outputs oO and o3. The use of the , five-input combinatorial functions, fO and f3, are also usable simultaneously with the logic gate outputs
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ATT ORCA fpga architecture ATT1C03 ATT1C09 ATATS044 21Q-133BA DS95-084FPGA DS94-131FPGA
Abstract: , read the present state and next state of a latch/FF, build a 4-bit shift register, etc. Each of the , -bit shift register, and the LUT can be used to detect when a register has a particular pattern in it , the latch/FF dO and latch/FF d3 inputs, or directly to the outputs oO and o3. The use of the LUT for , with the logic gate outputs. The output of the multiplexer is: f1 = (HLUTA x cO) + (HLUTB x cO) f1 = , on the o[4:0] PFU outputs or to the latch/FFs d[3:0] inputs. To increase memory address locations -
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C07-1R 100-P 144-P 208-P 225-P 240-P

AMD 2903

Abstract: AMD 2903 bit slice Move status Shift Register X X X X X Logical Logical AND Logical AND with files Logical , power and communicates with other modules through the PLC-3 chassis backplane. Two main processor modules are available for your PLC-3 system: cat. no. 1775-L1 cat. no. 1775-L2 1 Product Data , ) Product Data Description The main processor module is used in PLC-3 programmable controller systems , quickly determines if outputs are: G true G false complete control over program execution program
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AMD 2903 AMD 2903 bit slice plc shift register with latch outputs MCR 100-6 bit-slice Allen Bradley PLC PN955096-55

vfd control using plc

Abstract: Nippon capacitors and operated together. The output latch is transparent to the shift register outputs when LOAD is high , data from the shift register to the output latch when LOAD is high (transparent latch), and latches the , , then the data shifted into the shift register at DIN appears at the OUT0 to OUTn-1 outputs. CLK and DIN , clocked out of the internal shift register to DOUT (MAX6932) on CLK's falling edge. For the MAX6933 , Input. Data is loaded into the internal shift register on CLK's rising edge. On CLK's falling edge, data
Maxim Integrated Products
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vfd control using plc MAX685x MAX6922 MAX6934 MAX6920 MAX6921/MAX6931 21-0049D MAX6922AQH

FX0-14MR-ES

Abstract: mitsubishi plc manual 017-159 1 Specifying a PLC 1.1 What is a PLC? Outputs Control PLC Inputs Actuators , common questions a user asks once he is committed to using a PLC. q The number of inputs and outputs (I , FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For 20 I/O FX0 Micro PLC , relays x, y Max. no. of inputs and outputs 512 256 120 30 M General/Latch 2048 , . Available with 14, 20 or 30 inputs and outputs. Each model is stand alone and powered by most world ac
RS Components
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FX0-14MR-ES mitsubishi plc manual mitsubishi fx plc programming cable pin wiring di FX0-30MR-ES FX0-30MR-DS M8014

mitsubishi fx plc programming cable pin wiring di

Abstract: FX0-14MR-ES 232-4645 1 Specifying a PLC 1.1 What is a PLC? Outputs Control PLC Inputs Actuators , common questions a user asks once he is committed to using a PLC. q The number of inputs and outputs (I , FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For 20 I/O FX0 Micro PLC , relays x, y Max. no. of inputs and outputs 512 256 120 30 M General/Latch 2048 , . Available with 14, 20 or 30 inputs and outputs. Each model is stand alone and powered by most world ac
RS Components
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mitsubishi pin out plc to pc interface FX0-20MR-ES mitsubishi plc FX SERIES plc mitsubishi q series mitsubishi plc FX SERIES connection cable FX-10du-E

M8014

Abstract: d8042 problems occur when installed. Information- Inputs- Outputs- 1.2 Why use a PLC? Flexibility q , is committed to using a PLC. q The number of inputs and outputs (I/O) required? q Are the I/O digital , FX0 MEDOC software only FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For , . of outputs Max. no. of inputs and outputs General/Latch Link Special Non-battery backed Battery , 24Vdc supply to power source inputs. The relay or transistor outputs are standard FX PLC specification
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D8067 d8042 D8041 M8012 FX0-20MT-D FX0-20MT FX0-14MT-D M8050 M8051 M8052 M8053 M8056 M8057

1C05

Abstract: ATT ORCA fpga architecture present state and next state of a latch/FF, build a 4-bit shift register, etc. Each of the outputs can , direct paths from latch/FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC , :0]. The results are routed to the latch/FF dO and latch/FF d3 inputs, or directly to the outputs oO , usable simultaneously with the logic gate outputs. The output of the multiplexer is: f 1 = (HLUTA x CO , routed out on the o[4:0] PFU outputs or to the latch/FFs d[3:0] inputs. To increase memory address
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1C05 PX110 1C09 2843B C05 jj MXM pin assignment 304-P

1C07

Abstract: plj1 latch/FF, build a 4-bit shift register, etc. Each of the outputs can drive any number of the five PFU , /FFs, there are direct paths from latch/FF outputs to the I/O pads. This is done for each PLC that is , :0]. The results are routed to the latch/FF dO and latch/FF d3 inputs, or directly to the outputs oO , with the logic gate outputs. The output of the multiplexer is: f 1 = (HLUTA x CO) + (HLUTB x cO) f1 = , ., f[3:0], or the direct data input, wd[3:0]. The four latch/FF outputs q[3:0] can be arbitrarily
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1C07 plj1 HC s304 ic all pics IC PIN CONFIGURATION OF 74 47 att1765

TPA6116

Abstract: headphone op amp must be configured so that the same signal is present at both LOUT2 and ROUT2 outputs but with the , operating with a range of supply voltages, particularly relevant here are the SPKVDD, AVDD and HPVDD supply , plc www.wolfsonmicro.com January 2004, Rev 1.2 Copyright 2004 Wolfson Microelectronics plc WAN_0141 WM8750/51L SETUP LOUT2/ROUT2 REGISTER SETTINGS The LOUT2 and ROUT2 output pins are , ­(-R) = L+R]. REGISTER ADDRESS R40 (28h) LOUT2 Volume BIT LABEL DEFAULT DESCRIPTION
Wolfson Microelectronics
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TPA6116 headphone op amp speaker LM4895 WM8750L speaker 8Ohm WM9711/12L

TPA6116

Abstract: wm9712 500mW but 0.1% at 180mW output. WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com September 2003, Rev 1.1 Copyright 2003 Wolfson Microelectronics plc WAN_0141 WM8750 SETUP LOUT2/ROUT2 REGISTER , LOUT2 and ROUT2 outputs but with the ROUT2 output inverted as set by the INV bit in Table 2. Maximum , voltages. The WM8750L and WM9712L are capable of operating with a range of supply voltages, particularly , right channel are mixed to mono in the speaker [L­(-R) = L+R]. REGISTER ADDRESS R40 (28h) LOUT2
Wolfson Microelectronics
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wm9712 MAX4167 WM9712

mitsubishi fx plc programming cable pin wiring di

Abstract: FX0-14MR-ES devices 5.6 Applied functions D17799 1 Specifying a PLC l PLCs are increasingly being used with their standard hardware and software instead of dedicated 1.1 What is a PLC? computers with unique programs , PLC s o s s r l l Most PLCs are manufactured by well known i t r o y o a o Inputs Outputs t a r , quickly and cost effectively. with a product correctly specified for the application, l A PLC can be , number of inputs and outputs (I/O) required? l Are the I/O digital or analogue? Appropriate PLC l Are
RS Components
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mitsubishi FX series instruction list mitsubishi f2 plc manual PLC connect encoder mitsubishi FX on 60 mr-es melsec fx0 30mt manual mitsubishi plc cable f1 series M8047 D8047 M8058 M8059 M8061 D8061

probug

Abstract: MC68701 bit is controlled by the state of PLC. Associated with the EPROM are an 8-bit data latch and a 16 , address latch is controlled by the PLC bit. A description of the RAM/EPROM Control Register follows , Register for Port 4 has been written with "1's" in the appropriate bits. These address lines will assert "1's" until made outputs by writing the Data Direction Register. MC68701 FIGURE 16 - MC68701 MEMORY , written with "1 's" in the appropriate bits. These address lines will assert "1's" until made outputs by
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M6800 MC6800 probug MC68701L MC6801 MC68701-l1 IRF 3008 multiplexed ram MC6801/03 A13281-3 C198S4

probug

Abstract: mc68701 probug will not contain addresses until the Data Direction Register for Port 4 has been written with "Vs" in , the Data Direction Register for Port 4 has been written with "1 s" in the appropriate bits These address lines will assert "1 s" until made outputs by writing the Data Direction Register. 1) MCU read of , associated with IS3 are controlled by the Port 3 Control and Status Register and are discussed in the Port 3 , by an F53 negative edge. The latch is transparent after a read of Port 3 Data Register. LATCH ENABLE
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MC68701S MC68701S-1 MC68B701S mc68701 probug application circuits for MC68701 pdd 3010 AN/mc68701 probug MC6801/MC6803 MC68701CS MC68701CL MC68701L-1

AT01084

Abstract: Description Lookup table including truth table register and decoder Delay element, created with a programmable , LUT0: PORTC or PORTD (see PORTSEL in CTRLA register). Important remark: The port selected with PORTSEL , CTRLA register). Important remark: This port is common for inputs and outputs and for LUT0 and LUT1. Pin , . Register configuration: To use LUT0 and LUT1 as separated LUT with two inputs and one output, the user has , to output with ACEVOUT register. 3.5.3 Event system as LUT input Event system is proposed as
Atmel
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AT01084
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