500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
J2014001L422N GE Critical Power GP100, 3&934;-480, RS485 communications, controller slot, RJ45 terminations, includes a L401 and a L402 shelves in the same enclosure. Hardware included visit GE Critical Power
J2014001L401 GE Critical Power GP100, 3&934;-480, RS485 communications, add-on stand-alone shelf, configured for slot 3, hardware and shelf interconnect included visit GE Critical Power
J2014001L601 GE Critical Power Compact Power Line Shelves, GP100, 3Φ-480, dual, redundant, I2C shelf configured for 48Vdc output, configured for slot 1, hardware and shelf interconnect included visit GE Critical Power
J2014001L601A GE Critical Power Compact Power Line Shelves, GP100, 3Φ-480, dual, redundant, I2C shelf configured for 54Vdc output, configured for slot 1, hardware and shelf interconnect included visit GE Critical Power
CP841A_3C3R_S (150032047) GE Critical Power Galaxy Pulsar Edge Controller for Compact Power Line Applications with Security Features Update visit GE Critical Power
J2014001L402 GE Critical Power GP100, 3&934;-480, RS485 communications, controller slot, LAN, RJ45 terminations, configured for slot 3 visit GE Critical Power

placement of std cells in the core for asic

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: , three of which are used for personalization, the fourth layer being used solely for power and ground bussing. The key features of the array core are: * 14784 Internal cells arranged 168 in the X-direction , , high density needs of the Computer marketplace. In comparison with Motorola's MCA-3 family, the MCA , cells â'¢ 4-layer metal to permit high degree of routing capability, in excess of 80% â'¢ 400 Signal , of the TAB are: â'¢ Die on tape is supplied in a carrier â'¢ Tape has two metal layers (signal -
OCR Scan

m6845

Abstract: NA51 transistor protected power pad for use with core signals. No series res. In the interest of maintaining backward , rich set of core and configurable pad cells which allow great flexibility in building competitive , families. The ASIC Standard Library is listed in detail on pages 12 to 20. AMI's selection of soft , produce soft megacell schematics in the ASIC Standard Library, and a schematic symbol for incorporation , cells. This method allows the ASIC designer to define pad cells by choosing from a vast array of pad
American Microsystems
Original

verilog code voltage regulator

Abstract: verilog code for 32 bit risc processor modeling Sprinkled gate array cells for fast metal-level design changes late in the design cycle 4 , to the die. The TImePilot floorplanning flow lets you add, delete and swap core cells. A summary of the GS30TR macro library gate array cells available for ECO are shown in Table 2. Table 2 , identifier for each die fabricated. You can access the 64-bit identifier in software directly from the ASIC , of the clock tree is optimized for size, delay, and power in accordance with the requirements of
Texas Instruments
Original
verilog code voltage regulator verilog code for 32 bit risc processor fastscan vhdl code for watchdog timer of ATM verilog code for 16 bit risc processor vhdl code 32 bit risc code

verilog code for 32 bit risc processor

Abstract: vhdl code for usart accurate modeling u Sprinkled gate array cells for fast metal-level design changes late in the design , TImePilot floorplanning flow lets you add, delete and swap core cells. A summary of the GS30TR macro , identifier for each die fabricated. You can access the 64-bit identifier in software directly from the ASIC , of its semiconductor products to the specifications applicable at the time of sale in accordance , . INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order
Texas Instruments
Original
vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI LogicVision

DIGITAL IC TESTER report for project

Abstract: atmel 504 ± 0.15V. Table 1 shows the range of recommended operating conditions for which Atmel library cells , , load.) · number of simultaneous switching scan FF to determine supply buffers for the core · , methods. The design kit contains relevant descriptions of standard cells and peripheral cells, given for , Features · Comprehensive Library of Standard Logic and I/O Cells · ATC18RHA Core and IO18 pads , . Hard 0.18 µm CMOS Cell-based ASIC for Space Use ATC18RHA Description The ATC18RHA is fabricated on
Atmel
Original
4261C DIGITAL IC TESTER report for project atmel 504 IO33 ATC18RHA IO33 virage

DIGITAL IC TESTER report for project

Abstract: MCGA349 specific cells must be inserted in the Pad Ring. Two kinds of cells are used: · Back to Back Diodes , specific VCCPLL,VSSPLL 1.8V supply pair. Core Core Array All the cells of the ATC18RHA library are a , of making some placement and routing trials with different tools in order to determine the final , creating a first net-list (interconnection of Atmel ASIC cells) describing the behaviour and the structure , , THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO
Atmel
Original
5962-06B02 MCGA349 PL33RXZ MQFP-T352 ATMEL 644 LVPECL 4261E

verilog prbs generator

Abstract: prbs pattern generator using vhdl in the Atmel ASIC Design Guidelines. For each case of non-compliance, the case must be discussed , . The use of Schmitt trigger inputs in noisy environments is strongly recommended. ASIC Design for , Experience has shown that the safest methodology for time-domain control of an ASIC is synchronous design , Std. Cell Area 3 8 ASIC ASIC Clock Guidance The use of clock guidance is recommended if , Area 3 Std Cell Area 4 It is important to have an even number of rows (in the standard cell areas
Atmel
Original
verilog prbs generator prbs pattern generator using vhdl AOI gate d flip flop

DIGITAL IC TESTER report for project

Abstract: IO33 specific cells must be inserted in the Pad Ring. Two kinds of cells are used: · Back to Back Diodes , specific VCCPLL,VSSPLL 1.8V supply pair. Core Core Array All the cells of the ATC18RHA library are a , of making some placement and routing trials with different tools in order to determine the final , creating a first net-list (interconnection of Atmel ASIC cells) describing the behaviour and the structure , ASIC for Space Use ATC18RHA The ATC18RHA is fabricated on a proprietary 0.18 µm, five-metal-layers
Atmel
Original
4261F MQFP-F196 Genesys Logic 4261b atmel 216

FIR FILTER implementation xilinx

Abstract: fir filter design using vhdl doesn't have to tune the core · Months of development time saved Thoroughly tested for 100% PCI , capacity = number of logic cells Usable capacity = logic cells x utilization ASIC "gate" estimate = 8-12 , architectures The SLI solution will be significantly enhanced to include a number of new cores for , speeds/densities in identical pinouts and packages Fall Seminar - CPLD - 3 The First 5V Flash , different from pinout pre-assigning ­ strong function of utilization in typical CPLD architectures ­
Xilinx
Original
XC9500 XC5200 FIR FILTER implementation xilinx fir filter design using vhdl fpga frame buffer vhdl examples USB Prog ISP 172 XC9572 LIC AGENTS DATA 125KG XC4000E/EX

xilinx xc95108 jtag cable Schematic

Abstract: XC95144 the core · Months of development time saved Thoroughly tested for 100% PCI Compliance · , speeds/densities in identical pinouts and packages Fall Seminar - CPLD - 3 The First 5V Flash CPLD , - CPLD - 7 Pin-Locking is Key for ISP Must retain pinouts as the design evolves ­ best done , function of utilization in typical CPLD architectures ­ result of both architecture and software strategy , maintains pinouts ­ Endurance of 10,000 cycles ­ Extended JTAG test Lower cost XC9500F for production
Xilinx
Original
xilinx xc95108 jtag cable Schematic XC95144 xilinx FPGA IIR Filter XC95144 PQ100 Altera CPLD PCMCIA XC4000series

Atmel 544

Abstract: atmel 504 Logic and I/O Cells Up to 6.5 usable Mgates equivalent NAND2 Operating voltage 1.8V for core and 3.3V or 2.5V for I/O's Memory Cells Compiled or synthesized to the Requirements of the Design EDAC , Cell-based ASIC for Space Use ATC18RHA The ATC18RHA family is supported by a combination of state-of-art , end tools suppliers. The ATC18RHA asic family is available in several quality assurance grades, such , The ASIC "ATC18RHA Design Manual" presents all the required information and flows for 0.18µm designs
Atmel
Original
Atmel 544 atmel 404 MQFPT352 MLGA625 725m atmel h 404 4261G

ARM dual port SRAM compiler

Abstract: designware i2c cells for ECO as shown in Table 2. Table 2: Gate-Array Cells for ECO Function Number of macros , configuration of the clock tree is optimized for size, delay, and power in accordance with the requirements of , of its semiconductor products to the specifications applicable at the time of sale in accordance , . INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order , the cost-efficiency of standard cells with the fast time-to-market of gate arrays. TI provides a full
Texas Instruments
Original
ARM dual port SRAM compiler designware i2c NEC-V850 ARM10 ARM946 TMS320C54X SRST143

DR102

Abstract: QFP208-P-2828-K4 unit, and Boundary Scan Cells. The controller unit is placed in the ASIC core, and the Boundary Scan Cells are placed between I/O pads and the core logic, as shown in Figure 1. Boundary Scan Path , Scan Cells for Output Enable Signal In the scan chain, the chip input TDI connects to the TDI input of , and the core logic, through the Boundary Scan Cells, in normal mode. However in test mode, only test , controllability of the input and output signals. The next section defines the cells in OKI's Boundary Scan
-
Original
DR102 QFP208-P-2828-K4 ot2a OKI Package code STD-1149 1-800-OKI-6388

NA21 transistor

Abstract: kt 825 equivalent level shift is available in the I/O cells. The core can be either 3V for low power or 5V for high , of building blocks for the AMI8S standard cell family. A broad range of primary cells is , contains a rich set of core and pad cells which allow great flexibility in building competitive devices , the standard products of similar names, but are captured in the AMI ASIC Standard Library and are , shows the values of the delay parameter for three different loads. For output pad cells, 25pf, 50pf
AMI Semiconductor
Original
NA21 transistor kt 825 equivalent ami equivalent gates na52 transistor NA51 transistor MGMC51

TTL 740 NAND propagation delay

Abstract: NA51 equivalent transistor within five working days. The AMI ASIC Standard Library contains a rich set of core and pad cells , to 5V and 5V to 3V level shift is available in all I/O cells. Core can be either 3V for low power , schematics in the ASIC Standard Library, and a schematic symbol for incorporation and simulation with the , shows the values of the delay parameter for three different loads. For output pad cells, 25pf, 50pf, and 75pf loads are used. For core cells and input pad cells, fanouts of two, four, and eight gates
AMI Semiconductor
Original
TTL 740 NAND propagation delay NA51 equivalent transistor AMI8G65 G392 OB83 IB09X1

CTC 880

Abstract: vhdl coding for analog to digital converter and UART. The list of analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC and PLL with various , CELLS Introduction to Analog Cores Samsung ASIC is one of the leading suppliers of cell based mixed , design system. Workstation symbols are supplied for analog cells and are entered as part of the design , percent-of-full-scale change in analog output value (of fractions of 1LSB) for a 1% dc change in the power supply , netlist for all memories used in a design. However, when several memories of the same or the different
Samsung Electronics
Original
STD111 CTC 880 vhdl coding for analog to digital converter 16C450 16C550 ARM920T ARM940T

pure sine wave using TL 494

Abstract: sine wave inverter using pic transmission and communication core such as USB, IEEE1284 and UART. The list of analog core cells includes , features of new Samsung ASIC CTS flow are as follows: - 12 user selectable clock tree cells(CTC) for , CELLS Introduction to Analog Cores Samsung ASIC is one of the leading suppliers of cell based mixed , design system. Workstation symbols are supplied for analog cells and are entered as part of the design , percent-of-full-scale change in analog output value (of fractions of 1LSB) for a 1% dc change in the power supply
Samsung Electronics
Original
pure sine wave using TL 494 sine wave inverter using pic PURE SINE WAVE inverter schematic diagram inverter PURE SINE WAVE schematic diagram microcontroller 1 phase pure sine wave inverter sine wave inverter schematic IVT STDM110

pure sine wave using TL 494

Abstract: 152935 USB, IEEE1284 and UART. The list of analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC and , features of new SEC ASIC CTS flow are as follows: - 12 user selectable clock tree cells(CTC) for STD110 - , are supplied for analog cells and are entered as part of the design by the customer or design center. SEC ASIC uses basically the same automatic layout and verification tools for analog cells as for , of 1LSB) for a 1% dc change in the power supply. Power supply sensitivity may also expressed in
Samsung Electronics
Original
152935 verilog code for digital modulation LPG CRT Power Supply 75639 74950 design pure "sine wave" power inverter

design an 8 Bit ALU using VHDL software tools -FP

Abstract: AOI221 complex electronic systems on a single IC in a highly cost-effective manner. All aspects of the ASIC , This is the range for which Atmel's CBIC library cells have been characterised. Operation of a device , Cells Precisely tailored to the requirements of the system. In particular, customised versions of , a uniform environment for all aspects of ASIC design. This includes the logic synthesisfloorplanning-timing analysis cycle necessary for the convergence of deep sub-micron designs. Placement and routing
Atmel
Original
design an 8 Bit ALU using VHDL software tools -FP AOI221 atmel 0928 OAI221 MX 0541 ECPD07 8051TM

FD2S

Abstract: half adder 74xx ASIC offers USB interfaced buffers in the 0.5µm technology. USB is applicable only in STD cells , libraries. In addition, the other interface (CMOS, TTL and Schmitt trigger) cells are fully equipped for , be distributed evenly in the core and on all sides of the chip. · The total number of output , , in the range of tens of nano amperes, which is negligible. SEC ASIC 1-7 STD80/STDM80 , of this model for 2-input NAND cell. The data in this table are high-to-low transition delay times
Samsung Electronics
Original
FD2S half adder 74xx IVCD11 STD80 transistor 131 74xx ttl
Showing first 20 results.