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Part Manufacturer Description Datasheet BUY
CDB48500-USB Cirrus Logic CDB48500-USB Evaluation Kit visit Digikey
CDB5463U-Z Cirrus Logic Pb-freeEval Board for CS5463 with USB; RoHS Compliant: No; visit Digikey
CS4385-CQZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PQFP48, LEAD FREE, MS-022, LQFP-48 visit Digikey
CS4340A-KSZ Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16 visit Digikey
CS4354-CSZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PDSO14, 0.150 INCH, LEAD FREE, MS-012, SOIC-14 visit Digikey
CS4385-DQZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PQFP48, LEAD FREE, MS-022, LQFP-48 visit Digikey

pin+diagram+of+serial+lcd+display+16x2

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: . W x H (mm) (°C) - - - - - - - - - - - - 16x1 16x1 16x1 16x2 16x2 16x2 16x2 16x2 16x2 16x2 16x2 16x2 PRD250LPW1-ND N/A N/A PRD250LPW-ND PRD250LPW-ND , 0 to +50 0 to +50 0 to +50 - - - - - - - - 8x2 16x2 16x2 16x2 16x2 16x4 , 12.7 61 x 16 99 x 24 64.5 x 13.8 61.8 x 25.2 76 x 25.2 147 x 29.5 - - - - - 16x2 , - - - - - - - 16x1 16x1 16x1 16x2 16x2 16x2 16x2 16x2 20x2 20x4 20x4 40x2 DigiKey Electronics Catalog
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DMC-20481NY-LY-B optrex dmc16230 DMC20215A 20X4 LCD ic Q002 73-1025-ND 73-1011-ND 73-1018-ND 73-1014-ND 73-1048-ND 73-1034-ND 73-1035-ND
Abstract: Min Max Min Max Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 11.0 11.0 9.0 9.0 9.0 9.0 ns ns Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 5.5 5.5 4.5 4.5 4.5 4.5 ns ns Address setup time before clock K 16x2 32x1 TASS TASTS 2.7 2.6 2.3 2.2 2.2 2.2 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 0 0 0 0 ns ns DIN setup time before clock K 16x2 32x1 Xilinx
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XC4000E XC4000X XC4000EX XC4028EX XC4036EX 16x1 mux 16x2
Abstract: clock K Data valid after clock K Speed Grade Size Symbol 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWCS TWCTS TWPS TWPTS , 14.2 Preliminary Note 1. Note 2. Timing for the 16x1 RAM option is identical to 16x2 RAM timing , Symbol -5 Min 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT , 6.9 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK Xilinx
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XC4000 x3201 XC4013L X1790 XC4005L XC4010L XC4000L
Abstract: (wwp.x euc.)(An.x wwp.x Bbic.) (fln.x wwp.) Ka paTypa flMHMM [mm] [mm] [mm] [°c] dem16218sgh 16x2 2,45x5,55 55,0x24,5x2,2 50,0x16,0 - -20/+70 dem16221syh 16x2 1,95x3,80 47,0x18,5x5,2 43,0x12,0 - -20/+70 dem16223sy-py 16x2 1,85x3,15 53,0x20,0x8,0 36,0x10,0 LED 0/+50 dem16224syh 16x2 2,95x5,55 66 -
OCR Scan
dem16221 display 16x2 COB CHIP ON BOARD 295x5 CMMB 95x3
Abstract: Max Min Max Min Max Min Max Address write cycle time (clock K period) 16x2 32x1 , ) 16x2 32x1 TWPS TWPTS 5.5 5.5 4.5 4.5 4.5 4.5 ns ns Address setup time before clock K 16x2 32x1 TASS TASTS 2.7 2.6 2.3 2.2 2.2 2.2 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 0 0 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 2.4 2.9 2.0 2.5 2.0 2.5 ns ns DIN hold time Xilinx
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XC4013E xc4005e XC4003E TWCD
Abstract: period) 16x2 32x1 TWCS TWCTS 14.4 14.4 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.2 7.2 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.4 2.4 2.8 2.8 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 3.2 1.9 3.5 2.5 ns ns DIN hold time after clock K 16x2 32x1 TDHS TDHTS 0 0 0 0 Xilinx
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XQ4000E XQ4010E XQ4005E XQ4013E XQ4028EX C1226 XQ4013E datasheet XQ4000E/EX MIL-PRF-38535 PG191 CB196
Abstract: ) Speed Grade Size Symbol Min 3 Max Min 4 Units Max 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 Tw cs t w c ts 14.4 14.4 7.2 7.2 2.4 2.4 0 0 , identical to 16x2 RAM timing. Note 2: Applicable Read timing specifications are identical to Level-Sensitive , Operation Address write cycle time 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 Twc t w ct , after end of WE Read Operation Address read cycle time 16x2 32x1 16x2 32x1 T rc T rct T ilo T iho -
OCR Scan
XQ4000 XQ4025E
Abstract: Max Min Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.8 2.8 2.4 2.4 Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 DIN setup time before clock K 16x2 32x1 TDSS TDSTS DIN hold time after clock K 16x2 32x1 WE setup time before clock K Max Min Max Min Max Xilinx
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Net-list XC4010E XC4008E XC4006E XC4000X Series XC4020E
Abstract: : Note 2: Speed Grade Size Symbol 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS , 7.9 9.3 Preliminary Advance Timing for the 16x1 RAM option is identical to 16x2 RAM timing , Max Min 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP , 2.0 2.0 0.8 0.8 2.0 2.0 16x2 32x1 Data valid after address 16x2 change (no Write Enable Xilinx
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toko rcl 16X1 ram
Abstract: LCM2004AWSR LCM4002ASL LCM4004BSL 8x2 8x2 16x1 16x1 16x2 16x2 16x2 16x2 16x4 20x2 24x2 20x4 -
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LCM2004AWSL LCM1601ASL hitachi 16x2 lcd LCM1602ASL Display LCD 20x4 LCM2002A lcm-1602 lcm1602a HD44780 1602JSR LCM1604BSL LCM2002ASL LCM2402ASL
Abstract: www.p-tec.net sales@p-tec.net Tel: Fax: (719) 589 3122 (719) 589 3592 PC1602A-L (16x2 , sales@p-tec.net Tel: Fax: (719) 589 3122 (719) 589 3592 PC1602A-L (16x2) Character LCD Display , (16x2) Character LCD Display Absolute Maximum Ratings at TA = 25 °C Features *16 Character, 2 Line , sales@p-tec.net Tel: Fax: (719) 589 3122 (719) 589 3592 PC1602B-L (16x2) Character LCD Display , PC1602C-L (16x2) Character LCD Display Absolute Maximum Ratings at TA = 25 °C Features *16 Character, 2 P-tec
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16 pin diagram of lcd display 16x2 PC1602F PC1602H PC1602D 16x2 LCD Panel Display PC1602F-L PC1602P-O KS0066 KS0065
Abstract: (active edge) Write Operation Description Address write cycle time (clock K period) Size 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 Min 14.4 14.4 7.2 7.2 2.4 , 1 2 3 4 5 6 Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 2 , WE DIN hold time after end of WE Size 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 , time Data valid after address change (no Write Enable) 16x2 32x1 16x2 32x1 Read Operation Xilinx
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5962-98509 DS021 XC4025E 4010E
Abstract: Operation Description Size Min Max Min Max Units 16x2 14.4 - 15.0 - ns 32x1 14.4 - 15.0 - ns 16x2 7.2 1 ms 7.5 1 ms ns 32x1 7.2 1 ms 7.5 1 ms ns Address setup time before clock K 16x2 2.4 - 2.8 - ns 32x1 2.4 - 2.8 - ns Address hold time after clock K 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 3.2 - 3.5 - ns 32x1 1.9 - 2.5 - Xilinx
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SMD 5962-98509 xc4000 series fpgas smd p127 smd diode p190
Abstract: Max Units 16x2 14.4 - 15.0 - ns 32x1 14.4 - 15.0 - ns 16x2 , before clock K 16x2 2.4 - 2.8 - ns 32x1 2.4 - 2.8 - ns Address hold time after clock K 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 3.2 - 3.5 - ns 32x1 1.9 - 2.5 - ns 16x2 0 - 0 - ns 32x1 0 - 0 - ns WE setup time before clock K 16x2 2.0 - 2.2 - ns Xilinx
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XCN07010 XCN09001 XCN12004
Abstract: 8x1,16x2 12MHz 333 2.0~5.5 -25~85 Internal 8MHz RC Oscillator S3F8xxx (KS88) Series , /16TCx2 UARTx2, SIO 52/8 10x8 8x1,16x2 12MHz 333 2.0 ~ 3.6 -25 ~ 85 LVR, BLD , 10x8 8x1,16x2 12MHz 333 2.0 ~ 3.6 -25 ~ 85 LVR, BLD, Voltage Booster&Regulator , 8x3 16x2 12MHz 333 2.0~5.5 -40~85 LVR, IVC, PGM S3F84UAXZZ-QZ8A S3F84UAXZZ-AQ9A , 10x8 8x3 16x2 12MHz 333 2.0~5.5 -40~85 LVR, IVC, PGM 32 16 LVR PAGE 6 Samsung Electronics
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S3F833BXZZ-QX8B S3F84NBXZZ-QT8B s3f84k4xzz-dk94 S3F828BXZZ-QW8B S3F84B8XZZ-DK98 S3F833BXZZ F80K5 F80P5 F94C8 F84P4 F9444 F80M4
Abstract: p Liquid Crystal Displays I Character Display LCD Modules Character Display LCD Modules Type D isplay contents (ch ara cte rs x line) 16 x 1 16 x 1 16x2 16x2 16x2 16x4 20x2 20x2 20x2 24x2 O utside dim ensions - w idth x height x depth (m m ) 80 x 36 80 x 36 80 x 36 84x44 87x60 116 x 37 116x37 116x37 116x37 x 12Max. x 12Max. x11M ax. x 12Max. x 12Max. x 13Max. x 11Max. x 9Max. x 11Max. Effective , with LED Back Light D isplay co nte nts (ch ara cte rs x line) 16x2 16x2 20x2 24 x 2 O utside d im -
OCR Scan
RCM2009R RCM2008R RCM2019R RCM2007R RCM2027R RCM2018M RCM2027 LCD display 20X2 rcm200 RCM2003R RCM2013R RCM2025R
Abstract: Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 11.0 11.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 5.5 5.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.6 2.6 Address hold time after clock K 16x2 32x1 TAHS TAHTS DIN setup time before clock K 16x2 32x1 DIN hold time after clock K Max Min Max Min , 16x2 32x1 TDHS TDHTS 0 0 0 0 0 0 ns ns WE setup time before clock K 16x2 Xilinx
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9668e 5410E-02 9722E XC4000XL
Abstract: Address write cycle time (clock K period) 16x2 TWCS 32x1 TWCTS 9.0 9.0 Clock K pulse width (active edge) 16x2 TWPS 32x1 TWPTS 4.5 4.5 Address setup time before clock K 16x2 TASS 32x1 TASTS 2.2 2.2 Address hold time after clock K 16x2 TAHS 32x1 TAHTS 0 0 DIN setup time before clock K 16x2 TDSS 32x1 TDSTS 2.0 2.5 DIN hold time after clock K 16x2 TDHS 32x1 TDHTS 0 0 WE setup time before clock K 16x2 TWSS 32x1 TWSTS 2.0 1.8 WE hold time after Xilinx
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XC4036XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4044XL
Abstract: write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.8 2.8 2.4 2.4 Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 DIN setup time before clock K 16x2 32x1 TDSS TDSTS DIN hold time after clock K 16x2 32x1 WE setup time before clock K Max Min Max Min Max Write Operation 14.4 Xilinx
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xilinx xc4006e XILINX XC4008E
Abstract: period) 16x2 32x1 TWCS TWCTS 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.8 2.8 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 3.5 2.5 ns ns DIN hold time after clock K 16x2 32x1 TDHS TDHTS 0 0 ns ns WE setup time before clock K 16x2 32x1 TWSS Xilinx
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p79 smd p124 v8 smd p126 smd smd diode p126 transistor SMD p96 transistor P32 smd
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