NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: period of BF (pin 9) otherwise, stays at H level._ TVM2 IC TV mode 2 Set to level. TVMi IC TV mode 1 An , The frequency of the signal is 1/4 the 4FSC frequency (pin 43). The signal is reset by color frame pulses CFMI (pin 2)._ SC, Subcarrier output 2 An output pin for color subcarrier. When the phase of SC,(pin 4) is 180 degree, the phase of SC3 is 90 degree in NTSC mode ; in PAL mode, the phase of SC2 is 90 , drive output An output pin for wide Hor. "drive pulse. The pulse width is equal to that of PBLK (pin 39 ... | OCR Scan |
9 pages, |
ic 311 comparator 3 phase signal generator ic pin diagram of bf 494 SHARP COLOR TELEVISION IC 566 function generator LZ92E60 T-41-55 LZ2111J LZ2112J LZ212U LZ2122J LZ92E60 abstract |
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| Abstract: mode: L level during the blanking period of BF (pin 9) otherwise, stays at H level. 11 tvm2 IC , 4 sc! 0 Subcarrier output 1 An output pin for color subcarrier. The frequency of the signal is 1/4 , Subcarrier output 2 An output pin for color subcarrier. When the phase of SC,(pin 4) is 180 degree, the phase of SC2 is 90 degree in NTSC mode ; in PAL mode, the phase of SC2 is 90 degree when LSW (pin 14) is , drive output An output pin for wide Hor. "drive pulse. The pulse width is equal to that of PBLK (pin 39 ... | OCR Scan |
9 pages, |
RS-170 LZ2112J LZ2122J LZ2111J LZ92E60 LZ92E62 LZ93N25 LZ2124J LZ2121J LZ2121 T-41-55 LZ212U T-41-55 abstract |
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| Abstract: 16), PBLK (pin 39), BF (pin 9) end WBLK (pin 42) change, and the phase of ENCP (pin 15) and HBLK , Single +5 V power supply . Package : 48-pin QFP(QFP048-P-0707 QFP048-P-0707) ~~~ I in tie abwnce of confImtIOn by , using any WARPS devhce" s~ U95D52/M U95D52/M BLOCK DIAGRAM SEL2 SELI BF VRI WHD GND , An output pin for color subcarrier in NTSC mode. The frequency of the signal is 1/4 the CLKI (pin 27 , color subcarrier in NTSC mode. When the phase of SC I (pin 4) is 180 degree, the 5 SC2 o N ... | Original |
25 pages, |
QFP048-P-0707 48-PIN LZ95D71 U95D71 LZ95D52/M LZ95D71 abstract |
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| Abstract: 1/2 frequency of the OSCI. Test terminal 1 A test pin. Sat open w to L level in tie Normal mode. Width of FR N A pulse to control PUIW width of FR (pin 6). ~nnact control output to RWI (pin 4) pin through CR delay circuit. Width of FR control input 5 TST2 ICD - , GND - 10 Vcc 11 An input pin to control pulse width of FR, Falling edge of FR is defined by leading edge of input pulse. A test pin. Sat open w to L level in tie Normal mode. A reset ... | Original |
24 pages, |
w730 QFP072-P-101 LHI pir LHi 944 72-PIN LZ95G71 LZ95G71 abstract |
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| Abstract: Ceramic flat package for HCC 4585 BK 6m„ 69 6„„ uuuuuuuu PIN CONNECTIONS FUNCTIONAL DIAGRAM ( A=B)OUT , • INPUT CURRENT OF 100 nA AT 18V AND 25°C FOR HCC DEVICE • 100% TESTED FOR QUIESCENT CURRENT • MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF , computer and logic applications that require the comparison of two 4-bit words. This logic circuit , units for comparison of more than 4 bits is accomplished as shown in typical application. ABSOLUTE ... | OCR Scan |
6 pages, |
4585B pin diagram of bf 494 transistor 4585B abstract |
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| Abstract: TSTi ICD - Test terminal 1 A test pin. Set open or to L level in the Normal mode. 3 RWO O uir Width of FR control output A pulse to control pulse width of FR (pin 6). Connect to RWI (pin 4) pin through CR delay circuit. 4 RWI IC - Width of FR control input An input pin to control pulse width of FR. Falling edge of FR is defined by leading edge of input pulse. 5 TST2 ICD - Test terminal 2 A test pin. Set , transfer pulse for CCD. Connect to ... | OCR Scan |
24 pages, |
QFP072-P-1010 LZ95 LHi 906 72-PIN 2AX SMD LZ95G71 LZ95G71 abstract |
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| Abstract: POLARITY PIN NAME FUNCTION 1 FCK o im Clock output for delay line A pulse for clock of CCD delay line. The frequency of the signal is 1/2 frequency of the OSCI. 2 TSTi ICD - Test terminal 1 A test pin. Set open or , of FR (pin 6). Connect to RWI (pin 4) pin through CR delay circuit. 4 RWI IC - Width of FR control input An input pin to control pulse width of FR. Falling edge of FR is defined by leading edge of input , horizontal transfer pulse for CCD. Connect to H2 of CCD. 12 NC - - No-connection A pin for no use. 13 CLP ... | OCR Scan |
24 pages, |
LZ95G71 LZ95G71 abstract |
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| Abstract: Fig-5 Data read-out Timing Diagram (M68 bus interface) 4.9 Connector Pin Assignment No. Signal , (Refer to "Fig-6 System Block Diagram" on next page.) Signal 1 Fourteen of through holes are , F2 Fig-6 System Block Diagram of this VFD Module 4.11 Outer Dimensions 85.0 +/-1.0 80.0 + , mounting holes. (This VFD module is capable to communicate some different type of bus systems such as i80 (Intel) or M68 (Motorola), 8-bit or 4-bit parallel data.) 2.2 High quality of display and ... | Original |
18 pages, |
vfd circuit single line diagram vfd -driver 16T202DA1J samsung VFD DISPLAY samsung VFD 16T202DA1 16T202DA1J abstract |
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| Abstract: VALID > Fig-5 Data read-out Timing Diagram (M68 bus interface) 4.9 Connector Pin Assignment Fourteen , ) X DC/DC Converter vbb Ef+ Fig-6 System Block Diagram of this VFD Module 4.11 Outer Dimensions , ODoflO â-¡â-¡â-¡OD HB8BH (Unit:mm) 4.13 Pattern Details Fig-8 14-pin Through Hole Dimensions 4.94 6.15 , ) - Changed 4.10 System Block Diagram Page 3/18 Page 4/18 Page 6/18 Issued by 7yi/^) Checked by , compatible interface and mounting holes. (This VFD module is capable to communicate some different type of ... | OCR Scan |
18 pages, |
samsung VFD DISPLAY samsung VFD 16T202DA1 16t202da1e Samsung VFD 16T202DA1E 16T202DA1E 16T202DA1E abstract |
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| Abstract: the signal is 1/2 the frequency of the OSCI. 2 TSTi ICD - Test terminal 1 A test pin. Set open or to , FR (pin 6). Connect to RWI (pin 4) pin through CR delay circuit 4 RWI IC - Width of FR control input An input pin to control pulse width of FR. Trailing edge of FR is defined by rising edge of input , CCD. Connect to ... | OCR Scan |
28 pages, |
QFP072-P-1010 LZ2313B5 LZ2313 bcp 846 57415 24128 ccd cmos 84 LZ95G55 LZ95G55 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| the value of the pins match or do not match a programmable pattern. • LED drive capability (20 mA) on -up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected -up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the ...continued Symbol Pin Type Description Product data Rev. 02 - 12 December 2003 9 of 55 9397 750 12286 © Koninklijke www.datasheetarchive.com/download/99213260-653674ZC/silverbox-cd.zip (P89LPC912_913_914-02.pdf) |
Philips | 18/06/2004 | 10852.57 Kb | ZIP | silverbox-cd.zip |
| Processor to the Timer Input Captures. RESET An active-low signal on this pin forces ini- tialization of the the input pins in order to minimize output distortion and start-up stabilisation time. Use of an .3.1 Introduction There are three sources of Reset: - External Reset (Reset pin) - Power-On Reset (Internal source User ROM: 24Kbytes n Data RAM: 384 bytes n EEPROM: 640 + 256 bytes n 56 pin Shrink Dual-in-Line plastic Compares (1 output pin) n 8-bit Analog-to-Digital converter n Programmable Watchdog Timer n 16 10-bit PWM www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5023.htm |
STMicroelectronics | 02/04/1999 | 224.47 Kb | HTM | 5023.htm |
| temperature: (3) Table 8. IC's power losses estimate With the aid of the diagrams shown in fig. 20 it is timing diagram of figure 8). V REV V CC 1 V PKmax waveforms of fig. 1. It is a two- step process. During the ON-time of the switch, energy is taken from the input and stored in the primary winding of the flyback transformer (actually, two coupled inductors Adragna OFFLINE FLYBACK CONVERTERS DESIGN METHODOLOGY WITH THE L6590 L6590 L6590 L6590 FAMILY The design of flyback www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7310.htm |
STMicroelectronics | 20/10/2000 | 95.66 Kb | HTM | 7310.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.8.2 Pin Configuration of XC161 XC161 XC161 XC161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.8.3 Pin Definitions of XC161 XC161 XC161 XC161 segment 192 (C0'0000H 0000H 0000H 0000H) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional of the XC161 XC161 XC161 XC161. Figure 2-1 XC161 XC161 XC161 XC161 Block Diagram C166S C166S C166S C166S V2 CPU Break Interface Injection . Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc161cj_v24.dip!/xc161cj/documents/xc161_umd_system_v1.1_2002_02.pdf |
Infineon | 09/02/2004 | 9113.92 Kb | DIP | xc161cj_v24.dip |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.8.2 Pin Configuration of XC161 XC161 XC161 XC161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.8.3 Pin Definitions of XC161 XC161 XC161 XC161 segment 192 (C0'0000H 0000H 0000H 0000H) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional of the XC161 XC161 XC161 XC161. Figure 2-1 XC161 XC161 XC161 XC161 Block Diagram C166S C166S C166S C166S V2 CPU Break Interface Injection . Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc161cj.dip!/xc161cj/documents/xc161_umd_system_v1.1_2002_02.pdf |
Infineon | 09/02/2004 | 9113.92 Kb | DIP | xc161cj.dip |
| ) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of figure shows the block diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and different kinds of memories, and proficient peripheral units integration. The following block diagram shows . Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc164cs.dip!/xc164cs/documents/xc164_umd_system_v1.1_2002_02.pdf |
Infineon | 09/02/2004 | 8731.91 Kb | DIP | xc164cs.dip |
| ) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of figure shows the block diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and different kinds of memories, and proficient peripheral units integration. The following block diagram shows . Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc164cs_v25.dip!/xc164cs/documents/xc164_umd_system_v1.1_2002_02.pdf |
Infineon | 09/02/2004 | 8731.91 Kb | DIP | xc164cs_v25.dip |
| ) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of figure shows the block diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and different kinds of memories, and proficient peripheral units integration. The following block diagram shows . Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc164cs_v27.dip!/xc164cs/documents/xc164_umd_system_v1.1_2002_02.pdf |
Infineon | 25/11/2003 | 10263.06 Kb | DIP | xc164cs_v27.dip |
| $ * $Date: 4 Apr 2009 $ * $Revision History : Modeled compensation pin of SG1525A SG1525A SG1525A SG1525A. * $Revision: 1 ; - input of error amp + 3 ; compensation pin + 4 ; soft start pin + 5 ; reset pin + 6 OUTPUT OF THE PWM DRIVER, REFER TO CHIP PINS FOR OTHER NODES. *|.OPTIONS ITL5=0 RELTOL=.01 abstol=1e-4 * Library of Switchmode Regulator Controller Chips * Copyright Cadence Design Systems, Inc contribution of their measurement-based models * included in this library www.datasheetarchive.com/files/spicemodels/misc/swit_reg.lib |
Spice Models | 01/09/2009 | 320.85 Kb | LIB | swit_reg.lib |
| various types of pin failure modes. It is important to note that the four main failure mechanisms functional failures can be seen on ESD failures. Figure 3 - Schematic of a typical I/O pin and the curve section through an I/O pad and output buffers. Figure 4 - Diagram of a cross-section through an I/O pad attached to the pad, which are the drains of the output n-channel and p-channel transistors for that pin contact spiking. Figure 5 - Diagram of contact spiking Thermal oxide degradation and poly melt www.datasheetarchive.com/files/motorola/faq/index.htm |
Motorola | 21/02/2000 | 441.5 Kb | HTM | index.htm |