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LT1074HVCT7#44 Linear Technology Step-Down Switching Regulator; Package: TO-220; No of Pins: 7; Temperature Range: 0°C to +70°C ri Buy
LTC4308IMS8 Linear Technology Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; No of Pins: 8; Temperature Range: -40°C to +85°C ri Buy
LTC4308IDD Linear Technology Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; No of Pins: 8; Temperature Range: -40°C to +85°C ri Buy

pin diagram of bf 494

Catalog Datasheet Results Type PDF Document Tags
Abstract: period of BF (pin 9) otherwise, stays at H level._ TVM2 IC TV mode 2 Set to level. TVMi IC TV mode 1 An , The frequency of the signal is 1/4 the 4FSC frequency (pin 43). The signal is reset by color frame pulses CFMI (pin 2)._ SC, Subcarrier output 2 An output pin for color subcarrier. When the phase of SC,(pin 4) is 180 degree, the phase of SC3 is 90 degree in NTSC mode ; in PAL mode, the phase of SC2 is 90 , drive output An output pin for wide Hor. "drive pulse. The pulse width is equal to that of PBLK (pin 39 ... OCR Scan
datasheet

9 pages,
286.92 Kb

sharp 21" color tv diagram ic 311 comparator 3 phase signal generator ic melec h 540 pin diagram of bf 494 IC 566 function generator SHARP COLOR TELEVISION datasheet abstract
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Abstract: select and LZ95D71M LZ95D71M is used, set to H level. The polar ity of CBLK (pin 16), PBLK (pin 39), BF (pin 9 , device specification sheets before using any SHARP'S device SHARP BLOCK DIAGRAM SELs SELi BF VRI WHD , for color subcarrier in NTSC mode. The frequency of the signal is 1 /4 the CLKI (pin 27) SCi JU , mode. When the phase of SCi (pin 4) is 180 degree, the SC2 JIT Subcarrier output 2 phase of , of PBLK (pin 39) and the repetition is horizontal frequency. An input pin for resetting internal ... OCR Scan
datasheet

18 pages,
389 Kb

BF 987 equivalent LZ95D52/M LZ95D42/M LZ95D71M LZ95D52 QFP044-P-1010 LZ95D52M QFP048-P-0707 LZ95D52/M abstract
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Abstract: during the blanking period of BF (pin 9) otherwise, stays at H level._ A , color subcarrier. The frequency of the signal is 1/4 The 4FSC frequency (pin 43). The signal is reset by , subcarrier. When the phase of SC! (pin 4) is 180 degree, the phase of SC2 is 90 degree in NTSC mode; in PAL mode, the phase of SC, is 90 degree when LSW (pin 14) is Low and 270 degree when LSW is High._ A grounding pin. An output pin for wide Hor. drive pulse. The pulse width is equal to that of PBLX ... OCR Scan
datasheet

8 pages,
208.5 Kb

lz93n LZ93N LZ93N19 LZ93N abstract
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Abstract: mode: L level during the blanking period of BF (pin 9) otherwise, stays at H level. 11 tvm2 IC , 4 sc! 0 Subcarrier output 1 An output pin for color subcarrier. The frequency of the signal is 1/4 , Subcarrier output 2 An output pin for color subcarrier. When the phase of SC,(pin 4) is 180 degree, the phase of SC2 is 90 degree in NTSC mode ; in PAL mode, the phase of SC2 is 90 degree when LSW (pin 14) is , drive output An output pin for wide Hor. "drive pulse. The pulse width is equal to that of PBLK (pin 39 ... OCR Scan
datasheet

9 pages,
287.57 Kb

pin diagram of bf 494 LZ2111J LZ2112J LZ2122J LZ92E60 LZ92E62 LZ93N25 RS-170 LZ2124J LZ2121J LZ2121 datasheet abstract
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Abstract: 16), PBLK (pin 39), BF (pin 9) end WBLK (pin 42) change, and the phase of ENCP (pin 15) and HBLK , Single +5 V power supply . Package : 48-pin QFP(QFP048-P-0707 QFP048-P-0707) ~~~ I in tie abwnce of confImtIOn by , using any WARPS devhce" s~ U95D52/M U95D52/M BLOCK DIAGRAM SEL2 SELI BF VRI WHD GND , An output pin for color subcarrier in NTSC mode. The frequency of the signal is 1/4 the CLKI (pin 27 , color subcarrier in NTSC mode. When the phase of SC I (pin 4) is 180 degree, the 5 SC2 o N ... Original
datasheet

25 pages,
477.49 Kb

QFP048-P-0707 48-PIN LZ95D71 U95D71 LZ95D52/M LZ95D71 abstract
datasheet frame
Abstract: 1/2 frequency of the OSCI. Test terminal 1 A test pin. Sat open w to L level in tie Normal mode. Width of FR N A pulse to control PUIW width of FR (pin 6). ~nnact control output to RWI (pin 4) pin through CR delay circuit. Width of FR control input 5 TST2 ICD - , GND - 10 Vcc 11 An input pin to control pulse width of FR, Falling edge of FR is defined by leading edge of input pulse. A test pin. Sat open w to L level in tie Normal mode. A reset ... Original
datasheet

24 pages,
716.26 Kb

w730 SPI CCD Driver QFP072-P-101 PIR SENSOR 750 s LHI pir LHi 944 72-PIN 1C44 LZ95G71 LZ95G71 abstract
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Abstract: Ceramic flat package for HCC 4585 BK 6m„ 69 6„„ uuuuuuuu PIN CONNECTIONS FUNCTIONAL DIAGRAM ( A=B)OUT , • INPUT CURRENT OF 100 nA AT 18V AND 25°C FOR HCC DEVICE • 100% TESTED FOR QUIESCENT CURRENT • MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF , computer and logic applications that require the comparison of two 4-bit words. This logic circuit , units for comparison of more than 4 bits is accomplished as shown in typical application. ABSOLUTE ... OCR Scan
datasheet

6 pages,
218.77 Kb

4585B 4585 cmos pin diagram of bf 494 transistor datasheet abstract
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Abstract: TCD6220AF TCD6220AF TCD5241BD TCD5241BD, TCD5240D TCD5240D, TCD5251BD TCD5251BD, TCD5250D TCD5250D TIMING PULSE GENERATING IC The CMOS LSI of , · Generation of ail timing pulses required to drive TCD5241BD TCD5241BD, TCD5251BD TCD5251BD, TCD5240D TCD5240D and TCD5250D TCD5250D. · Correspondence with electronic shutter from 1/50, 1 /6 0 s to 1/10000 s. · Generation of sampling pulses for the CDS signal processing. Generation of controlling pulse for the electronic shutter , TCD6220AF TCD6220AF TC6220AF TC6220AF TCD6220AF TCD6220AF BLOCK DIAGRAM ^ 7 2 5 0 00214?^ G IB 281 ... OCR Scan
datasheet

29 pages,
592.75 Kb

TCD5241BD TCD6220AF TCD5240D TCD5251BD TCD5250D TC6220AF TCD6220AF abstract
datasheet frame
Abstract: TSTi ICD - Test terminal 1 A test pin. Set open or to L level in the Normal mode. 3 RWO O uir Width of FR control output A pulse to control pulse width of FR (pin 6). Connect to RWI (pin 4) pin through CR delay circuit. 4 RWI IC - Width of FR control input An input pin to control pulse width of FR. Falling edge of FR is defined by leading edge of input pulse. 5 TST2 ICD - Test terminal 2 A test pin. Set , transfer pulse for CCD. Connect to ... OCR Scan
datasheet

24 pages,
740.77 Kb

QFP072-P-1010 LZ95 LHi 906 72-PIN 2AX SMD LZ95G71 LZ95G71 abstract
datasheet frame
Abstract: POLARITY PIN NAME FUNCTION 1 FCK o im Clock output for delay line A pulse for clock of CCD delay line. The frequency of the signal is 1/2 frequency of the OSCI. 2 TSTi ICD - Test terminal 1 A test pin. Set open or , of FR (pin 6). Connect to RWI (pin 4) pin through CR delay circuit. 4 RWI IC - Width of FR control input An input pin to control pulse width of FR. Falling edge of FR is defined by leading edge of input , horizontal transfer pulse for CCD. Connect to H2 of CCD. 12 NC - - No-connection A pin for no use. 13 CLP ... OCR Scan
datasheet

24 pages,
740.11 Kb

ic 3524 pin diagram LZ95G71 LZ95G LZ95G71 abstract
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The drain pin of the IC needs to be properly clamped to prevent the spike due to the transformer V inmin (see the timing diagram of figure 8). V REV V CC 1 V PKmax V R will be illustrated with reference to the basic circuit and the waveforms of fig. 1. It is a two- step process. During the ON-time of the switch, energy is taken from the input and stored in the primary winding of the flyback transformer (actually, two coupled inductors). At the secondary side, the catch diode
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STMicroelectronics 20/10/2000 95.66 Kb HTM 7310.htm
types of pin failure modes. It is important to note that the four main failure mechanisms (discussed in functional failures can be seen on ESD failures. Figure 3 - Schematic of a typical I/O pin and the curve section through an I/O pad and output buffers. Figure 4 - Diagram of a cross-section through an I/O pad attached to the pad, which are the drains of the output n-channel and p-channel transistors for that pin , such as contact spiking. Figure 5 - Diagram of contact spiking Thermal oxide degradation and poly
www.datasheetarchive.com/files/motorola/faq/index.htm
Motorola 21/02/2000 441.5 Kb HTM index.htm
types of pin failure modes. It is important to note that the four main failure mechanisms (discussed in functional failures can be seen on ESD failures. Figure 3 - Schematic of a typical I/O pin and the curve section through an I/O pad and output buffers. Figure 4 - Diagram of a cross-section through an I/O pad attached to the pad, which are the drains of the output n-channel and p-channel transistors for that pin , such as contact spiking. Figure 5 - Diagram of contact spiking Thermal oxide degradation and poly
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Motorola 21/02/2000 441.62 Kb HTM index-v1.htm
Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and Pinning Draft User's proficient peripheral units integration. The following block diagram shows the structure of CPU: . Figure given to describe certain components and shall not be considered as warranted characteristics. Terms of not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated
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Infineon 09/02/2004 8731.91 Kb DIP xc164cs.dip
Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and Pinning Draft User's proficient peripheral units integration. The following block diagram shows the structure of CPU: . Figure given to describe certain components and shall not be considered as warranted characteristics. Terms of not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated
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Infineon 09/02/2004 8731.91 Kb DIP xc164cs_v25.dip
Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of diagram of the XC164 XC164 XC164 XC164. XC164 XC164 XC164 XC164 Derivatives System Units Architectural Overview and Pinning Draft User's proficient peripheral units integration. The following block diagram shows the structure of CPU: . Figure given to describe certain components and shall not be considered as warranted characteristics. Terms of not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated
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Infineon 25/11/2003 10263.06 Kb DIP xc164cs_v27.dip
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.8.2 Pin Configuration of XC161 XC161 XC161 XC161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.8.3 Pin Definitions of XC161 XC161 XC161 XC161 4.4 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94 segment 192 (C0'0000H 0000H 0000H 0000H) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional the block diagram of the XC161 XC161 XC161 XC161. Figure 2-1 XC161 XC161 XC161 XC161 Block Diagram C166S C166S C166S C166S V2 CPU Break Interface
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Infineon 09/02/2004 9113.92 Kb DIP xc161cj.dip
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.8.2 Pin Configuration of XC161 XC161 XC161 XC161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.8.3 Pin Definitions of XC161 XC161 XC161 XC161 4.4 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94 segment 192 (C0'0000H 0000H 0000H 0000H) - Start address of internal boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional the block diagram of the XC161 XC161 XC161 XC161. Figure 2-1 XC161 XC161 XC161 XC161 Block Diagram C166S C166S C166S C166S V2 CPU Break Interface
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Infineon 09/02/2004 9113.92 Kb DIP xc161cj_v24.dip
16-Bit Single-Chip Microcontro l ler wi th 166SV2 166SV2 166SV2 166SV2 Core Volume 1 (of 2): System Uni ts Edition certain components and shall not be considered as warranted characteristics. Terms of delivery and rights warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or
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Infineon 25/11/2003 8106.77 Kb DIP xc161cj_v26.dip
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.8.2 Pin Configuration of boot ROM changed to segment 191 (BF'0000H 0000H 0000H 0000H) - Additional start address of internal Program SRAM The following figure shows the block diagram of the XC167 XC167 XC167 XC167. Figure 2-1 XC167 XC167 XC167 XC167 Block Diagram : The block diagram above shows the fully equipped XC167 XC167 XC167 XC167 in 144-pin package, as described in this given to describe certain components and shall not be considered as warranted characteristics. Terms of
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Infineon 25/11/2003 10493 Kb DIP xc167ci_v24.dip