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SN74151AN Texas Instruments 8-Line To 1-Line Data Selector / Multiplexer 16-PDIP 0 to 70 visit Texas Instruments
PMP7410 Texas Instruments Uses TPS40210 in Sepic configuration to generate 14.4V output visit Texas Instruments
DLPR910AYVA Texas Instruments DLPR910 Configuration PROM for DLPC910 48-DSBGA visit Texas Instruments
DLPR910YVA Texas Instruments DLPR910 Configuration PROM for DLPC910 48-DSBGA visit Texas Instruments
ISL95520HRZ-T Intersil Corporation SMBus Interface Hybrid Power Boost (HPB) and Narrow VDC (NVDC) Configurations Combo Battery Charger; QFN32; Temp Range: See Datasheet visit Intersil Buy
ISL95520HRZ Intersil Corporation SMBus Interface Hybrid Power Boost (HPB) and Narrow VDC (NVDC) Configurations Combo Battery Charger; QFN32; Temp Range: See Datasheet visit Intersil Buy

pin configuration of 74151

Catalog Datasheet MFG & Type PDF Document Tags

74151 mux

Abstract: circuit diagram of MUX 74151 (LSul) is 20/iA Iih and -0.4mA In- PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) â sCZ ig , and duration of the short circuit should not exceed one second. 4. Measure Ice on the 74151 with E , Sgnetics Logic Products 74151, LS151, S151 Multiplexers 8-lnput Multiplexer Product , -state version DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, Si, S2. True (Y) and Complement (Y
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74151 mux circuit diagram of MUX 74151 MUX 74151 LS 74151 of MUX 74151 74151 8 by 1 Multiplexer 74LS151 74S151 N74151N N74LS151N N74S151N N74LS151D

LS 74151

Abstract: 74151 16 to 1 Signetics 74151, LS151, S151 Multiplexers 8-Input Multiplexer Product Specification Logic , TYPE TYPICAL PROPAGATION DELAY (ENABLE TO Y) TYPICAL SUPPLY CURRENT (TOTAL) 74151 74LS151 74S151 18ns 12ns 9ns 29mA 6mA 45mA DESCRIPTION The '151 is a logical im plem entation of a single-pole, 8-position switch with the switch position controlled by the state of three S elect inputs, S0, S , . W hen E is HIGH, the Y output is HIGH and the Y output is LOW, regard less of all other inputs. The
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74151 16 to 1 74151 waveform 74151 74151 PIN DIAGRAM 74151 PIN DIAGRAM for multiplexer circuit multiplexers 74 LS 151 N74S151D

Multiplexer IC 74151

Abstract: pin configuration IC 74151 Iil, and 74LS unit load (LSul) is 20/iA Iih and -0.4mA lJ L . PIN CONFIGURATION LOGIC SYMBOL , duration of the short circuit should not exceed one second. 4. Measure Icc on the 74151 with E and S o - S , Signetics 74151, LS151, S151 Multiplexers 8-lrtput Multiplexer Product Specification Logic , TYPE 74151 74LS151 74S151 TYPICAL PROPAGATION DELAY (ENABLE TO Y) 18ns 12ns 9ns TYPICAL SUPPLY CURRENT (TOTAL) 29mA 6mA 45mA DESCRIPTION The '151 is a logical implementation of a single-pole, 8
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Multiplexer IC 74151 pin configuration IC 74151 pin diagram of ic 74151 ic 74151 specification pin configuration TTL 74151 IC 74151 WF07570S

74151 PIN DIAGRAM

Abstract: 74151 pin configuration ) is 20jjA l!H and -0.4mA l,L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2 1 15 14 13 , duration of the short circuit should not exceed one second. 4. Measure Ice on the 74151 with Ã' and S0- S2 , '¢ See '251 for 3-state version DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S-|, S2. True (Y) and , HIGH and the Y output is LOW, regardless of all other inputs. The logic function provided at the output
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74151 pin configuration pin configuration of 74151 pin diagram of 74151 74151 multiplexer PIN CONFIGURATION 74151 74151 8 of 1

full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 be reduced by an order of magnitude depending on the system configuration. Power requirements can be , contains some 17 logic func tions most of which are MacroFunctions. The overall configuration of the chip is shown in the final figure of this data sheet. The functions included are; 7485 74279 74151 74138 , capable of implementing up to 2100 equivalent gates of custom and conventional logic. · Pre-programmed to contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of
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full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 pin configuration of IC 74138 Application of Multiplexer IC 74151 EP1800JC-EV1 EP1800 0UT20 0UT21 OUT22 0UT23

pin configuration IC 74151

Abstract: Multiplexer IC 74151 manipulation. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) '3 [I < 2OE HE 'oil YOE ?E ëE , Signelics 74151, LS151, S151 Multiplexers 8-Input Multiplexer Product Specification Logic , TYPE 74151 74LS151 74S151 TYPICAL PROPAGATION DELAY (ENABLE TO Y) 18ns 12ns 9ns TYPICAL SUPPLY CURRENT (TOTAL) 29mA 6mA 45mA DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S2. True (Y) and Com
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pin diagram of ic 74ls151 Multiplexer IC 74151 data

TFC 718 S

Abstract: tfc 718 OKI Semiconductor MSM18T0000 1.0|im Sea of Gates Family for High-Performance, 5 Volt Applications DESCRIPTION O K I's M SM 18T0000 Sea of Gates fam ily is a high-perform ance, high-density sem icustom , from O KI's 1 Meg DRAM manufacturing process. The M SM 18T0000 Family has been designed for high pin , pin count capability is achieved by utilizing reduced pitch I /O cells and O KI's high capacity assem bly techniques. O K I's M SM 18T0000 Sea of Gates fam ily includes speed and density logic which perm
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TFC 718 S tfc 718 74151s 10T0000 HP9000 RS6000 PC386 MSM18T

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 types of packages â'¢ 24-to 64-pin DIP â'¢ 20-to 84-pin PLCC â'¢ 24-to 160-pin FLAT â'¢ 72- to 208-pin , number of the pins can be increased easily as an option. 56 â  MASTER CHIP CONFIGURATION Item Symbol , including the pin capacity of package and the pad capacity inside chip. 160 â'¢ AC characteristics (VDD = , SUPPLY PINS AND STANDARD PIN LAYOUT FOR EACH PACKAGE Package Name of series (number of pad) Standard number of pins Standard PINOUT (pin number) Type No. of pins 70V 71V 72V (74) 73V 74V (88
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asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000

counter 74168

Abstract: 3-8 decoder 74138 SUPPLY PINS AND STANDARD PIN LAYOUT FOR EACH PACKAGE Package Name of series (number of pad) Standard number of pins Standard pin {pin numb out 3r) Type No. of pins 70V 71V 72 V (74) 73V 74V (88 , Manufacturer Package Name of series (number of pad) Standard number of pins Standard PINOUT (pin , structure. This series has the features to easily realize functions of the schmitt trigger, crystal , is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master
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counter 74169 74183 adder 74169 binary counter 74381 alu 74175 flip flops flip flop 74379 MSM75V000 MSM-76V000 MSM77V000 MSM78V000

truth table for ic 74138

Abstract: 16CUDSLR cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS. A+PLUS includes the A ltera Design Processor (ADP), w hich consists of integ rated m od u les that
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truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74147 pin diagram and truth table pin diagram of IC 74184

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop integration (700 to 10,000 gates) â'¢ Various types of packages â'¢ 24-to 64-pin DIP â'¢ 20-to 84-pin PLCC â'¢ 24- to 160-pin F LAT â'¢ 72- to 208-pin PGA (including the plastic PGA) â'¢ Various types of , pin capacity of package and the pad capacity inside chip. 106 This Material Copyrighted By Its , POWER-SUPPLY PINS PIN LAYOUT FOR EACH PACKAGE AND STANDARD o: under development Package Name of series (number of pads) Standard number of pins Standard PINOUT (pin number) No. of pins 70H 71 H 72H (74
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74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000

74118

Abstract: pin configuration IC 74151 specifications are not guaranteed when driving the PCK111 single-endedly. PINNING Pin configuration VCCO VCCO , . Pin configuration Pin description SYMBOL VCC CLK_SEL CLK0, CLK0 VBB CLK1, CLK1 VEE VCCO Q0-Q9 PIN , data Supersedes data of 2002 Feb 15 2002 Dec 13 Philips Semiconductors Philips Semiconductors , voltage VEE range of -2.25 V to -3.8 V for ECL · Low voltage VCC range of +2.375 V to +3.8 V for PECL · 75 , met, it is necessary that both sides of the differential output are terminated into 50 , even if only
Philips Semiconductors
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74118 internal pin diagram of IC 74151 MC100EP111 PCK111/PCK210/PCKEL14/PCKEP14

DALSA AREA CCD

Abstract: Diode A3X configuration The FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 (quadrant W) is marked with a gold SYMBOL VNS TG VNS VNS VPS SFD SFS VCS , measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the , VCS VCS OUT VNS DOT ON TOP OF CCD INDICATES LOCATION OF PIN 1 Figure 12- Pin (top view) Figure 13 -configuration Pin configuration (top view) November 3, 2009 17 DALSA Professional
DALSA Professional Imaging
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DALSA AREA CCD Diode A3X 4992H FTF5066C/HG FTF5066C/IG FTF5066C/EG FTF5066C/TG

pin diagram for IC cd 1619 fm receiver

Abstract: ic 7490 pin diagram decade counter valid when the positive transition of a DIGIT OUTPUT occurs. STORE, Pin 15 The STORE input is used to , the scan counter. SCAN. Pin 21 The MK50395 has an internal scan oscillator. The frequency of the , brightness can be controlled by the duty cycle of the external scan oscillator. VDD, Pin 22 VDD is the , be changed during the positive transition of the COUNT input. CARRY, Pin 38 The CARRY output goes , positive-going edges of a pulse train at the COUNT input (pin 36) are standardized by an internal monostable to a
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pin diagram for IC cd 1619 fm receiver ic 7490 pin diagram decade counter MK50395N MK5009 counter meter mk50395 ic sn7490 pin diagram MK50395/6/7 MK50396 MK50397 CD4043

A1W TRANSISTOR

Abstract: LOCATION OF PIN 1 Figure 12- Pin (top view) Figure 13 -configuration Pin configuration (top view , reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe , Product Specification 33M Full-Frame CCD Image Sensor Pin configuration The FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 , professional digital photography applications, with very low dark current and a linear dynamic range of over 12
DALSA Professional Imaging
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A1W TRANSISTOR
Abstract: LOCATION OF PIN 1 Figure 12- Pin (top view) Figure 13 -configuration Pin configuration (top view , reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe , Product Specification 33M Full-Frame CCD Image Sensor Pin configuration The FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 , professional digital photography applications, with very low dark current and a linear dynamic range of over 11 DALSA Professional Imaging
Original

CG1 HOYA

Abstract: diode a4W measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the , Image Sensor FTF5066C Pin configuration The FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 (quadrant W) is marked , A2 VPS VCS OUT VNS DOT ON TOP OF CCD INDICATES LOCATION OF PIN 1 Figure 12- Pin-configuration (top view) Figure 13 Pin configuration (top view) July 1, 2008 17 DALSA Professional
DALSA Professional Imaging
Original
CG1 HOYA diode a4W ccd color Linear Image Sensor 74131 CCD IMAGE BAS28

MK50395N

Abstract: 7490 Decade Counter negative edge of count input. PACKAGE DESCRIPTION 40-pin Dual In-Line Plastic â r f/m" -J Iâ'",» - , bringing the load counter pin 31 high at the end of digit 4 thru digit 1 time and then bringing the store pin 15 low after the leading edge of D3, D2, and D1 with a delay. The four BCD output pins 11-14 are , the end of P6. When this occurs the sign flip-flop is set, and the level at pin 40 goes high, changing , three highest digits of the latch are set into the counter by bringing the load counter pin 31 high from
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7490 Decade Counter MK 50395 SN7490 decode counter 7490 4 digit COUNTER LED bcd Two Digit counter diagram MK50396N MK50397N

7408, 7404, 7486, 7432 use NAND gate

Abstract: JLCC-68 have up to 2304 bits of RAM organized In an optional by-nlne memory configuration that Is system , determined by the location on the chip of the associated circuitry and any pin location requirements that may , MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide , of RAM, 4608 bits of ROM or for bus Interface circuits with high-drive requirements. The AVB , Interfacing with bus organized logic.The AVM (MB66xxxx) series of memory arrays Include, In addition to the
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LCC-64 JLCC-68 7408, 7404, 7486, 7432 use NAND gate ci 74386 jLCC68 74153 full adder cI 74150 MB65XXXX MB66XXXX MB67XXXX C4002

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 Is determined by the location on the chip of the associated circuitry and any pin looatlon , Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to , , 2304 bits of RAM, 4608 bits of ROM or for bus Interface circuits with hlgh-drtve requirements. The AVB , Interfacing with bus organized loglc.The AVM (MB66xxxx) series of memory arrays Include, In addition to the 1.5K, 2.3K, and 4K gates of logic, two basic sizes of static registered memories: The C4002 and C l 502
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up down counter using IC 7476 74154 shift register IC full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 pin function of ic 74390 0010S 350AVB 540AVB S50AVB
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