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pin configuration of 74151

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Abstract: ,L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2 1 15 14 13 12 Vcc - Pin 16 GND = , for 3-state version DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S-|, S2. True (Y) and , HIGH and the Y output is LOW, regardless of all other inputs. The logic function provided at the output , ,SO*SI«S2 + l7»So«Si«S2 In one package the '151 provides the ability to select from eight sources of ... OCR Scan
datasheet

5 pages,
122.75 Kb

S151 N74S151N 74151 8 of 1 multiplexer 74151 PIN CONFIGURATION 74151 circuit diagram of MUX 74151 74151 waveform 74LS151 74151 8 by 1 Multiplexer 74151 multiplexer pin diagram of 74151 74151 mux 74151 LS151 LS151 abstract
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Abstract: i2 13 (io> (13) "O-f-°>- (11) fc^ «0-p>o- Y I (5) I Vcc - Pin 16 GND - Pin 8 , Sgnetics Logic Products 74151, LS151 LS151, S151 Multiplexers 8-lnput Multiplexer Product , DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, Si, S2. True (Y) and Complement (Y) outputs are both , , regardless of all other inputs. The logic function provided at the output is: Y - E.(lo«5o*Sl«52 ll *So*Si ... OCR Scan
datasheet

5 pages,
126.59 Kb

74 LS 151 Logic DIAGRAM LS TTL family characteristics 74ls151 74151 16 to 1 74151 8 of 1 pin configuration of 74151 74151 pin configuration 74151 waveform 74151 multiplexer MUX 74LS151 function of 74151 74151 PIN DIAGRAM 74151 LS151 LS151 abstract
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Abstract: Iil, and 74LS unit load (LSul) is 20/iA Iih and -0.4mA lJ L . PIN CONFIGURATION LOGIC SYMBOL , duration of the short circuit should not exceed one second. 4. Measure Icc on the 74151 with E and S o - S , Signetics 74151, LS151 LS151, S151 Multiplexers 8-lrtput Multiplexer Product Specification Logic , TYPE 74151 74LS151 74LS151 74S151 74S151 TYPICAL PROPAGATION DELAY (ENABLE TO Y) 18ns 12ns 9ns TYPICAL SUPPLY CURRENT (TOTAL) 29mA 6mA 45mA DESCRIPTION The '151 is a logical implementation of a single-pole ... OCR Scan
datasheet

5 pages,
125.1 Kb

ic 74151 specification of ic 74151 74151 multiplexer ic 74ls151 notes 74151 pin diagram of 74151 TTL IC pin diagram of ic 74ls151 74151 PIN DIAGRAM TTL 74151 IC 74151 pin diagram of ic 74151 pin configuration IC 74151 LS151 LS151 abstract
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Abstract: PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 'S[T i2 u HI VCC U 13'5 nm jH'7 Ü , Signetics 74151, LS151 LS151, S151 Multiplexers 8-Input Multiplexer Product Specification Logic , TYPE TYPICAL PROPAGATION DELAY (ENABLE TO Y) TYPICAL SUPPLY CURRENT (TOTAL) 74151 74LS151 74LS151 74S151 74S151 18ns 12ns 9ns 29mA 6mA 45mA DESCRIPTION The '151 is a logical im plem entation of a single-pole, 8-position switch with the switch position controlled by the state of three S elect inputs, S0, S ... OCR Scan
datasheet

5 pages,
223.05 Kb

multiplexers 74 LS 151 74151 8 of 1 74151 PIN DIAGRAM 74151 waveform 74151 16 to 1 LS 74151 LS151 LS151 abstract
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Abstract: manipulation. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) '3 [I < 2OE HE 'oil YOE ?E ëE G , Signelics 74151, LS151 LS151, S151 Multiplexers 8-Input Multiplexer Product Specification Logic , TYPE 74151 74LS151 74LS151 74S151 74S151 TYPICAL PROPAGATION DELAY (ENABLE TO Y) 18ns 12ns 9ns TYPICAL SUPPLY CURRENT (TOTAL) 29mA 6mA 45mA DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S2. True (Y ... OCR Scan
datasheet

5 pages,
118.46 Kb

ls151 ic 74151 74151 8 by 1 Multiplexer pin diagram of ic 74ls151 pin configuration IC 74151 Multiplexer IC 74151 LS151 LS151 abstract
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Abstract: be reduced by an order of magnitude depending on the system configuration. Power requirements can be , contains some 17 logic func tions most of which are MacroFunctions. The overall configuration of the chip is shown in the final figure of this data sheet. The functions included are; 7485 74279 74151 74138 , capable of implementing up to 2100 equivalent gates of custom and conventional logic. · Pre-programmed to contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of ... OCR Scan
datasheet

7 pages,
271.01 Kb

7483 half adder multiplexer 74151 sn 7449 function table 74151 chip 74151 adder IC 74279 pin configuration of d flip flip 7474 ic ttl 74138 TTL 74194 MSI IC 74138 decoder Application of Multiplexer IC 74151 IC 74138 decoder pin configuration of IC 74138 EP1800JC-EV1 EP1800JC-EV1 EP1800JC-EV1 abstract
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Abstract: OKI Semiconductor MSM18T0000 MSM18T0000 1.0|im Sea of Gates Family for High-Performance, 5 Volt Applications DESCRIPTION O K I's M SM 18T0000 18T0000 Sea of Gates fam ily is a high-perform ance, high-density sem icustom , from O KI's 1 Meg DRAM manufacturing process. The M SM 18T0000 18T0000 Family has been designed for high pin , pin count capability is achieved by utilizing reduced pitch I /O cells and O KI's high capacity assem bly techniques. O K I's M SM 18T0000 18T0000 Sea of Gates fam ily includes speed and density logic which perm ... OCR Scan
datasheet

9 pages,
288.52 Kb

tfc 718 TFC 718 S 18T0000 18T0000 abstract
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Abstract: Figure 1. Pin configuration Pin description SYMBOL VCC CLK_SEL CLK0, CLK0 VBB CLK1, CLK1 VEE VCCO , data Supersedes data of 2002 Feb 15 2002 Dec 13 Philips Semiconductors Philips Semiconductors , voltage VEE range of -2.25 V to -3.8 V for ECL · Low voltage VCC range of +2.375 V to +3.8 V for PECL · 75 , met, it is necessary that both sides of the differential output are terminated into 50 , even if only , skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ... Original
datasheet

13 pages,
116.67 Kb

pin configuration IC 74151 PCK111 PCK111 abstract
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Abstract: cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS. A+PLUS includes the A ltera Design Processor (ADP), w hich consists of integ rated m od u les that ... OCR Scan
datasheet

8 pages,
291.6 Kb

7408 ic truth table 74158 free ic 74183 alu 74162 truth table logicaps Flip-Flop 7471 freqdiv pin diagram decoder 74147 Truth Table 74280 pin diagram of IC 74184 74175 truth table 74147 pin diagram and truth table IC 74373 truth table datasheet abstract
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Abstract: configuration The FTF5066C FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 (quadrant W) is marked with a gold SYMBOL VNS TG VNS VNS VPS SFD SFS VCS OG , DOT ON TOP OF CCD INDICATES LOCATION OF PIN 1 Figure 12- Pin (top view) Figure 13 -configuration , directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the , The image clock phases of quadrant W are internally connected to X, and Y is connected to Z. PIN # W ... Original
datasheet

18 pages,
889.45 Kb

FTF5066C FTF5066C abstract
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