NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ,L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2 1 15 14 13 12 Vcc - Pin 16 GND = , for 3-state version DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S-|, S2. True (Y) and , HIGH and the Y output is LOW, regardless of all other inputs. The logic function provided at the output , ,SO*SI«S2 + l7»So«Si«S2 In one package the '151 provides the ability to select from eight sources of ... | OCR Scan |
5 pages, |
N74S151D N74S151N 74151 8 by 1 Multiplexer S151 Signetics 74151 74151 8 of 1 multiplexer 74151 74151 waveform circuit diagram of MUX 74151 TTL 74151 pin diagram of 74151 74151 multiplexer 74151 mux LS151 LS151 abstract |
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| Abstract: i2 13 (io> (13) "O-f-°>- (11) fc^ «0-p>o- Y I (5) I Vcc - Pin 16 GND - Pin 8 , Sgnetics Logic Products 74151, LS151 LS151, S151 Multiplexers 8-lnput Multiplexer Product , DESCRIPTION The '151 is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, Si, S2. True (Y) and Complement (Y) outputs are both , , regardless of all other inputs. The logic function provided at the output is: Y - E.(lo«5o*Sl«52 ll *So*Si ... | OCR Scan |
5 pages, |
74 LS 151 Logic DIAGRAM multiplexer 74151 74151 16 to 1 74151 pin configuration function of 74151 MUX 74LS151 74151 8 of 1 pin configuration of 74151 74151 8 by 1 Multiplexer 74151 waveform 74151 multiplexer 74151 PIN DIAGRAM LS151 LS151 abstract |
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| Abstract: interconnection resources. The final configuration of the three main programmable elements Is determined by the , 4- £ £ £ k configuration memory i fc\ ir»D v » Logic CeN is a trademark of Xilinx, Inc. IBM , array of configuration memory cells. The configuration bit stream is loaded into the LCA device at , process is independent of the user logic functions. Configuration Memory The static memory cell used for , re-written. A static configuration memory cell is loaded with one bit of the configuration bit stream and ... | OCR Scan |
66 pages, |
74151 MUX 8-1 applications 7483 4-bits parallel adder 74163 four bit binary counter 74257 grid tie inverter schematic TTL johnson ring counter pin diagram encoder 74147 74595 grid tie inverters circuit diagrams CI 74241 ttl 7483 FULL ADDER DN 74352 Am3020/3030/3042/3064/3090 Am3020/3030/3042/3064/3090 abstract |
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| Abstract: valid when the positive transition of a DIGIT OUTPUT occurs. STORE, Pin 15 The STORE input is used to , the scan counter. SCAN. Pin 21 The MK50395 MK50395 has an internal scan oscillator. The frequency of the , can be controlled by the duty cycle of the external scan oscillator. VDD, Pin 22 VDD is the negative , INHIBIT can be changed during the positive transition of the COUNT input. CARRY, Pin 38 The CARRY output , following description: THE COUNTER The positive-going edges of a pulse train at the COUNT input (pin 36 ... | OCR Scan |
23 pages, |
internal diagram of 7490 IC decode counter 7490 Application of Multiplexer IC 74151 12 hour digital clock using 7490 pin diagram of ic 74151 CI 74151 SN7490 ic 7490 ic 7490 7 segment decade counter MULTIPLEXER IC SN74151 ic sn7490 pin diagram MK50395/6/7 MK50395/6/7 abstract |
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| Abstract: when the positive transition of a DIGIT OUTPUT occurs. STORE, Pin 15 The STORE input is used to control , SCAN. Pin 21 The MK50395 MK50395 has an internal scan oscillator. The frequency of the scan oscillator is , duty cycle of the external scan oscillator. VDD, Pin 22 VDD is the negative supply input and is , COUNT input. CARRY, Pin 38 The CARRY output goes high with the leading edge of the COUNT input at the , leading edge of the count input and is also a push-pull output. UP/DOWN, Pin 40 The counter will increment ... | OCR Scan |
23 pages, |
decode counter 7490 pin diagram of ic 74151 Application of Multiplexer IC 74151 BCD thumbwheel mk5009 7490 bcd 7 segment ttl pin diagram for IC cd 1619 p 7490 bcd counter CI 74151 ic sn7490 pin diagram ic 7490 pin diagram decade counter 7490 Decade Counter pin connections MK50395/6/7 MK50395/6/7 abstract |
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| Abstract: measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the , Image Sensor FTF5066C FTF5066C Pin configuration The FTF5066C FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 (quadrant W) is marked , A2 VPS VCS OUT VNS DOT ON TOP OF CCD INDICATES LOCATION OF PIN 1 Figure 12- Pin-configuration (top view) Figure 13 Pin configuration (top view) July 1, 2008 17 DALSA Professional ... | Original |
19 pages, |
Transistor TG p10 74151 pin configuration 74151 PIN DIAGRAM BAS28 BAT74 BC860C BFR92 .47k capacitor image ccd image sensor CCD Linear Image Sensor ccd sensor pin diagram image sensor sample hold FTF5066C FTF5066C FTF5066C abstract |
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| Abstract: integration (700 to 10,000 gates) • Various types of packages • 24-to 64-pin DIP • 20- to 84-pin PLCC • 24-to 160-pin FLAT • 72- to 208-pin PGA (including the plastic PGA) • Various types of functional , PINS AND STANDARD PIN LAYOUT FOR EACH PACKAGE Package Name of series (number of pad) Standard number of pins Standard pin {pin numb out 3r) Type No. of pins 70V 71V 72 V (74) 73V 74V (88) 79V , Name of series (number of pad) Standard number of pins Standard PINOUT (pin number) Type ... | OCR Scan |
23 pages, |
74381 alu synchronous counter using 4 flip flip MH 74150 74169 binary direction counter priority encoder 16 to 4 74148 alu 74381 74131 design a bcd counter using jk flip flop Toggle flip flop BCIC 74168 74169 SYNCHRONOUS 4-BIT BINARY COUNTER MSM70V000 MSM70V000 MSM70V000 abstract |
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| Abstract: to 10,000 gates) • Various types of packages • 24-to 64-pin DIP • 20-to 84-pin PLCC • 24- to 160-pin F LAT • 72- to 208-pin PGA (including the plastic PGA) • Various types of functional blocks (316 , average including the pin capacity of package and the pad capacity inside chip. 106 This Material , NUMBER OF POWER-SUPPLY PINS PIN LAYOUT FOR EACH PACKAGE AND STANDARD o: under development Package Name of series (number of pads) Standard number of pins Standard PINOUT (pin number) No. of pins ... | OCR Scan |
30 pages, |
74150 demultiplexer Multiplexer 74152 74259 ttl 74183 priority encoder 74147 design excess 3 counter using 74161 74169 binary counter 74151 adder 74138 logic circuit 74139 Dual 2 to 4 line decoder decoder 3-8 74ls with nor gate TTL 74139 MSM70H000 MSM70H000 MSM70H000 abstract |
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| Abstract: terminal clo - 10 - pF Note: The terminal capacity represents an average including the pin capacity of , of 90 to 10% CL = 20 pF 1.6 2.5 3.4 nS 161 â- STANDARD NUMBER OF POWER SUPPLY PINS AND STANDARD PIN , Standard PINOUT (pin number) Type No. of pins 70V 71V 72V (74) 73V 74V (88) 79V (94) 75V (112) 76V (138 , ) Standard number of pins Standard PINOUT (pin number) Type No. of pins 70V 71V 72 V (74) 73V 74V (88 , This series has the features to easily realize functions of the schmitt trigger, crystal/ ceramic or CR ... | OCR Scan |
23 pages, |
7449 DECODER 7495 4-bit latch 74139 for bcd to excess 3 code 74381 alu counter 74169 multiplexer 74151 7482 full adder priority encoder 74147 alu 74381 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74183 alu MH 74151 MSM70V000 MSM70V000 MSM70V000 abstract |
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| Abstract: negative edge of count input. PACKAGE DESCRIPTION 40-pin Dual In-Line Plastic â- r f/m" -J I-,» - , description: THE COUNTER The positive going edges of a pulse train at the COUNT input (pin 36) are , at the end of digit 4 thru digit 1 time and then bringing the store pin 15 low after the leading edge , occurs the sign flip-flop is set, and the level at pin 40 goes high, changing the mode of counting from , set into the counter by bringing the load counter pin 31 high from the leading edge of D1, thru D4. ... | OCR Scan |
22 pages, |
4013 FLIP FLOP APPLICATION DIAGRAMS FT 4013 D flip flop Decade Counter 7490 BCD to 7-Segment 7 segment display 6011 counter meter mk50395 Two Digit counter internal diagram of 7490 decade counter 7475 d-flip flop MK 50395 mh 7490 6-DIGIT DECADE COUNTER MK50395N MK50396N MK50395N abstract |
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| more details on the software configuration of the I/O ports. The RESET configuration of each pin is /W=read/write Notes : 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2 the dedicated ISPSEL pin. The Remote ISP is performed in three steps: - Selection of the RAM -down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6816.htm |
STMicroelectronics | 09/02/2001 | 287.83 Kb | HTM | 6816.htm |
| for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1 contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits V SS on the application board through a pull-down resistor. If any of these pins are used www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6816-v2.htm |
STMicroelectronics | 02/11/2000 | 275.91 Kb | HTM | 6816-v2.htm |
| = open drain, T = true open drain, PP = push-pull Note: the Reset configuration of each pin is shown in , else the configuration is floating interrupt input. 2. OSC1 and OSC2 pins connect a crystal or ceramic the dedicated ISPSEL pin. The Remote ISP is performed in three steps: - Selection of the RAM -down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to oscillator pins have to be tied to ground as shown in Figure 16. The selection of the internal RC www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6813-v1.htm |
STMicroelectronics | 20/10/2000 | 264.14 Kb | HTM | 6813-v1.htm |
| The XC4000 XC4000 XC4000 XC4000 and Spartan series architectures have a number of static RAM configurations defined as are listed in alphanumeric order under each category. There are a number of standard TTL 7400-type of the Â"Xilinx Unified LibrariesÂ" chapter for information on the specific device families that use functions in each of the architectural families (libraries) to minimize re-designing. Arithmetic Functions There are three types of arithmetic functions: accumulators (ACC), adders (ADD), and adder www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd04011.htm |
Xilinx | 16/02/1999 | 288.7 Kb | HTM | wcd04011.htm |
| !PADS-POWERPCB-V5.0-INCHES! DESIGN DATABASE ASCII FILE 1.0 *PCB* GENERAL PARAMETERS OF THE LAYERPAIR 1 4 Layer pair used to route connection VIAMODE A Type of via to Amount of time spent on this PCB design DOTGRID 0.05 0.05 Space between graphic dots SCALE 12.542 Scale of window expansion ORIGIN 28.61 28.385 User defined origin location WINDOWCENTER 28.80639 28.44011 Point defining the center of the window BACKUPTIME 5 Number of www.datasheetarchive.com/download/10999358-365330ZC/876a.zip (876A_Rev0.asc) |
Linear | 22/09/2009 | 741.38 Kb | ZIP | 876a.zip |
| | | Warnings such as non-montonic behavior at the noisy end | points of the slopes or . | |* [Disclaimer] Please be aware that in the absence of a written agreement | Texas Instruments(TI) assumes no liability for: | | (1) The accuracy of the IBIS models provided to your company | (2) The proper functioning of these Models in your design of these models. | | This information is for modeling purposes only www.datasheetarchive.com/download/49855882-921938ZC/sprm257a.zip (sprm257a.ibs) |
Texas Instruments | 07/08/2011 | 886.29 Kb | ZIP | sprm257a.zip |
| | | Warnings such as non-montonic behavior at the noisy end | points of the slopes or . | |* [Disclaimer] Please be aware that in the absence of a written agreement | Texas Instruments(TI) assumes no liability for: | | (1) The accuracy of the IBIS models provided to your company | (2) The proper functioning of these Models in your design of these models. | | This information is for modeling purposes only www.datasheetarchive.com/files/texas-instruments/simulation-models/sprm257a.ibs |
Texas Instruments | 07/08/2011 | 2886.85 Kb | IBS | sprm257a.ibs |
| software register configurations. Some pins are modeled as IO or tri-state for output mode. [Disclaimer] Please be aware that in the absence of a written agreement, Texas Instruments (TI) assumes no liability for: 1) the accuracy of the IBIS models 16 warnings can be waived Some pins may contain selectors which are not valid options for that particular pin. Please refer to the device datasheet www.datasheetarchive.com/download/99403166-922131ZC/sprm568.zip (sprm568.ibs) |
Texas Instruments | 23/05/2012 | 2805.82 Kb | ZIP | sprm568.zip |
| software register configurations. Some pins are modeled as IO or tri-state for output mode. [Disclaimer] Please be aware that in the absence of a written agreement, Texas Instruments (TI) assumes no liability for: 1) the accuracy of the IBIS models 16 warnings can be waived Some pins may contain selectors which are not valid options for that particular pin. Please refer to the device datasheet www.datasheetarchive.com/download/16484529-922130ZC/sprm567.zip (sprm567.ibs) |
Texas Instruments | 23/05/2012 | 2805.92 Kb | ZIP | sprm567.zip |