NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: :16x1 character dot matrix LCD display *Test Socket:One position for 28-pin IC socket *Operating Key , module + flat cable x 1 2-pin signal line hook x 1 40-pin IC socket x 1 DC power supply x 1 EXT , *28-pin IC socket x2 *System software disk x1 *User,s manual x1 *DC power adaptor x1 *3.3V adaptor x2 , IC socket X2 * DC adaptor * 16-bit 40-pin module + flat cable X1 * 4 signal line hook X1 , environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL ... | Original |
35 pages, |
pin out diagram of 74138 ic ic 7490 pin diagram ic 74148 ic 74148 block diagram TTL 74189 74688 comparators gould 4035 P89C238 ic 74139 ic 74247 pin diagram of ic 74190 IC 74189 PIN DIAGRAM pin configuration IC 74151 SU-2000 SU-2000 abstract |
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| Abstract: min. 59 sec. PIN CONNECTIONS Figure 1 SEGMENT OUTPUTS vss " SËT-LZB- fail d- (LSB) BCD OUTPUTS (MSB) STORE - (MSB) cD COUNTER C„ BCD c INPUTS CB (LSB) cA CLEAR- â-ºIC« " 2C â-º 3 C - 4 C - 5 , applications while the MK50397 MK50397 is best suited for stop watch or real-time computer clock applications. Pin , d FUNCTIONAL DESCRIPTION (Refer to Figure 2) Vss, Pin 1 Vss is the positive supply voltage. It should be maintained between 10 and 15 Vdc with respect to VDD. SET. Pin 2 SET is used to exercise ... | OCR Scan |
23 pages, |
MK 50395 12 hour digital clock using 7490 Application of Multiplexer IC 74151 internal diagram of 7490 IC SN7490 pin diagram of ic 74151 CI 74151 ic 7490 ic 7490 7 segment decade counter MULTIPLEXER IC SN74151 ic sn7490 pin diagram 7490 Decade Counter MK50395/6/7 MK50395/6/7 abstract |
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| Abstract: sec. PIN CONNECTIONS Figure 1 SEGMENT OUTPUTS vss " SËT-LZB- fail d- (LSB) BCD OUTPUTS (MSB) STORE - (MSB) cD COUNTER C„ BCD c INPUTS CB (LSB) cA CLEAR- â-ºIC« " 2C â-º 3 C - 4 C - 5[ -6[ " 7 C - 8 C - 9 C , stop watch or real-time computer clock applications. Pin connections are shown in Figure 1. V-15 BLOCK , SEGMENT IDENTIFICATION d FUNCTIONAL DESCRIPTION (Refer to Figure 2) Vss, Pin 1 Vss is the positive supply voltage. It should be maintained between 10 and 15 Vdc with respect to VDD. SET. Pin 2 SET is used to ... | OCR Scan |
23 pages, |
decode counter 7490 pin diagram of ic 74151 Application of Multiplexer IC 74151 BCD thumbwheel mk5009 7490 bcd 7 segment ttl pin diagram for IC cd 1619 p 7490 bcd counter CI 74151 ic sn7490 pin diagram ic 7490 pin diagram decade counter 7490 Decade Counter pin connections MK50395/6/7 MK50395/6/7 abstract |
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| Abstract: pin dual-in-line package. An Devices Yellow High Efficiency Red Green HDSP-2301 HDSP-2301 , 11 10 9 8 7 SEE NOTE 3 4.87 (0.192) REF. 1 2 1 2 3 3 PIN 1 , (0.197 ± 0.005) PIN 1 2 3 4 5 6 FUNCTION COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 COLUMN 5 INT. CONNECT* PIN 7 8 9 10 11 12 FUNCTION DATA OUT VB VCC CLOCK GROUND DATA IN *DO , Thermal Resistance IC Junction-to-Case RJÂC 25 °C/W/ Device 2 Data Out Voltage 2.4 ... | Original |
44 pages, |
e45e HDSP2312 DIODE MOTOROLA 2471 ci 74393 E408 74151 MUX 8-1 CI 74122 ne 555 timer 7490 divide by 6 HDSP-2010 HDSP-2451 motorola 6810 Multiplexer IC 74151 HDSP-2000 HDSP-2301 HDSP-2302 HDSP-2301 abstract |
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| Abstract: , MASSACHUSETTS 02062-9106 • 617/329-4700 Applications of the AD537 AD537 IC Voltage-to-Frequency Converter by Barrie , circuit is available in three performance grades in a 14-pin ceramic package or 10 pin hermetic metal can. , well-defined current limit. The SYNC input (pin 2) allows the oscillator to be slaved to a master clock if desired. It also permits control of the state of the output. These uses of the SYNC pin are dealt with in , most cases will be 2.5k£2. The +V|n terminal of the op-amp (pin 5) offers a high input resistance ... | OCR Scan |
18 pages, |
250M AD537 AD537K AN-277 Digital Weighing Scale schematic internal pin diagram of IC 74151 Lm324 comparator Multiplexer IC 74151 quadrature sinewave oscillator lm324 AN-277 abstract |
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| Abstract: , MASSACHUSETTS 02062-9106 • 617/329-4700 Applications of the AD537 AD537 IC Voltage-to-Frequency Converter by Barrie , circuit is available in three performance grades in a 14-pin ceramic package or 10 pin hermetic metal can. , well-defined current limit. The SYNC input (pin 2) allows the oscillator to be slaved to a master clock if desired. It also permits control of the state of the output. These uses of the SYNC pin are dealt with in , most cases will be 2.5k£2. The +V|n terminal of the op-amp (pin 5) offers a high input resistance ... | OCR Scan |
18 pages, |
AD562 AD537K AD537 pin configuration IC 74151 pin diagram of AD537 ad521 quadrature sinewave oscillator lm324 250M AN-277 Application of Multiplexer IC 74151 ic 74151 pin diagram of ic 74151 10CR AN-277 abstract |
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| Abstract: addresspin(i.e.,column1ofall4characters is tied to pin 1, etc.). In this way, any diode in the four 5 x 7 , the normal configuration of the HDSP-2000 HDSP-2000 displays, character 1 is the leftmost character, character , diagram shown in Figure 2. In those circuits, the display is mounted upside down, so that pin 1 is in the , the HDSP-2000 HDSP-2000 family displays. Depending upon overall systems configuration, microprocessor time , Label x is the 1 MHz clock. Label y is the output of 7404 pin 2 which is the inverted QD output of ... | Original |
36 pages, |
HDSP-2472 motorola 6810 astable multivibrator with 7404 ic 7490 pin diagram ic 74151 HDSP2000 HDSP-2000 HDSP-2300 CI 74LS00 IC 74122 astable by 74ls04 HDSP-2451 motorola 6820 pia HDSP-2000 abstract |
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| Abstract: performed automatically by the gate array design software). An example configuration for a 2-input NAND gate , requirements. Output drive may be increased from the basic 1mA to a maximum of 48mA per pin by means of parallel , block is 4.5 Kbits Access time 12 ns (typical) depending on configuration. For a triple port RAM the , Accesse time 9 ns (typ) depending on configuration. In order to access the feasability of integrating a , etc. This overhead is dependent upon the exact configuration of the memory in question. Tables 2a and ... | OCR Scan |
25 pages, |
internal diagram of 7490 IC ph 4531 diode ic 7490 pin diagram pin diagram of ic 7489 up down counter using IC 7476 decoder IC 74154 decoder IC 74154 pin diagram ic 74247 logic ic 7476 pin diagram pin diagram of ic 74190 Quad 2 input nand gate cd 4093 data sheet ic 74139 datasheet abstract |
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| Abstract: Ciò - 10 - PF Note: Terminal capacities are average values and include package pin capacities and , OSCILLATION CIRCUITS Configuration of oscillation circuits CMOS standardcell LSI External parts • OSC , PN! !a) ¿.J I (C) b-76 (11 b-69 Z2> (2) I IC) (Ni b-82 t. (c) (C) b-70 (IL , ENCODER 74148 11 8-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 74151 12 8-LINE TO 1-LINE , in the Comments column, the addition of a terminal for each bit of an internal flip-flop makes the IC ... | OCR Scan |
32 pages, |
binary to gray 74157 decoder IC 74154 7493 binary counter pin configuration IC 74151 ic 74192 pin configuration pin diagram of ic 74190 74283 IC decoder IC 74154 pin diagram IC 74154 Demultiplexer IC 74154 MSI IC 74138 decoder ic 74148 block diagram MSM91H000 MSM91H000 abstract |
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| Abstract: configuration â- Input: CMOS or TTL thresholds with or without pull-up; 7 pins also feature Schmitt thresholds , input, output, or bidirectional pad. Additional options are available for each I/O configuration , Quad Pin Number Gates Gates Count Count I/O Pads Carriers Flat Packs Grid Arrays 84 160 208 , mask-programmable gate arrays, many configuration options exist for each input/output (I/O) cell in the CP20K CP20K family. An example configuration of an I/O cell is shown in Figure 6. This cell is configured as an I/O ... | OCR Scan |
37 pages, |
7482 adder ic 74153 Multiplexer IC 74150 ic pin configuration 74153 4 bit comparator 7485 74151 adder 74152 mux 74151 mux ic 7485 4 bit comparator 74157 mux 16 bit comparator using 74*85 IC T flip flop IC MUX 74157 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| more details on the software configuration of the I/O ports. The RESET configuration of each pin is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.7.3ESD Pin Protection Strategy www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6816.htm |
STMicroelectronics | 09/02/2001 | 287.83 Kb | HTM | 6816.htm |
| pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.7.3ESD Pin Protection Strategy www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6816-v2.htm |
STMicroelectronics | 02/11/2000 | 275.91 Kb | HTM | 6816-v2.htm |
| = open drain, T = true open drain, PP = push-pull Note: the Reset configuration of each pin is shown in , else the configuration is floating interrupt input. 2. OSC1 and OSC2 pins connect a crystal or ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.9 CONTROL PIN CHARACTERISTICS www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6813-v1.htm |
STMicroelectronics | 20/10/2000 | 264.14 Kb | HTM | 6813-v1.htm |
| !PADS-POWERPCB-V5.0-INCHES! DESIGN DATABASE ASCII FILE 1.0 *PCB* GENERAL PARAMETERS OF THE PCB DESIGN UNITS 2 2=Inches 1=Metric 0=Mils USERGRID 0.005 0.005 Space between USER grid points MAXIMUMLAYER 4 Maximum routing layer WORKLEVEL 1 Level items will be created on DISPLAYLEVEL 1 toggle for displaying working level last LAYERPAIR 1 4 Layer pair used to route connection VIAMODE A www.datasheetarchive.com/download/10999358-365330ZC/876a.zip (876A_Rev0.asc) |
Linear | 22/09/2009 | 741.38 Kb | ZIP | 876a.zip |