NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Configuration Pin Function 1 14 2 13 3 12 4 11 Pin Symbol 1, 2 3, 9, 11 , specified. Parameters Supply voltage Pin 14 Supply current Pin 14 Power dissipation Junction , Control voltage Test Conditions / Pins Pin 14 FM-mode Pin 14 AM-mode Pin 8 Pin 12 Symbol VS , 1 kW 7 2 mA 93 7486 Figure 5. Pin 7 AGC time constant 10 Figure 6. Pin 8 , 7 14 +VS 13 1 12 IF Input sound carrier AF output (AM) 2 10 4 Standard switch ... | Original |
8 pages, |
IC 7481 pin configuration U2829B pin out diagram of 7486 IC pin configuration 14 pin 7486 U2829 pin diagram of 7486 pin diagram of ic 7483 pin diagram of 7486 IC ic 7483 pin configuration ic 7483 block diagram internal circuit of ic 7486 7483 ic pin diagram TDA4483 TDA4483 abstract |
|
|||
| Abstract: :* 3-pin locking: MCH fan (1) 4-pin ATX type : CPU power (1) 10-pin : Dual USB 2.0 (2) 14-pin shrouded , 184-pin latching DIMM sockets of unbuffered PC2700/333MHz and PC3200/400MHz DDR SDRAM (2.5V, ECC support , master/ slave configuration); PIO Mode 4, Bus Master IDE or synchronous DMA mode transfer up to 100MB/s , ) Keyboard / Mouse (6-pin female minidin) Headers 3-pin locking: CPU fan (1) 4-pin locking: POST Code (1) 7-pin vertical: Serial-ATA (2) 10-pin shrouded : Serial ports (2) 16-pin shrouded : Multifunction (1 ... | Original |
2 pages, |
VT100 82541ER 82547GI ati radeon mobility desktop mb cpu power section diode 24b f021 mobility radeon 9 MPGA478 SOCKET PC3200 prescott prescott 800 dual core cpu FSB 800 PRESCOTT 800 d2024 datasheet abstract |
|
|||
| Abstract: TEST pin. Normally, use at "L". 13 TEST3 I TEST pin. Normally, use at "H" or open. 14 , ) SDIP28-P-400-1 SDIP28-P-400-1.78: 2.2 g (typ.) Digital Filter (fs = 44.1 kHz) DA Converter · 2 kinds of package, 28-pin flat package and 28-pin DIP shrunk package. · It is possible to construct a system in simple , 2003-06-27 TC9237BF/BN TC9237BF/BN Pin Assignment (top view) Block Diagram 2 2003-06-27 TC9237BF/BN TC9237BF/BN Description of Pin Function Pin No. Symbol I/O Function&Operation Remarks 1 M/L I 2 ... | Original |
16 pages, |
TC9237BN TC9237BF TA2009P TA2009F pin DIAGRAM OF IC 7486 pin diagram of 7486 AFL89 IC 7486 pin diagram pin configuration 14 pin 7486 pin configuration of 7486 IC pin configuration OF IC 7486 IC 7486 internal structure function table IC 7486 TC9237BF/BN TC9237BF TC9237BF/BN abstract |
|
|||
| Abstract: 2/14 TOSHIBA TC9237BF/BN TC9237BF/BN DESCRIPTION OF PIN FUNCTIONS PIN No. SYMBOL I/O FUNCTION & OPERATION , . Normally, use at "I' 13 TEST3 TEST pin. Normally, use at "H" or open. With a pull-up resistor 14 GNDD , clock input pin. 28 VßEL Logic power supply pin. 2000-02-25 3/14 TOSHIBA TC9237BF/BN TC9237BF/BN DESCRIPTION , capacitor between Vqa and GNDA shall be connected as close to the pin as possible. 2000-02-25 11/14 , 96fs - 87dB (Typ.) 98dB (Typ.) • 2 Kinds of package, 28-pin flat package and 28-pin DIP shrunk ... | OCR Scan |
13 pages, |
TC9237BN TC9237BF TC9237 TA2009P TA2009F IC 7486 pin diagram TC9236AF AFL89 TC9237BF/BN TC9237BF/BN abstract |
|
|||
| Abstract: "L". 13 TEST3 I TEST pin. Normally, use at "H" or open. With a pull-up resistor 14 , 96fs - 87dB (Typ.) 98dB (Typ.) • 2 Kinds of package, 28-pin flat package and 28-pin DIP shrunk , ) dedicated to +5V single power supply operation. 1 2001-06-19 TOSHIBA TC9237BF/BN TC9237BF/BN PIN CONNECTION m/l , DESCRIPTION OF PIN FUNCTIONS PIN No. SYMBOL I/O FUNCTION & OPERATION REMARKS 1 M/L I Input data MSB First/LSB First selection pin. MSB First at "H" and LSB First at "L" With a pull-up resistor 2 ... | OCR Scan |
15 pages, |
IC 7486 pin diagram TA2009F TA2009P TC9236 TC9237BF TC9237BN TOShiba clock generator toshiba interpolation function table IC 7486 AFL89 VDAi TC9236AF TC9237BF/BN TC9237BF/BN abstract |
|
|||
| Abstract: TA = 30°C SSB NOISE FIGURE (dB) G, GAIN (dB) 18 17 25°C 16 15 85°C 14 Pin = , GND Pin Connections and Functional Block Diagram REV 2 ©MOTOROLA RF DEVICE DATA Motorola , 5.0 Vdc) 800 mA Power Output (Pin = 11 dBm) 5 4 6 3 7 2 T1 , Material 30 MIL FR4 Connectors SMA Type Figure 1. Applications Circuit Configuration MRFIC2404 MRFIC2404 , 0.441 50.42 5.733 105.10 0.043 107.18 0.620 74.86 2900 0.439 53.14 ... | Original |
6 pages, |
MRFIC2404R2 MRFIC2404 MRFIC2403 gaas amplifier 7486 611 motorola pin diagram of 7486 m2404 MRFIC2404/D MRFIC2404/D abstract |
|
|||
| Abstract: 25°C 16 15 85°C 14 Pin = 20 dBm VDD = 5.0 Vdc Vbias = 0 Vdc 13 12 2.0 2.1 2.2 , 1 2 3 4 GND VDD RF OUT GND Pin Connections and Functional Block Diagram , mA SLEEP Mode Supply Current (Vbias = 5.0 Vdc) 800 mA Power Output (Pin = 11 , Applications Circuit Configuration MRFIC2404 MRFIC2404 2 MOTOROLA RF DEVICE DATA Table 1. Scattering , 74.86 2900 0.439 53.14 5.565 116.69 0.041 98.95 0.617 77.74 2950 ... | Original |
6 pages, |
pin diagram of 7486 MRFIC2404 MRFIC2403 M2404 MRFIC2404/D MRFIC2404/D abstract |
|
|||
| Abstract: |S21| S12 Typical Characteristics 19 5.0 4.8 17 25°C 16 15 85°C 14 Pin = 20 , GND Pin Connections and Functional Block Diagram REV 3 ©MOTOROLA RF DEVICE DATA Motorola , Power Output (Pin = 11 dBm) 5 4 6 3 7 2 T1 RF IN VBIAS RF OUT VDD C1 8 , Type W Figure 1. Applications Circuit Configuration MRFIC2404 MRFIC2404 2 MOTOROLA RF DEVICE DATA , 0.620 74.86 2900 0.439 53.14 5.565 116.69 0.041 98.95 0.617 77.74 ... | Original |
6 pages, |
pin diagram of 7486 MRFIC2404R2 MRFIC2404 MRFIC2403 M2404 611 motorola MRFIC2404/D MRFIC2404/D abstract |
|
|||
| Abstract: TA = 30°C SSB NOISE FIGURE (dB) G, GAIN (dB) 18 17 25°C 16 15 85°C 14 Pin = , GND Pin Connections and Functional Block Diagram REV 3 ©MOTOROLA RF DEVICE DATA Motorola , 5.0 Vdc) 800 mA Power Output (Pin = 11 dBm) 5 4 6 3 7 2 T1 , Material 30 MIL FR4 Connectors SMA Type Figure 1. Applications Circuit Configuration MRFIC2404 MRFIC2404 , 0.441 50.42 5.733 105.10 0.043 107.18 0.620 74.86 2900 0.439 53.14 ... | Original |
6 pages, |
pin diagram of 7486 MRFIC2404R2 MRFIC2404 MRFIC2403 M2404 611 motorola MRFIC2404/D MRFIC2404/D abstract |
|
|||
| Abstract: CAPACITOR NC FOUTPUT COMPARATOR INPUT VS 8 Figure 2. D-14, N-14 Pin Configurations 18 +VS , VOUT 14 OFFSET NULL +IN 2 +IN VOUT 1 NC OFFSET NULL OFFSET NULL PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. P-20A P-20A Pin Configuration Table 2. Pin Function Descriptions D-14, N-14 1 Pin No. P-20A P-20A 2 Mnemonic VOUT 2 3 4 3 4 6 5 6 8 9 7 , preventing Pin 1 from swinging below Pin 2. Figure 18. PSRR vs. Full-Scale Frequency Rev. D | Page 14 ... | Original |
20 pages, |
ad650jn AD650BD AD650 AD650JNZ AD650JP AD650KN AD650SD cmos nand gate open collector 7486 XOR GATE 7486 ci AD650AD 7474 dual d flip flop 7474 14 PIN FUNCTIONAL DIAGRAM OF 7400 AD650 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| ), taking care to align the device adapter's female pin 1 connector with the male pin 1 on Figure 14: SDIP Document Format Size Document Number Date Update Pages Portable Document Format 1M 7486 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Emulator Configuration . 7 1.3 Software and Documentation for the Emulator Kit . 8 1.4 this way, it is possible to fully emulate microcontroller resources. 1.1 Emulator Configuration www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7486.htm |
STMicroelectronics | 22/02/2001 | 90.95 Kb | HTM | 7486.htm |
| configuration register The TouCAN ignores its RX pins and drives its TX pins as recessive The TouCAN loses _x) TCNMCR - TouCAN Module Configuration Register 0x30 7080 0x30 7480 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 buffers zero through 13), special for message buffer 14, and special for message buffer 15 Programmable architecture 16.2 External Pins The TouCAN module interface to the CAN bus consists of four pins: CANTX0 and -15] ID_HIGH $4 ID[14-0] RTR ID_LOW $6 DATA BYTE 0 DATA BYTE 1 $8 DATA BYTE 2 DATA BYTE 3 $A DATA BYTE 4 www.datasheetarchive.com/download/23307443-484153ZC/mpc555um.zip (c16touc.pdf) |
Motorola | 16/02/2000 | 5718.84 Kb | ZIP | mpc555um.zip |
| email: scansupport@intellitech.com - - This BSDL file reflects the pre-configuration JTAG behavior. To reflect - the post-configuration JTAG behavior (if any), edit this file as described - below. Many of regarding keeping INIT low. - - NOTE: Post-configuration JTAG is available only if the BSCAN symbol pins - in the FPGA design to comply with IEEE Std. 1149.1-1993. entity XC5202 XC5202 XC5202 XC5202_TQ144 TQ144 TQ144 TQ144 is generic (PHYSICAL_PIN_MAP : string := "TQ144 TQ144 TQ144 TQ144" ); port ( CCLK: linkage bit; DONE: linkage bit; GND: linkage bit www.datasheetarchive.com/download/81237942-987374ZC/wcd03014.zip (xc5202_tq144.bsd) |
Xilinx | 12/02/1999 | 31.82 Kb | ZIP | wcd03014.zip |
| email: scansupport@intellitech.com - - This BSDL file reflects the pre-configuration JTAG behavior. To reflect - the post-configuration JTAG behavior (if any), edit this file as described - below. Many of regarding keeping INIT low. - - NOTE: Post-configuration JTAG is available only if the BSCAN symbol pins - in the FPGA design to comply with IEEE Std. 1149.1-1993. entity XC5202 XC5202 XC5202 XC5202_TQ144 TQ144 TQ144 TQ144 is generic (PHYSICAL_PIN_MAP : string := "TQ144 TQ144 TQ144 TQ144" ); port ( CCLK: linkage bit; DONE: linkage bit; GND: linkage bit www.datasheetarchive.com/download/38283265-987025ZC/wcd02e01.z |
Xilinx | 13/07/1998 | 33.76 Kb | Z | wcd02e01.z |
| email: scansupport@intellitech.com - - This BSDL file reflects the pre-configuration JTAG behavior. To reflect - the post-configuration JTAG behavior (if any), edit this file as described - below. Many of regarding keeping INIT low. - - NOTE: Post-configuration JTAG is available only if the BSCAN symbol pins - in the FPGA design to comply with IEEE Std. 1149.1-1993. entity XC5202 XC5202 XC5202 XC5202_TQ144 TQ144 TQ144 TQ144 is generic (PHYSICAL_PIN_MAP : string := "TQ144 TQ144 TQ144 TQ144" ); port ( CCLK: linkage bit; DONE: linkage bit; GND: linkage bit www.datasheetarchive.com/download/541384-987026ZC/wcd02e02.zip (xc5202_tq144.bsd) |
Xilinx | 13/07/1998 | 31.82 Kb | ZIP | wcd02e02.zip |
| 1999 A-1 Table A-14 SRAM (Static RAM Access Memory) Array MPC555 MPC555 MPC555 MPC555 MPC555 MPC555 MPC555 MPC555 INTERNAL MEMORY MAP MOTOROLA (Write Only). See Table 3-14 for bit descriptions. 64 U SPR 287 S read only PVR Processor Version -10 for bit descriptions. 32 POR, H SPR 560 S BBCMCR BBC Module Configuration Register.See Table 4-8 for bit descriptions. 32 U SPR 568 U L2U_MCR L2U Module Configuration Register.See Table 11-7 for bit Unit) Address Access Symbol Register Size Reset 0x2F C000 U1 SIUMCR SIU Module Configuration Register www.datasheetarchive.com/download/23307443-484153ZC/mpc555um.zip (appa.pdf) |
Motorola | 16/02/2000 | 5718.84 Kb | ZIP | mpc555um.zip |
| . Figure 3. ST62T32B ST62T32B ST62T32B ST62T32B Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 62T32B/E32B 62T32B/E32B 62T32B/E32B 62T32B/E32B Pin Configuration These compact low-cost devices feature a Timer comprising an 8-bit , EEPROM, SPI, UART & 52, 42 PINS Datasheet , SPI, UART & 52, 42 PINS ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST /O pins, fully programmable as: - Input with pull-up resistor - Input without pull-up resistor www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4990-v3.htm |
STMicroelectronics | 25/05/2000 | 189.24 Kb | HTM | 4990-v3.htm |
| applications. Figure 3. ST62T32B ST62T32B ST62T32B ST62T32B Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 . Figure 2. ST62T32B/E32B ST62T32B/E32B ST62T32B/E32B ST62T32B/E32B Pin Configuration These compact low-cost devices feature a Timer comprising an , EEPROM, SPI, UART & 52, 42 PINS Datasheet 8-BIT PINS ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST6232B ST6232B ST6232B ST6232B ST62E32BF1 ST62E32BF1 ST62E32BF1 ST62E32BF1 ST62P32 ST62P32 ST62P32 ST62P32 Data RAM: 192 bytes n Data EEPROM: 128 bytes n User Programmable Options n 30 I/O pins, fully www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4990-v1.htm |
STMicroelectronics | 20/10/2000 | 196.53 Kb | HTM | 4990-v1.htm |
| . Figure 3. ST62T32B ST62T32B ST62T32B ST62T32B Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 62T32B/E32B 62T32B/E32B 62T32B/E32B 62T32B/E32B Pin Configuration These compact low-cost devices feature a Timer comprising an 8-bit , EEPROM, SPI, UART & 52, 42 PINS Datasheet , SPI, UART & 52, 42 PINS ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB1 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB3 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BB6 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ1 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ3 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST6232BQ6 ST /O pins, fully programmable as: - Input with pull-up resistor - Input without pull-up resistor www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4990-v2.htm |
STMicroelectronics | 11/01/2000 | 189.29 Kb | HTM | 4990-v2.htm |
| . Figure 3. ST62T32B ST62T32B ST62T32B ST62T32B Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PA0 PA1 PA2 . Figure 2. ST62T32B/E32B ST62T32B/E32B ST62T32B/E32B ST62T32B/E32B Pin Configuration These compact low-cost devices feature a Timer comprising an 8 32B ST62E32B ST62E32B ST62E32B ST62E32B 1.4 PROGRAMMING MODES 1.4.1 Option Byte The Option Byte allows configuration capability , EEPROM, SPI, UART & 52, 42 PINS ST6232B ST6232B ST6232B ST6232B 8-BIT MICROCONTROLLER ( MCU ) WITH OTP, ROM, FASTROM, EPROM, ADC, 16-BIT 16-BIT 16-BIT 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI, UART & 52, 42 PINS Document Number: 4990 Date www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4990.htm |
STMicroelectronics | 02/04/1999 | 186.97 Kb | HTM | 4990.htm |