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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
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pin diagram priority decoder 74138

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intel 8289

Abstract: pin diagram priority decoder 74138 - sysb/RE5B \ system â'¢ sen / signals Figure 2. Pin Diagram Figure 3. Functional Pinout 7-110 à , priority BREQ line which is active. The binary address is decoded by a decoder to select the corresponding , settle. cbrs bus arbiter bus arbiter 2 bus arbiter bus arbiter 741« 74138 priority â'"^ 3 to 8 encoder decoder Figure 4. Parallel Priority Resolving Technique rcre bhes m higher , System Bus Arbitration for 8089 IOP in Remote Mode The Intel 8289 Bus Arbiter is a 20-pin, 5
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74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 74138 74139 Logic Function BCD-to-Decimal Decoder 4-Bit Magnitude Comparator 8-Bit Shift Register Divide-by-twelve Counter 4-Bit Binary Counter 4-Bit Shift Register 4-Bit Shift Register 3-Line to 8-Line Decoder / Demultiplexer 2-line to 4-line Decoder/Demultiplexer 8-line to 3-line Priority Encoder 8-line to 1-line Data , /Multiplexer Dual 2-line to 4-line Decoder/Demultiplexer Macro Block Name (0042) (0085) (0091) (0092) (0093 , individual resources. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
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74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 7 7495 4-Bit Shift Register (0095) 28 8 74138 3-Line to 8-Line Decoder / Demultiplexer (0138) 14 g 74139 2-line to 4-line Decoder/Demultiplexer (0139) 7 10 74148 8-line to 3-line Priority Encoder , BLOCK LIST No. Logic Function Macro Block Name No. of Cells Comment 1 7442 BCD-to-Decimal Decoder , ) 13 14 74155 Dual 2-line to 4-line Decoder /Demultiplexer (0155) 12 tionat blocks and the macro , 's BINALY Logic Simulation. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
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IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 > 4-BIT SHIFT REGISTER 7495 * 8 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER 74138 9 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER 1/2 74139 10 8-LINE TO 3-LINE PRIORITY ENCODER 74148 11 , Note: Terminal capacities are average values and include package pin capacities and chip internal pad , DECODER 7442 2 4-BIT MAGNITUDE COMPARATOR 7485 1 3 8-BIT SHIFT REGISTER 7491 * 4 , -BIT BINARY COUNTER 1/2 74393 39 EXCESS-3 TO DECIMAL DECODER 7443 40 EXCESS-3 GRAY TO
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F9444

Abstract: power control F9444 devices, handle 16 levels of priority interrupt, and perform fast direct memory access. It has control , to 24 MHz â'¢ LS TTL Input/Output Structure with l3L Internal Circuits â'¢ 40-Pin DIP Needing a , Technology â'¢ Comprehensive Family of Support Circuits Pin Functions MULTIPROCESSOR I SIGNALS ] EXTERNAL , Ambient Temperature Under Bias -55 to + 125°C Vcc Pin Potential to Ground Pin -0.5 to +6.0 V Input , Diagram INFORMATION BUS DATA PATHS CONTROL LINES Architecture The F9445 microprocessor comprises three
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F9444 F9447 F9448 power control F9444 IC 3-8 decoder 74138 pin diagram 3-8 decoder 74138 pin diagram pin diagram priority decoder 74138 MC 74138 F9446 F9449 F9470

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram 21. 32 to 5 Priority Encoder Block Diagram Philips Semiconductors Programmable Logic Devices , is depicted in Figure 1 wherein a simple three to eight decoder is fused into the array. The , generated at the input receivers. Hence, this diagram could be trimmed by six gates, down to eight to , whose inputs span the complete NAND gate foldback structure. 1 OF 8 DECODER/DEMULITPLEXER 8 , ); 8 EN Figure 1. Decoder Implementation in NAND Foldback Structure October 1993 27
Philips Semiconductors
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full 18*16 barrel shifter design full adder using ic 74138 TTL SN 7404 pn sequence generator using d flip flop 12 bit comparator images of pin configuration of IC 74138 PLHS501 AN049

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 LATCHES 1 O F 8 DECODER/M ULTIPLEXER 10 TO 4 LINE ENCODER 8 TO 3 LINE PRIORITY ENCODER 16 BIT DATA SELECTO , . 4. These inputs can be re-routed to any other I/O PAD. TMODE pin at logic HIGH enables the test mode func tion and then CKTEST pin configures it. CKTEST can also be used as a conventional input signal and , an exam ple the diagram of a DFFNR1, Macro cell (D Flip-Flop with Reset) as it appears to the routing , give n in M HS user's manual. r O PIN vi"! r o p in v p p ] K > H H > °-i I (PMOS
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circuit diagram for IC 7483 full adder ttl ic 7485 0850R 7483 4 bit binary full adder circuit diagram for 7483 transistor KD 617 ic 7442 encoder 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT

IC 3-8 decoder 74138 pin diagram

Abstract: F9444 62 I/O devices, handle 16 levels of priority interrupt, and perform fast direct memory access. It has , 24 MHz â'¢ LS TTL Input/Output Structure with l3L Internal Circuits â'¢ 40-Pin DIP Needing a Single , Pin Functions MULTIPROCESSOR SIGNALS EXTERNAL REQUESTS bus i CONTROL) CLK _F9445 MR 16 , -65to+150°C Ambient Temperature Under Bias -55 to + 125°C Vcc Pin Potential to Ground Pin -0.5 to +6.0 V , |JU1-nunvc cvciy ojoic, may be used for external synchronization of memory and I/O control. STRBD, Pin 6 â
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MSI IC 74138 decoder F9445 self-test 74138 FAIRCHILD 74ls240 bus transfer switch Fairchild 9445 F9445-16DM M38510 F9445-24 F9445-20 F9445-16

p54c

Abstract: SiS 85C503 shows the system block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC , Address Data Figure 1.1 System Block Diagram Preliminary V2.0 January 9, 1995 1 Silicon , Supports Rotating Priority Mechanism - Hidden Arbitration Scheme Minimizes Arbitration Overhead · , Snoop Frequency · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 January 9, 1995 , Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M
Silicon Integrated Systems
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p54c SiS 85C503 85c501 3-8 decoder 74138 85c503 9ROM 85C501/502/503 S85C501 S85C502 S85C503 85C502

74194 ring counter

Abstract: grid tie inverter schematic diagram support schematic capture and simulation on popular CAE workstations. BLOCK DIAGRAM /OD OO OO DQQ I/O , Industrial (-40°C to +85°C) c. PACKAGE TYPE J - Plastic Leaded Chip Carrier G = Pin Grid Array - b , 68-pin PLCC 68-pln PGA 84-pin PLCC 84-Dln PGA 175-pin PGA 3020 X X X X 3030 X X 3042 X X , FINISH C = Gold d. PACKAGE TYPE Z = 84-pin PGA (Am3020) Z = 84-pin PGA (Am3030) Z = 132-pin PGA (Am3042)* Z = 132-pin PGA (Am3064)* Z = 175-pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED
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74194 ring counter grid tie inverter schematic diagram 74299 universal shift register CI 74241 DN 74352 grid tie inverter schematics

AMD K6

Abstract: 74147 decimal to binary encoder easily BLOCK DIAGRAM g /E x u j u u u u u E I/O Blocks / + , Plastic Leaded Chip Carrier G = Pin Grid Array b. SPEED OPTION -50 (50 MHz toggle rate) -70 (70 MHz , TYPE Z = 84-pin PGA (Am3020) Z = 84-pin PGA (Am3030) Z = 132-pin PGA (Am3042)* Z = 132-pin PGA (Am3064)* Z = 175-pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED/POWER OPTION -50 = 50 MHz , interface between the deviceâ'™s external package pin and the internal user logic. Each IOB includes both
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AMD K6 74147 decimal to binary encoder C10BCPRD C10BCRD C10BPRD C10JCR C12JCR C16BARD

IC 3-8 decoder 74138 pin diagram

Abstract: f9444 vices, handle 16 levels of priority interrupt, and perform fast direct memory access. It has control , with Single Clock up to 24 MHz LS TTL Input/Output Structure with l3L Internal Circuits 40-Pin DIP , Technology Comprehensive Family of Support Circuits Pin Functions CLK fOi M ULTIPROCESSOR I , perature Am bient Tem perature Under Bias Vcc Pin Potential to Ground Pin Input Voltage (dc) Input Current , . Timing and Status SYN, Pin 7 - Synchronize O utput - Active every cycle; may be used fo r external
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74874 74164 counter pin diagram of ic 74164 74164 with ic PIN DIAGRAM decoder 74138 have three enabled pin F9444 power control

d6406

Abstract: laser sharp measurement Decoder/Driver. Hex Bus , Chip Select Decoder (PC SD â"¢ ). Programmable Chip Select Decoder (P C S D ). Programmable Chip Select Decoder (P C S D ). Programmable Chip Select Decoder (P C S D ). Programmable Logic (16-Pin). Static 16
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d6406 laser sharp measurement Transistor AF 138 pin diagram AMD FX 9590 80C86/88 AA22846 J22912 K29793 NZ21084 RS39191

intel 8288

Abstract: intel 8288 bus controller -2 Figures S-1 8087 Numeric Data Processor Pin Diagram . S-2 S-2 8087 Evolution and , Block Diagram . S-8 8-5 Register Structure . S-9 S-6 Status Word Format , Figure 4. Numeric Data Processor Block Diagram cendental (trigonometric) functions, processes decimal , PROGRAM PROGRAM CHANNEL 2 PROGRAM DATA Figure 5. I/O Processor Block Diagram 1-5 , are contained in standard 40-pin dual in-line packages (figure 2-1) and operate from a single +5V
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intel 8288 intel 8288 bus controller 8085 MICROCOMPUTER SYSTEMS USERS MANUAL 8086 interrupt structure design fire alarm 8088 microprocessor RCA SK CROSS-REFERENCE SA/C-258

smi 5502

Abstract: T54B block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC DRAM 244 , * * * 245 ISA BUS Address Data Figure 1.1 System Block Diagram Preliminary V2.0 April 2, 1995 , Priority Mechanism - Hidden Arbitration Scheme Minimizes Arbitration Overhead · Integrated PCI Bridge - , Buffer Strength · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 April 2, 1995 , Functional Block Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA
Silicon Integrated Systems
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smi 5502 T54B SiS5501 ha 501 73 5503 74138 S5501 S5502 S5503

SIS5513

Abstract: SiS5511 implement a low cost, high performance, Pentium PCI/ISA system. Figure 1.1 shows the system block diagram , * * * Address Data ISA BUS Figure 1.1 System Block Diagram Preliminary V1.2 June 14, 1995 1 , Provides High Performance PCI Arbiter. - Supports 4 PCI Master. - Supports Rotating Priority Mechanism , Bursting. - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes. · 208-Pin PQFP. · 0.6µm CMOS , /ISA Cache Memory Controller 2.2 Functional Block Diagram HA[31:3] BOFF# HBE[7:0]# ADS# M/IO
Silicon Integrated Systems
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LVT573 SIS5513 SiS5511 T40 N sis 5511 pin configuration of IC 74138 8kx1 RAM S5511 S5512 S5513 66/60/50MH

LEAPER-3

Abstract: 74189 by using the PCFACE-III slot pin diagram. 8. No hard state limited for interface experiment , in a wide variety of modules has dominated the priority in Leap for a long time. To meet the demands , for 24,28,32 pin DIP EPROM, 8 socket module support for SEEPROM in 20-pin DIP EEPROM and FLASH SEEPORM-248D(SOP) FLASH-328P 8 socket module support for 32-pin PLCC over 1M bits EPROM, EEPROM and FLASH FLASH-328PA 8 socket module support for 32-pin PLCC under 1M bits EPROM, EEPROM and FLASH
Leap Electronic
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LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration SU-2000 PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622

Intel 8008

Abstract: design fire alarm 8088 microprocessor onsiderations, 72 2.5.1 Board-to-Board Relations, 72 2.5.2 Pin Assignments, 73 2.5.3 Connector-Naming and , Bus Pin Assignments, 119 Bus Termination, 120 Variable Elements of Capability, 120 Compliance-Level , Layout C onsiderations, 153 M e ch a n ica l C onsiderations, 155 4.7.1 iSBX Connector, 155 4.7.2 Pin , . (Figure 1-4 is a block diagram of an SBC, and Fig. 1-5 shows the implementation.) A typical SBC in the , TTTTT M U LTIB U S SYSTEM BUS FIG U R E 1-4 Block diagram of a single-board computer
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Intel 8008 STR IC intel 8218 76381 parallel bus arbitration RADIO SHACK PARTS CROSS REF

CB4CLE

Abstract: cb4re . D2_4E 2- to 4-Line Decoder/Demultiplexer with Enable . D3_8E 3- to 8-Line Decoder/Demultiplexer with Enable . D4_16E 4- to 16-Line Decoder/Demultiplexer with , Gates with Non-Inverted Inputs . X74_42 4- to 10-Line BCD-to-Decimal Decoder with , -Bit Expandable Magnitude Comparator. X74_138 3- to 8-Line Decoder/Demultiplexer , _139 2- to 4-Line Decoder/Demultiplexer with Active-Low Outputs and Active-Low Enable
Xilinx
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CB4CLE cb4re CB8CLED cb8cle CB4CLED X74-160

f9454

Abstract: F9445 perations A p p lica tio n s In stru ctio n Execution Times Tim ing Diagram s and S p e cifica tio n s O rdering Inform ation Page 1 2 2 4 5 15 19 30 31 36 Pin Functions C LK _ F 9445 HR 16-B IT M IC R O P , Under Bias Vcc Pin Potential to Ground Pin Input Voltage (dc) Input Current (dc) ' O utput Voltage , valid with STRBD strobe; 3-state d u rin g data-channel and non-bus cycles. T im ing and Status SYN, Pin , ory and I/O control. STRBD, Pin 6 - Data Strobe - Active LOW o utput; active only d u ring memory, I
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f9454 74l93 9347S F9454
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