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SN74LS00N-00 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN74LS00DBR Texas Instruments Quad 2-input positive-NAND gates 14-SSOP 0 to 70 visit Texas Instruments Buy
SN74LS00NE4 Texas Instruments Quad 2-input positive-NAND gates 14-PDIP 0 to 70 visit Texas Instruments
SN74LS00DBRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SSOP-14 visit Texas Instruments
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70 visit Texas Instruments Buy
SN74LS00J-00 Texas Instruments IC LS SERIES, QUAD 2-INPUT NAND GATE, CDIP14, Gate visit Texas Instruments

pin diagram of 74ls00

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of 74ls00

Abstract: 74LS00 Diagram All the state transitions take place at rising edge of the system clock. The state machine can , DTACK Generator is a state machine. It delays the memory or I/O access cycle of the PC Card when the card asserts the *WAIT signal. The state diagram is shown in Figure 0-1 *CSD3=1 S0 00 *CSD3 , B B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2
Motorola
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74HC04 74HC240 74HC74 pin diagram of 74ls00 74ls00 datasheet motorola 74LS00 74HC74 decoder inverter wait HE95002

pin diagram of 74ls00

Abstract: 74HC04 Generator State Diagram All the state transitions take place at rising edge of the system clock. The , Semiconductor, Inc. The DTACK Generator is a state machine. It delays the memory or I/O access cycle of the PC Card when the card asserts the *WAIT signal. The state diagram is shown in Figure 0-1 *CSD3 , FOR DRAGONBALL For More Information On This Product, Go to: www.freescale.com 1 Because of an , 74HC04 U2A 2 B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0
Freescale Semiconductor
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MC68EZ328 74ls00 circuit diagram 74LS00 impedance 74LS00 application PAL22V10

datasheet of ic 74ls00

Abstract: pin diagram of ic 74ls00 machine. It delays the memory or I/O access cycle of the PC Card when the card asserts the *WAIT signal. The state diagram is shown in Figure 0-1 *CSD3=1 S0 00 *CSD3=0 *CSD3=1 *CSD3=0 S1 S3 10 01 S2 11 *WAIT=0 Figure 0-1. DTACK Generator State Diagram All the state transitions take place at rising edge of the system clock. The state machine can be implemented by following , Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00
Freescale Semiconductor
Original
datasheet of ic 74ls00 pin diagram of ic 74ls00 74HC74 application 74HC74 datasheet 74LS00 integrated circuit datasheet of 74HC74 ic

74LS00

Abstract: motorola 74LS00 machine. It delays the memory or I/O access cycle of the PC Card when the card asserts the *WAIT signal. The state diagram is shown in Figure 0-1 *CSD3=1 S0 00 *CSD3=0 *CSD3=1 *CSD3=0 S1 S3 10 01 S2 11 *WAIT=0 Figure 0-1. DTACK Generator State Diagram All the state transitions take place at rising edge of the system clock. The state machine can be implemented by following , Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00
Freescale Semiconductor
Original
IC 74hc74

74LS00 CMOS

Abstract: 74LS00 gate diagram '¢ Features - â'¢ The LC74HC00M consists of 4 identical 2-input NAND gates. â'¢ Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL (74LS00) with the low power dissipation and high noise margin of standard CMOS ICs. â'¢ Has buffered outputs, improving the output transition , 'OUT Per output ±25 mA Current Dissipation 'CC/'Gnd ±50 mA Clamp Diode Current 'K Per input pin  , °C ns Equivalent Circuit and Logic Diagram (1/4 LC74HC00M) I vcc A1-A4 . -t n,t,.9,aplnl 11â'"i i
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LC74HC00WB 74LS00 CMOS 74LS00 gate diagram 74LS00 circuit diagram with voltage ttl 74ls00 series 74LS00 pinout CMOS 74LS00 LC74HC 54LS/74LS LC74HC00 5306KI/4106KI

schematic diagram brushless motor control

Abstract: schematic diagram Permanent Magnet brushless DC m to note some HW connections in the schematic. Bit "0" (pin 9) of the parallel port is used to enable , ac peripheral to run. At this time it is already possible to see a PWM wave on pin 24 of ST52x301 , . Di Guardo INTRODUCTION Brushless DC motors (BLDC) are becoming widely used in the field of control motors. These kind of synchronous motors are used as servo drives in applications such as computer , frequency corresponding instantaneously to the rotor speed. One of the advantages of BLDC motor is the
STMicroelectronics
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schematic diagram brushless motor control schematic diagram Permanent Magnet brushless DC m ST52X301 permanent magnet synchronous machine schematic diagram Permanent Magnet brushless DC jps inverter AN1113

TTL 74HC00

Abstract: 74LS00 TTL '¢ High noise immunity characteristic of CMOS â'¢ Diode protection on all inputs Pin Configuration 1A [T , in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are , . Features â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL , Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L H-HIGH voltage level L-LOW voltage level Fig. 1 Logic Symbol Fig. 2 Logic diagram (one gate) ~ ~ ~ ' ~ 3-3 â
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TTL 74HC00 74LS00 TTL 74hc00 and gates 74HC00 TTL 74ls00 5V 74HC00 GD54/74HC00 GD54/74HCT00 54/74LS00 000M5L7 00Q42

74LS00 pinout

Abstract: 74hc00 and gates '¢ High noise immunity characteristic of CMOS â'¢ Diode protection on all inputs Pin Configuration 1A , identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are , â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL , Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L H-HIGH voltage level L-LOW voltaae level Fig. 1 Logic Symbol Fig. 2 Logic diagram (one gate) 3-3 GD54
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GD74HC00 GD54HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC GD74HCT00 GD54HCT00

pin diagram of ic 74ls00

Abstract: M74HC00 A B L L H L H H H L L H H H PIN CONFIGURATION (TOP VIEW) Outline 14P4 14P2P LOGIC DIAGRAM , DESCRIPTION The M74HC00 ts a semiconductor integrated circuit consisting of four 2-input positive-logic NAND , dissipation: 5,uW/package (max) (VCc=5V, Ta=25'C, quiescent state) â'¢ High noise margin: 30% of Vcc, min (VCC=4.5V, 6V) â'¢ Capable of driving 10 LSTTL loads â'¢ Wide operating voltage range: VCc=2~6V â , industrial and consumer digital equipment. FUNCTIONAL DESCRIPTION Use of silicon gate technology allows the
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M74HC00P M74HC00DP 4000B 74LS00 transfer function 74LS00 pin configuration M74HCOO 74LS00 function table pin configuration 74LS00

74LS00 integrated circuit

Abstract: Package) C1R (Chip Carrier) tPLH = tPHL â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 â , ­ formance of LSTTL combined with true CMOS low power consumption. The internal circuit is compo­ sed of 3 , : M 54HCT00F1R M 74HCT00M 1R M 74HCT00B1R M 74HCT00C1R PIN CONNECTIONS (top view) This , components. They are also plug in replace­ ments for LSTTL devices giving a reduction of po­ wer , L L H L H H H L H H H L PIN DESC RIPTIO N PIN No SYMBOL
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M54HCT00 M74HCT00 M54/74HCT00 M54/74HC

TTL 74HC00

Abstract: 74HCoo . (74HC) â'¢ High noise immunity characteristic of CMOS â'¢ Diode protection on all inputs Pin , identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are , â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL , Suffix-D : Small Outline Package Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB , Logic diagram (one gate) This Material Copyrighted By Its Respective Manufacturer 4-3 GD54/74HC00
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74HCoo 74hc00 tphl tplh tPHL 74hc00 74HCT00 74 LS 00 Logic Gates

pin diagram of ic 74ls00

Abstract: 74LS00 gate diagram DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL , fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output , M74HCT00C1R PIN CONNECTIONS (top view) This integrated circuit has input and output characteristics that , devices giving a reduction of power consumption. INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No
STMicroelectronics
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M54HCT00F1R M74HCT00M1R M74HCT00B1R 74LS00 Electrical and Switching characteristics M74HCT00B1 M54/M74HCT00 P027A

CD4011 internal diagram

Abstract: of 74ls00 offset pins, a 1 iu F decoupling capacitor should be connected as shown on the diagram of Figure 3. MUX , 1 + 2 + 3 -0 -1 -2 -3 MAO 3/4 OF 74LS00 OR CD4011 5~S «-IN3 HN2 h INI -IN3 - IN2 - IN1 , /Hold Circuit 12-Bit A/D 3-State Output Buffer â  40 Pin DIP â  35 kHz Throughput â  Low Power , over-voltage input protection (to ± 35V) and the instrumentation amp provides gain ranges of 1 to 100*. The gain range is selected through the use of a single external resistor and allows a variable FUNCTIONAL
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HI-509A MUX-24 CD4011 internal diagram of 74ls00 CD4011 equivalent pin configuration cd4011 CD4011 PIN DIAGRAM cd40115 HS9404 HI-508A MUX-08

pin diagram of ic 74ls00

Abstract: 74LS00 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset , are in 24-pin packages) ® 5 DAC707/708/709 DISCUSSION OF SPECIFICATIONS DIGITAL INPUT
Burr-Brown
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uv 709 DAC709 16-BIT DAC707JP/KP DAC708/709

74LS00

Abstract: specification of 74ls00 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset , are in 24-pin packages) ® 5 DAC707/708/709 DISCUSSION OF SPECIFICATIONS DIGITAL INPUT
Burr-Brown
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specification of 74ls00 74HTC

pin diagram of ic 74ls00

Abstract: IC TTL 74LS00 ) Bypass, 0.0022µF to 0.01µF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset
Burr-Brown
Original
IC TTL 74LS00 analog devices ic 74LS00 lead side brazed hermetic op amp 709 DAC707KH 709 operational amplifier

pin diagram of ic 74ls00

Abstract: 74ls00 circuit diagram Package) PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE I Io h I = Io l = 4 , same high speed per formance of LSTTL combined with true CM OS low power consumption. The internal circuit is compo sed of 3 stages including buffer output, which ena bles high noise immunity and stable , and NMOS components. They are also plug in replace ments for LSTTL devices giving a reduction of po , T00B1R PIN CONNECTIONS (top view) W - INPUT AND OUTPUT EQUIVALENT CIRCUIT < o o I I _j - -
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of ic 74ls00 74ls00 tr tf T00F1 M54/M

pin diagram of ic 74ls00

Abstract: pin diagram of 74ls00 ) Bypass, 0.0022µF to 0.01µF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset
Burr-Brown
Original
7407 connection diagram 709b
Abstract: ) Bypass, 0.0022µF to 0.01µF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , latch. GA Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13 , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 , (The DAC708 and DAC709 are in 24-pin packages) ® 5 DAC707/708/709 DISCUSSION OF Burr-Brown
Original

74LS00

Abstract: DAC707 ) Bypass, 0.0022µF to 0.01µF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset
Burr-Brown
Original
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