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pin configuration of 74LS154

Catalog Datasheet MFG & Type PDF Document Tags

pin configuration of 74LS154

Abstract: circuit diagram of 74ls154 lOul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 5E 1 [I 2 , Signetics 74154, LS154 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1-of-16 demultiplexer by using one of the enable
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N74LS154N pin configuration of 74LS154 circuit diagram of 74ls154 1 to 16 74154 demultiplexer decoder 74154 pin configuration of 74154 N74154N 1N916 1N3064

pin configuration of 74LS154

Abstract: 74LS154 GD54/74LS154 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS Feature · Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs · Performs the Demultiplexing Function by Distributing Data from One Input Line to Any One of 16 Outputs · Input Clamping Diodes Simplify System Design · High Fan-Out, Low-lmpedance, Totem-Pole Outputs · Fully Compatible with Most TTL, DTL and MSI Circuits Pin Configuration A B C D G2 G1 15 14 13 12 0 1 2 3 11 n- 4 - 5
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pin diagram of 74ls154 OF 74LS154 74LS1S4 74LS154 decoder GD54/74LS154

TTL 74154

Abstract: pin configuration of 74154 ln_. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) à E Hl vcc ï Å' m *o 2d iE , Signetics 74154, LS154 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1-of-16 demultiplexer by using one of the enable , state of the applied data. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74154 21ns
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TTL 74154 74154 74154 demultiplexer 74154 decoder decoder 74LS154 pin diagram decoder 74154 WF075WS

1 to 16 74154 demultiplexer

Abstract: 74LS154 decoder 1ul 10ut 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) ·E , Signetics 74154 , LSI54 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a l-of-16 demultiplexer by using one of the enable
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max3633 74154 24 pins N74LS154 WF07S70S WF075MS

pin configuration of 74LS154

Abstract: ic 74ls154 static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1-of-16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of manufacturers in both Mix-MOS and CMOS technologies , density > > On board 1-of-16 Decoder > > Completely Static operation > > TTL compatible > > Low power
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74F154 ic 74ls154 74hct154 128K X 8 BIT LOW POWER CMOS SRAM 1 of 16 Decoder 74HC154 AEPSX512K8 74HCT154 74HC154

Demultiplexer IC 74154

Abstract: decoder IC 74154 and -0.4mA I|l- PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 5 E îE i\r *E , Signetìcs 74154, LS154 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1-of-16 demultiplexer by using one of the enable
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Demultiplexer IC 74154 decoder IC 74154 IC 74154 IC 74154 pin diagram decoder IC 74154 pin diagram cI 74154

Advanced Electronic Packaging

Abstract: 74F154 m aximize bit density > > On board 1-of-16 D eco d er > > Com pletely Static operation > > TTL com , high density 512 Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1-of-16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of
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Advanced Electronic Packaging 512K x 8 bit Low Power CMOS Static RAM 512 x 8 static ram
Abstract: > > Double sided to maximize bit density > > On board 1-of-16 Decoder > > Completely Static operation , AEPSX512K8 is a high density 512 Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1-of-16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of -
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HCT154

74ls154

Abstract: yl-63 fail to connect ADC pin to Vqq or GND when using. Fig. 6 shows the relations between Y address of RAM , > Page 6 DB7 DBO e Page 7 DB7 X = 6 X = 7 Fig. 8 Address Configuration of Display Data RAM 13 , . 15 HD 61202 b) Example of connection with HD6801 74LS154 PIO Pli P12 P13 (lOS)SCl (R/W)SC2 P14 , driving signals. Each bit data of display RAM corresponds to ON/OFF of each dot of liquid crystal display , liquid crystal graphic display system configuration by combining the row (common) driver HD61203. â
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HD61202 yl-63 LS2074 61202 D-82166 HD6800
Abstract: density > > On board 1-of-16 Decoder > > Completely Static operation > > TTL compatible » Low , Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1-of-16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of manufacturers in both Mix-MOS -
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DSS47T3

1 to 16 74154 demultiplexer

Abstract: TTL 74154 l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 3 E El vcc ' Å' H] *0 1[T 11 *1 , Sgnetics 74154, LS154 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1-of-16 demultiplexer by using one of the enable , state of the applied data. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74154 21ns
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74154 pin diagram 74154 ci 74154 n WF07570S WF064S0S

pin configuration of 74LS154

Abstract: MM74HC pin configuration , and is functionally and pin equivalent to the 54LS154/74LS154. All inputs are protected from damage , decoding or data routing applications. It possesses high noise immunity, and low power consumption of CMOS , inputs (A, B, C, and D). If the device is enabled these inputs determine which one of the 16 normally high outputs will go low. Two active low enables (GT and G2) are provided to ease cascading of decoders , (V0ut) - 0.5 to VCc + 0.5V Clamp Diode Current (I|k, Iok) ±20 mA DC Output Current, per pin (Iout) Â
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MM54HC154 MM74HC154 MM74HC pin configuration T55B D2132 G1.L MM54HC154J 54HC MM54HC154/MM74HC154 54LS154/74LS154 TL/F/5122-1

HITACHI hd6303

Abstract: HD6303 liquid crystal graphic display system configuration. Pin Arrangement Z ü iiiiè îïiis s ii Ym Ym Y li , further details on HD6800 and HD6801, refer to their manuals. 74LS154 Figure 8 Example of Connection , state of each dot o f a liquid crystal display to provide more flexible than character display. The , Information Type No. HD44102CH HD44102D Package 80-pin plastic OFP(FP-80) Chip · · · · · · · , of 65 Hz, in checker pattern display. Access from the CPU is stopped. 12. Measured by terminal at no
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HD6303 HITACHI hd6303 HD44102------------------------ HD44103CH HD44102 HD44I02

HD44102CH

Abstract: HD44103CH P30-P37 are used as the data bus. â'¢ The 74LS154 is a 4-to-16 decoder that decodes 4 bits of P10-P13 to , dot matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of each dot of a liquid crystal display to provide more flexible than character display. The HD44102CH is produced by the CMOS process. Therefore, the combination of HD44102CH with a CMOS , dissipation. The combination of HD44102CH with the row (common) driver HD44103CH facilitates dot matrix
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MSB808 HD44102CH* application h06303 1S2074 B204 work of 74ls154 D44102- A2-A15

HD44102

Abstract: HD6303 P30­P37 are used as the data bus. · The 74LS154 is a 4-to-16 decoder that decodes 4 bits of P10­P13 to , crystal driving signals. Each bit data of display RAM corresponds to on/off state of each dot of a liquid , process. Therefore, the combination of HD44102 with a CMOS microcontroller can complete portable battery-driven unit utilizing the liquid crystal display's low power dissipation. The combination of HD44102 with , configuration. Features · Dot matrix liquid crystal graphic display column driver incorporating display RAM
Hitachi Semiconductor
Original
HD44103 THT-21

HD44102CH

Abstract: HD6303 crystal graphic display system configuration. Pin Arrangement |gtelgfcM eblgto:isi«igisi8i8i Y* Y , , Read Status Low power dissipation Power supplies: V ^ S V ± 10%, V ^ O t o - 5 V CMOS process 80-pin , load, at 1/32 dury factor, and frame frequency of 65 Hz, in checker pattern display. Access from the , of 65 Hz. HITACHI 220 Hitachi America, Ltd. · Hitachi Plaza · 2000 Sierra Point Pkwy. · Brisbane , time Wr t, 1.0 - - 200 US ns Pin Description Pin Name Pin Number I/O Function
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44102CH hitachi hd44102 ch display
Abstract: , refer to their manuals. 74LS154 Figure 8 Example of Connection to HD6801 HITACHI Hitachi , ) Description Pin Arrangement The HD44102CH is a column (segment) driver for dot matrix liquid crystal , crystal graphic display system configuration. HITACHI 216 Hitachi America, Ltd. â'¢ Hitachi Plaza â , V ± 10%, Va 0 to - 5 V CMOS process 80-pin flat plastic package HITACHI Hitachi America, Ltd , output load, at 1/32 dury factor, and fram e frequency of 65 Hz, in checker pattern display. Access from -
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44102C

real time microprocessor 8253 applications

Abstract: 8253 timer CS must be controllable from the first four addresses shown in Table 1, thus the configuration of , trace is the narrowed pulse at pin 3 (U19A) 74LS08. The bottom trace from pin 17 of the 8253 is the , . Additionally, C language code is provided to allow sampling of data at speeds of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can , section is detailed in Figure 4. The second part of the application note describes the software written
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LTC1099 real time microprocessor 8253 applications 8253 timer 8253 OX307 u1 74ls245 intel microprocessor 8253 applications DC-20 LTC1064-1 AN34-11

HD61202

Abstract: decoder 74LS154 DB7 X - 6 X-7 5 Figure 9 Address Configuration of Display Data RAM * HITACHI Hitachi America, Ltd. â , driving signais. Each bit data of display RAM corresponds to the on/off state of a dot of a liquid crystal , facilitate dot matrix liquid crystal graphie display system configuration in combination with the row (common , crystal panels with 1/32-1/64 duty cycle multiplexing Wide range of instruction function: Display Data , 17.0 V â'¢ CMOS process â'¢ 100-pin fiat plastic package (FP-100) 5 HITACHI Hitachi America, Ltd. â
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HD61202- COM65 COM66 COM64 COMI28
Abstract: fail to connect ADC pin to Vcc or GND when using. Figure 3 shows the relations between Y address of RAM , X=0 I X= 1 X = 6 X=7 Figure 5 Address Configuration of Display Data RAM HITACHI , SCI and R/W signal from SC2. For details of HD6800 and HD6801, refer to their manuals. · 74LS154 , matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display to provide more flexible than character display. As it is internally -
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HD61202U HD61203U
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