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SN7496N Texas Instruments SN7496 16-PDIP 0 to 70
SN7496N-10 Texas Instruments TTL/H/L SERIES, 5-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16
SN7496J Texas Instruments IC TTL/H/L SERIES, 5-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
SN7496J-00 Texas Instruments TTL/H/L SERIES, 5-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16
SN7496N-00 Texas Instruments TTL/H/L SERIES, 5-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16
TDA7496 STMicroelectronics 5 W + 5 W amplifier with DC volume control

pin configuration of 7496 IC

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Signelics 7496, LS96 Shift Registers 5-Bit Shift Register Product Specification Logic , preset entry · Buffered positive-triggered clock · Buffered active LOW Clear (Master Reset) TYPE 7496 , the '96 has the output of each stage available as well as a D-type serial input and ones transfer , flipflops change state on the LOW-to-HIGH transition of the clock. The Serial (S) input is edge-triggered , 40/uA I(h and -1.6m A l)L, and a 74LS unit load (LSul) is 20/iA l|H and -0.4m A l(i_. PIN -
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74LS96 ic 7496 pin diagram of 7496 ic 7496 7496 truth table IC 74LS96 N7496N N74LS96N 1N916 1N3064
Abstract: used when ordering. Pin Configuration ISL71090SEH75 (8 LD FLATPACK) TOP VIEW 1 DNC 8 , triangular mark is indicative of pin #1. It is a part of the device marking and is placed on the lid in the , by adding a capacitor from COMP pin to GND. See Table 1 for recommended values. of the COMP , pin one identification mark is used in addition to a tab, the limits of the tab dimension do not , 1.0ÂuVP-P noise at 0.1Hz with an accuracy over temperature of 0.15%. â'¢ Reference output voltage . . . Intersil
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APPLICATION OF IC 7492 FN8591
Abstract: used when ordering. Pin Configuration ISL71090SEH75 (8 LD FLATPACK) TOP VIEW DNC 1 8 , triangular mark is indicative of pin #1. It is a part of the device marking and is placed on the lid in the , by adding a capacitor from COMP pin to GND. See Table 1 for recommended values. of the COMP , pin one identification mark is used in addition to a tab, the limits of the tab dimension do not , 1.0ÂuVP-P noise at 0.1Hz with an accuracy over temperature and radiation of 0.15%. â'¢ Reference output Intersil
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Abstract: the output. All specifications for this device are guaranteed at 5 V and 850 MHz. Because of the high , configuration with built-in source capacitor · Package: 4PSOP PACKAGE DIMENSIONS 1 . 8 +0.1 0.85+0.05 , Lead fram e m aterial Pin treatm ent S old er plate thickness Epoxy resin 42 alloy Sold er , - - - -4 5 Max. 10 6 300 150 125 Tch Tstg ELEC TR IC A L CH ARACTERISTICS (Ta = 25 , 0 -1 0 0 10 20 Input Power P(N (dBm) KGF1183 Pqj IM3 snd IM ^ vs. Pin 50 VD[>=3V 350MHz, f -
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d 7377 amplifier E2Q0022-38-71
Abstract: com bined with the pin configuration m ake this device ideal for balanced or mirrored applications , higher density designs. ~ 2 - 2 2 .o .o s 4 (All Leads) PIN CONFIGURATION (Top View) PIN , ) n n n u u u Note: E2 62 Pin 3 is identified with a circle on the bottom of the package , emitter connected to guard pin of capacitances meter. 3-282 UPA827TF ABSOLUTE MAXIMUM RATINGS1 (Ta , _ · HIGH GAIN WITH LOW OPERATING CURRENT: IS 2 1 EI2 = 9 dB T Y P a t f = 2 G H z, V ce = 2 V, Ic = 7 -
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9013 npn transistor pin view 15251 NEC 14324 ic ma 4810 hfe 4538 IC 7432 UPA827TF-T1
Abstract: range of wavelength. x identifies the pin 1 position. OS1 DS1 OG ø R1 ø 2D ø 1D VSS ø 1A , R 21 Connect a 0.01uF capacitor between the VCC 4 and GND pins of each TTL IC (C19 to C27). 4.7k , The circuit configuration of this part is the same as the OS1 side amplifier. (R49 ~ R63,C50 ~ C61 , s Overview s Pin Assignments The MN3666A is a high-speed high-resolution CCD linear image , registers for read out are integrated in a single chip. · Use of photodiodes with a new structure has Panasonic
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LH0032CG pin diagram of ic 7495 shift register ic 7495 shift registers 7498 4 bit storage register of Shift Register IC 7495 7498 pin configuration 7495 shift register 7500-B WDIP022-C-0400D 2SC828A
Abstract: sity designs. 4 PIN CONFIGURATION B1 E2 B2 (Top View) PIN CO NNECTIO NS 1. Collector (Q1) 2 , : Pin 3 is identified with a circle on the bottom of the package. ELECTRICAL CHARACTERISTICS (Ta = 25 , capacitance m eter (autom atic balanced bridge method), with em itter connected to guard pin of capacitances , _ · HIGH GAIN WITH LOW OPERATING CURRENT: |S 2 ie |2 = 9 dB T Y P at f = 2 G Hz, V ce = 2 V, Ic = 7 m A |S2ie |2 = 8.5 dB T Y P at f = 2 G Hz, V ce = 1 V, Ic = 5 m A PACKAGE DRAWING (Units in mm) P -
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NEC 7815 nec 9531 transistor npn c 9013 LT 5242 lt 7209 ls 7432 IC pin configuration
Abstract: R 21 Connect a 0.01uF capacitor between the VCC 4 and GND pins of each TTL IC (C19 to C27). 4.7k , The circuit configuration of this part is the same as the OS1 side amplifier. (R49 ~ R63,C50 ~ C61 , s Pin Assignments M Di ain sc te on na tin nc ue e/ d s Overview The MN3666A is a , for visible light inputs over a wide range of wavelength. nt in ue Pl pl d in ea an c se , n. s Features x identifies the pin 1 position. OS1 DS1 OG ø R1 ø 2D ø 1D VSS ø 1A Panasonic
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ttl 7498 pin diagram of ic shift registers 7495 traffic light using 68K ic 7495 shift register LS76 LS37
Abstract: large output at a high S/N ratio for visible light inputs over a wide range of wavelength. s Pin Assignments x identifies the pin 1 position. M Di ain sc te on na tin nc ue e/ d s Features · 7500 , pins of each TTL IC (C19 to C27). 4.7k × 2 A stands for the following circuit. 10 (R 23 to R28) 15uF , C 41 15uF R44 100 C49 0.01uF GND The circuit configuration of this part is the same as , chip. · Use of photodiodes with a new structure has made the dark output voltage very low. · An Panasonic
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Q22-Q25 7498 4 bit 7498 ttl 7498 register 7498 ic
Abstract: combined with the pin configuration make this device ideal for balanced or mirrored applications. This , balanced bridge method), with emitter connected to guard pin of capacitances meter. California Eastern , designs. 0.6 ± 0.1 0.45 0.22 - 0.05 (All Leads) 0.13 ± 0.05 0 ~ 0.1 Note: Pin 1 is the lower left most pin as the package lettering is oriented and read left to right. PIN CONNECTIONS 1 , Cutoff Current at VEB = 1 V, IC = 0 uA hFE DC Current Gain1 at VCE = 2 V, IC = 7 mA fT -
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NE686 IC 7448 pin configuration ic 7448 pin configuration of ic 7448 ic LC 7815 C 4804 transistor S21E
Abstract: locations on the wafer. These features combined with the pin configuration make this device ideal for , balanced bridge method), with emitter connected to guard pin of capacitances meter , package style allows for higher density designs. 0.6 ± 0.1 0.45 0.13 ± 0.05 0 ~ 0.1 Note: Pin 1 is the lower left most pin as the package lettering is oriented and read left to right. PIN , Cutoff Current at VEB = 1 V, IC = 0 A hFE DC Current Gain1 at VCE = 2 V, IC = 7 mA fT Gain California Eastern Laboratories
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UPA827TF-T1-A 8 pin ic 3842 LB 9051
Abstract: large output at a high S/N ratio for visible light inputs over a wide range of wavelength. s Pin Assignments x identifies the pin 1 position. M Di ain sc te on na tin nc ue e/ d s Features · 7500 , 0.01uF capacitor between the VCC 4 and GND pins of each TTL IC (C19 to C27). 4.7k × 2 A stands for the , circuit configuration of this part is the same as the OS1 side amplifier. (R49 ~ R63,C50 ~ C61,Q22 ~ Q25 , chip. · Use of photodiodes with a new structure has made the dark output voltage very low. · An Panasonic
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R-786
Abstract: mold part No. Q2 2SC4959 2SC4226 PIN CONFIGURATION (Top View) B1 The uPA832TF features , , IC = 7 mA PACKING STYLE 8-mm wide embossed tape. Pin 6 (Q1 Base), pin 5 (Q2 Emitter), and pin 4 (Q2 Base) face perforated side of tape. 2 3 C1 E1 C2 PIN CONNECTIONS 1. Collector , method), with emitter connected to guard pin of capacitance meter. 2 pF dB uPA835TF (2) Q2 , guard pin of capacitance meter. hFE CLASSIFICATION Rank Marking FB V37 hFE value of Q1 75 NEC
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3692 nec PA835TF PA832TF PA835TF-T1
Abstract: , Ic = 7 mA · · 6-pin thin-type small mini mold package 2 different transistors on-chip (2SC4959 , ON-CHIP TRANSISTORS Q1 3-pin small mini mold part No. 2SC4959 Q2 2SC4226 PIN CONFIGURATION (Top View , perforated side of tape. 1 CTO E1 C2 4. Base (Q2) 5. Emitter (Q2) 6. Base (Q1 ) C1 PIN CONNECTIONS , measured with capacitance meter (automatic balanced bridge method), with emitter connected to guard pin of , meter (automatic balanced bridge method), with emitter connected to guard pin of capacitance meter -
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sem 5025 ic 4440 for audio amplification pe 5571 NEC 9736
Abstract: in the bipolar configuration.(Jumper pin 16 to pin 19 for uni polar, or pin 21 to pin 22 for bipolar , output (taken from the output of a T TL flip-flop) is brought out to pin 26. The data is transmitted M SB , temperature range, and has a maximum relative accuracy error of i ' /aLSB. The unit is packaged in a convenient, small, low profile module. All of its logic inputs and outputs are fully TTL/DTL compatible. U S E R F L E X IB IL IT Y The ADC-10Z is designed for flexibility and ease of use. It contains an -
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SN7496
Abstract: thin-type small mini mold package 0.45 0.60±0.1 @f = 1 GHz, VCE = 3 V, IC = 7 mA PIN , 5 (Q2 Emitter), and pin 4 (Q2 Base) face perforated side of tape. 2 3 C1 E1 C2 , with capacitance meter (automatic balanced bridge method), with emitter connected to guard pin of , balanced bridge method), with emitter connected to guard pin of capacitance meter. hFE CLASSIFICATION , DIFFERENT ELEMENTS) IN A 6-PIN THIN-TYPE SMALL MINI MOLD PACKAGE PACKAGE DRAWINGS (Unit:mm) The NEC
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2SC4227 nec 14312 transistor nec 7912 ic 5219 8mm 21 01 140 5091 configuration of ic 7819 4440 audio ic PA834TF PA831TF PA834TF-T1
Abstract: CONFIGURATION (Top View) B1 E2 6 5 Q1 ORDERING INFORMATION PART NUMBER 0.45 Q2 nt 3-pin , tape. Pin 6 (Q1 Base), pin 5 (Q2 Emitter), and pin 4 (Q2 Base) face perforated side of tape. 2 , method), with emitter connected to guard pin of capacitance meter. 2 pF dB uPA835TF (2) Q2 , method), with emitter connected to guard pin of capacitance meter. hFE CLASSIFICATION V37 75 to , over all the business of both companies. Therefore, although the old company name remains in this Renesas Electronics
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ic 4075 NT 2955 ON transistor
Abstract: NEC Sales Representative (Unit sample quantity is 50 pcs). PIN CONFIGURATION (Top View) ABSOLUTE , Emitter should be connected to the guard pin of capacitance meter. hFE CLASSIFICATION Rank Marking hFE , SILICON EPITAXIAL TWIN TRANSISTOR (WITH BUILT-IN 6-PIN 2 x 2SC5184) THIN-TYPE SMALL MINI MOLD FEATURES · Low noise NF = 1 .3 dB TYP. @ V ce = 2 V, Ic = 3 mA, f = 2 GHz NF = 1.3 dB TYP. @ V ce = 1 V, Ic = 3 mA, f = 2 GHz · · 6-pin thin-type small mini mold package adopted Built-in 2 transistors (2 x -
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nec 16312 ha 13463 SN 16880 7082 B ic audio amplifier 8377 om nec 8039 PA828TF PA828TF-T1
Abstract: ), Pin 5 (Q2 Emitter), Pin 4 (Q2 Base) face to perforation side of the tape. 0 to 0.1 Loose , is 50 pcs). PIN CONFIGURATION (Top View) ABSOLUTE MAXIMUM RATINGS (TA = 25qC) q Parameter B1 , Emitter should be connected to the guard pin of capacitance meter. hFE CLASSIFICATION Rank FB , over all the business of both companies. Therefore, although the old company name remains in this , current as of the date this document is issued. Such information, however, is subject to change without Renesas Electronics
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D1650 D1138 D1138 transistor transistor D1138 D1589 D4204
Abstract: cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS. A+PLUS includes the A ltera Design Processor (ADP), w hich consists of integ rated m od u les that -
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truth table for ic 74138 16CUDSLR IC 74151 diagram and truth table ALU IC 74183 74183 alu 74147 pin diagram and truth table
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